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Viewing changes to src/mame/machine/leland.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/machine/leland.c
81
81
 *
82
82
 *************************************/
83
83
 
84
 
READ8_HANDLER( cerberus_dial_1_r )
 
84
READ8_MEMBER(leland_state::cerberus_dial_1_r)
85
85
{
86
 
        int original = input_port_read(space->machine(), "IN0");
87
 
        int modified = dial_compute_value(space->machine(), input_port_read(space->machine(), "AN0"), 0);
 
86
        int original = ioport("IN0")->read();
 
87
        int modified = dial_compute_value(machine(), ioport("AN0")->read(), 0);
88
88
        return (original & 0xc0) | ((modified & 0x80) >> 2) | (modified & 0x1f);
89
89
}
90
90
 
91
91
 
92
 
READ8_HANDLER( cerberus_dial_2_r )
 
92
READ8_MEMBER(leland_state::cerberus_dial_2_r)
93
93
{
94
 
        int original = input_port_read(space->machine(), "IN0");
95
 
        int modified = dial_compute_value(space->machine(), input_port_read(space->machine(), "AN1"), 1);
 
94
        int original = ioport("IN0")->read();
 
95
        int modified = dial_compute_value(machine(), ioport("AN1")->read(), 1);
96
96
        return (original & 0xc0) | ((modified & 0x80) >> 2) | (modified & 0x1f);
97
97
}
98
98
 
105
105
 *************************************/
106
106
 
107
107
 
108
 
WRITE8_HANDLER( alleymas_joystick_kludge )
 
108
WRITE8_MEMBER(leland_state::alleymas_joystick_kludge)
109
109
{
110
 
        leland_state *state = space->machine().driver_data<leland_state>();
111
110
        /* catch the case where they clear this memory location at PC $1827 and change */
112
111
        /* the value written to be a 1 */
113
 
        if (cpu_get_previouspc(&space->device()) == 0x1827)
114
 
                *state->m_alleymas_kludge_mem = 1;
 
112
        if (cpu_get_previouspc(&space.device()) == 0x1827)
 
113
                *m_alleymas_kludge_mem = 1;
115
114
        else
116
 
                *state->m_alleymas_kludge_mem = data;
 
115
                *m_alleymas_kludge_mem = data;
117
116
 
118
117
        /* while we're here, make sure the first 3 characters in battery RAM are a */
119
118
        /* valid name; otherwise, it will crash if you start a game and don't enter */
120
119
        /* your name */
121
 
        if (state->m_battery_ram[0] == 0)
 
120
        if (m_battery_ram[0] == 0)
122
121
        {
123
 
                state->m_battery_ram[0] = 'C';
124
 
                state->m_battery_ram[1] = 'I';
125
 
                state->m_battery_ram[2] = 'N';
 
122
                m_battery_ram[0] = 'C';
 
123
                m_battery_ram[1] = 'I';
 
124
                m_battery_ram[2] = 'N';
126
125
        }
127
126
}
128
127
 
137
136
static void update_dangerz_xy(running_machine &machine)
138
137
{
139
138
        leland_state *state = machine.driver_data<leland_state>();
140
 
        UINT8 newy = input_port_read(machine, "AN0");
141
 
        UINT8 newx = input_port_read(machine, "AN1");
 
139
        UINT8 newy = state->ioport("AN0")->read();
 
140
        UINT8 newx = state->ioport("AN1")->read();
142
141
        int deltay = newy - state->m_dial_last_input[0];
143
142
        int deltax = newx - state->m_dial_last_input[1];
144
143
 
159
158
}
160
159
 
161
160
 
162
 
READ8_HANDLER( dangerz_input_y_r )
163
 
{
164
 
        leland_state *state = space->machine().driver_data<leland_state>();
165
 
        update_dangerz_xy(space->machine());
166
 
        return state->m_dangerz_y & 0xff;
167
 
}
168
 
 
169
 
 
170
 
READ8_HANDLER( dangerz_input_x_r )
171
 
{
172
 
        leland_state *state = space->machine().driver_data<leland_state>();
173
 
        update_dangerz_xy(space->machine());
174
 
        return state->m_dangerz_x & 0xff;
175
 
}
176
 
 
177
 
 
178
 
READ8_HANDLER( dangerz_input_upper_r )
179
 
{
180
 
        leland_state *state = space->machine().driver_data<leland_state>();
181
 
        update_dangerz_xy(space->machine());
182
 
        return ((state->m_dangerz_y >> 2) & 0xc0) | ((state->m_dangerz_x >> 8) & 0x03);
 
161
READ8_MEMBER(leland_state::dangerz_input_y_r)
 
162
{
 
163
        update_dangerz_xy(machine());
 
164
        return m_dangerz_y & 0xff;
 
165
}
 
166
 
 
167
 
 
168
READ8_MEMBER(leland_state::dangerz_input_x_r)
 
169
{
 
170
        update_dangerz_xy(machine());
 
171
        return m_dangerz_x & 0xff;
 
172
}
 
173
 
 
174
 
 
175
READ8_MEMBER(leland_state::dangerz_input_upper_r)
 
176
{
 
177
        update_dangerz_xy(machine());
 
178
        return ((m_dangerz_y >> 2) & 0xc0) | ((m_dangerz_x >> 8) & 0x03);
183
179
}
184
180
 
185
181
 
192
188
 
193
189
static const UINT8 redline_pedal_value[8] = { 0xf0, 0xe0, 0xc0, 0xd0, 0x90, 0xb0, 0x30, 0x70 };
194
190
 
195
 
READ8_HANDLER( redline_pedal_1_r )
196
 
{
197
 
        int pedal = input_port_read(space->machine(), "IN0");
198
 
        return redline_pedal_value[pedal >> 5] | 0x0f;
199
 
}
200
 
 
201
 
 
202
 
READ8_HANDLER( redline_pedal_2_r )
203
 
{
204
 
        int pedal = input_port_read(space->machine(), "IN2");
205
 
        return redline_pedal_value[pedal >> 5] | 0x0f;
206
 
}
207
 
 
208
 
 
209
 
READ8_HANDLER( redline_wheel_1_r )
210
 
{
211
 
        return dial_compute_value(space->machine(), input_port_read(space->machine(), "AN0"), 0);
212
 
}
213
 
 
214
 
 
215
 
READ8_HANDLER( redline_wheel_2_r )
216
 
{
217
 
        return dial_compute_value(space->machine(), input_port_read(space->machine(), "AN1"), 1);
 
191
READ8_MEMBER(leland_state::redline_pedal_1_r)
 
192
{
 
193
        int pedal = ioport("IN0")->read();
 
194
        return redline_pedal_value[pedal >> 5] | 0x0f;
 
195
}
 
196
 
 
197
 
 
198
READ8_MEMBER(leland_state::redline_pedal_2_r)
 
199
{
 
200
        int pedal = ioport("IN2")->read();
 
201
        return redline_pedal_value[pedal >> 5] | 0x0f;
 
202
}
 
203
 
 
204
 
 
205
READ8_MEMBER(leland_state::redline_wheel_1_r)
 
206
{
 
207
        return dial_compute_value(machine(), ioport("AN0")->read(), 0);
 
208
}
 
209
 
 
210
 
 
211
READ8_MEMBER(leland_state::redline_wheel_2_r)
 
212
{
 
213
        return dial_compute_value(machine(), ioport("AN1")->read(), 1);
218
214
}
219
215
 
220
216
 
225
221
 *
226
222
 *************************************/
227
223
 
228
 
READ8_HANDLER( offroad_wheel_1_r )
229
 
{
230
 
        return dial_compute_value(space->machine(), input_port_read(space->machine(), "AN3"), 0);
231
 
}
232
 
 
233
 
 
234
 
READ8_HANDLER( offroad_wheel_2_r )
235
 
{
236
 
        return dial_compute_value(space->machine(), input_port_read(space->machine(), "AN4"), 1);
237
 
}
238
 
 
239
 
 
240
 
READ8_HANDLER( offroad_wheel_3_r )
241
 
{
242
 
        return dial_compute_value(space->machine(), input_port_read(space->machine(), "AN5"), 2);
 
224
READ8_MEMBER(leland_state::offroad_wheel_1_r)
 
225
{
 
226
        return dial_compute_value(machine(), ioport("AN3")->read(), 0);
 
227
}
 
228
 
 
229
 
 
230
READ8_MEMBER(leland_state::offroad_wheel_2_r)
 
231
{
 
232
        return dial_compute_value(machine(), ioport("AN4")->read(), 1);
 
233
}
 
234
 
 
235
 
 
236
READ8_MEMBER(leland_state::offroad_wheel_3_r)
 
237
{
 
238
        return dial_compute_value(machine(), ioport("AN5")->read(), 2);
243
239
}
244
240
 
245
241
 
250
246
 *
251
247
 *************************************/
252
248
 
253
 
READ8_HANDLER( ataxx_trackball_r )
 
249
READ8_MEMBER(leland_state::ataxx_trackball_r)
254
250
{
255
251
        static const char *const tracknames[] = { "AN0", "AN1", "AN2", "AN3" };
256
252
 
257
 
        return dial_compute_value(space->machine(), input_port_read(space->machine(), tracknames[offset]), offset);
 
253
        return dial_compute_value(machine(), ioport(tracknames[offset])->read(), offset);
258
254
}
259
255
 
260
256
 
265
261
 *
266
262
 *************************************/
267
263
 
268
 
READ8_HANDLER( indyheat_wheel_r )
 
264
READ8_MEMBER(leland_state::indyheat_wheel_r)
269
265
{
270
266
        static const char *const tracknames[] = { "AN0", "AN1", "AN2" };
271
267
 
272
 
        return dial_compute_value(space->machine(), input_port_read(space->machine(), tracknames[offset]), offset);
 
268
        return dial_compute_value(machine(), ioport(tracknames[offset])->read(), offset);
273
269
}
274
270
 
275
271
 
276
 
READ8_HANDLER( indyheat_analog_r )
 
272
READ8_MEMBER(leland_state::indyheat_analog_r)
277
273
{
278
 
        leland_state *state = space->machine().driver_data<leland_state>();
279
274
        switch (offset)
280
275
        {
281
276
                case 0:
282
277
                        return 0;
283
278
 
284
279
                case 1:
285
 
                        return state->m_analog_result;
 
280
                        return m_analog_result;
286
281
 
287
282
                case 2:
288
283
                        return 0;
295
290
}
296
291
 
297
292
 
298
 
WRITE8_HANDLER( indyheat_analog_w )
 
293
WRITE8_MEMBER(leland_state::indyheat_analog_w)
299
294
{
300
 
        leland_state *state = space->machine().driver_data<leland_state>();
301
295
        static const char *const tracknames[] = { "AN3", "AN4", "AN5" };
302
296
 
303
297
        switch (offset)
304
298
        {
305
299
                case 3:
306
 
                        state->m_analog_result = input_port_read(space->machine(), tracknames[data]);
 
300
                        m_analog_result = ioport(tracknames[data])->read();
307
301
                        break;
308
302
 
309
303
                case 0:
326
320
{
327
321
        leland_state *state = machine.driver_data<leland_state>();
328
322
        /* allocate extra stuff */
329
 
        state->m_battery_ram = reinterpret_cast<UINT8 *>(memory_get_shared(machine, "battery"));
 
323
        state->m_battery_ram = reinterpret_cast<UINT8 *>(state->memshare("battery")->ptr());
330
324
 
331
325
        /* start scanline interrupts going */
332
326
        state->m_master_int_timer = machine.scheduler().timer_alloc(FUNC(leland_interrupt_callback));
360
354
        state->m_alternate_bank = 0;
361
355
 
362
356
        /* initialize the master banks */
363
 
        state->m_master_length = machine.region("master")->bytes();
364
 
        state->m_master_base = machine.region("master")->base();
 
357
        state->m_master_length = state->memregion("master")->bytes();
 
358
        state->m_master_base = state->memregion("master")->base();
365
359
        (*state->m_update_master_bank)(machine);
366
360
 
367
361
        /* initialize the slave banks */
368
 
        state->m_slave_length = machine.region("slave")->bytes();
369
 
        state->m_slave_base = machine.region("slave")->base();
 
362
        state->m_slave_length = state->memregion("slave")->bytes();
 
363
        state->m_slave_base = state->memregion("slave")->base();
370
364
        if (state->m_slave_length > 0x10000)
371
 
                memory_set_bankptr(machine, "bank3", &state->m_slave_base[0x10000]);
 
365
                state->membank("bank3")->set_base(&state->m_slave_base[0x10000]);
372
366
}
373
367
 
374
368
 
376
370
{
377
371
        leland_state *state = machine.driver_data<leland_state>();
378
372
        /* set the odd data banks */
379
 
        state->m_battery_ram = reinterpret_cast<UINT8 *>(memory_get_shared(machine, "battery"));
 
373
        state->m_battery_ram = reinterpret_cast<UINT8 *>(state->memshare("battery")->ptr());
380
374
        state->m_extra_tram = auto_alloc_array(machine, UINT8, ATAXX_EXTRA_TRAM_SIZE);
381
375
 
382
376
        /* start scanline interrupts going */
391
385
        state->m_master_int_timer->adjust(machine.primary_screen->time_until_pos(8), 8);
392
386
 
393
387
        /* initialize the XROM */
394
 
        state->m_xrom_length = machine.region("user1")->bytes();
395
 
        state->m_xrom_base = machine.region("user1")->base();
 
388
        state->m_xrom_length = state->memregion("user1")->bytes();
 
389
        state->m_xrom_base = state->memregion("user1")->base();
396
390
        state->m_xrom1_addr = 0;
397
391
        state->m_xrom2_addr = 0;
398
392
 
406
400
        state->m_master_bank = 0;
407
401
 
408
402
        /* initialize the master banks */
409
 
        state->m_master_length = machine.region("master")->bytes();
410
 
        state->m_master_base = machine.region("master")->base();
 
403
        state->m_master_length = state->memregion("master")->bytes();
 
404
        state->m_master_base = state->memregion("master")->base();
411
405
        ataxx_bankswitch(machine);
412
406
 
413
407
        /* initialize the slave banks */
414
 
        state->m_slave_length = machine.region("slave")->bytes();
415
 
        state->m_slave_base = machine.region("slave")->base();
 
408
        state->m_slave_length = state->memregion("slave")->bytes();
 
409
        state->m_slave_base = state->memregion("slave")->base();
416
410
        if (state->m_slave_length > 0x10000)
417
 
                memory_set_bankptr(machine, "bank3", &state->m_slave_base[0x10000]);
 
411
                state->membank("bank3")->set_base(&state->m_slave_base[0x10000]);
418
412
}
419
413
 
420
414
 
458
452
INTERRUPT_GEN( leland_master_interrupt )
459
453
{
460
454
        /* check for coins here */
461
 
        if ((input_port_read(device->machine(), "IN1") & 0x0e) != 0x0e)
 
455
        if ((device->machine().root_device().ioport("IN1")->read() & 0x0e) != 0x0e)
462
456
                device_set_input_line(device, INPUT_LINE_NMI, ASSERT_LINE);
463
457
}
464
458
 
470
464
 *
471
465
 *************************************/
472
466
 
473
 
WRITE8_HANDLER( leland_master_alt_bankswitch_w )
 
467
WRITE8_MEMBER(leland_state::leland_master_alt_bankswitch_w)
474
468
{
475
 
        leland_state *state = space->machine().driver_data<leland_state>();
476
469
        /* update any bankswitching */
477
470
        if (LOG_BANKSWITCHING_M)
478
 
                if ((state->m_alternate_bank ^ data) & 0x0f)
479
 
                        logerror("%04X:alternate_bank = %02X\n", cpu_get_pc(&space->device()), data & 0x0f);
480
 
        state->m_alternate_bank = data & 15;
481
 
        (*state->m_update_master_bank)(space->machine());
 
471
                if ((m_alternate_bank ^ data) & 0x0f)
 
472
                        logerror("%04X:alternate_bank = %02X\n", cpu_get_pc(&space.device()), data & 0x0f);
 
473
        m_alternate_bank = data & 15;
 
474
        (*m_update_master_bank)(machine());
482
475
 
483
476
        /* sound control is in the rest */
484
 
        leland_80186_control_w(space->machine().device("custom"), offset, data);
 
477
        leland_80186_control_w(machine().device("custom"), offset, data);
485
478
}
486
479
 
487
480
 
501
494
        state->m_battery_ram_enable = ((state->m_sound_port_bank & 0x24) == 0);
502
495
 
503
496
        address = (!(state->m_sound_port_bank & 0x04)) ? &state->m_master_base[0x10000] : &state->m_master_base[0x1c000];
504
 
        memory_set_bankptr(machine, "bank1", address);
 
497
        state->membank("bank1")->set_base(address);
505
498
 
506
499
        address = state->m_battery_ram_enable ? state->m_battery_ram : &address[0x8000];
507
 
        memory_set_bankptr(machine, "bank2", address);
 
500
        state->membank("bank2")->set_base(address);
508
501
}
509
502
 
510
503
 
517
510
        state->m_battery_ram_enable = ((state->m_top_board_bank & 0x80) != 0);
518
511
 
519
512
        address = (!(state->m_alternate_bank & 1)) ? &state->m_master_base[0x02000] : &state->m_master_base[0x12000];
520
 
        memory_set_bankptr(machine, "bank1", address);
 
513
        state->membank("bank1")->set_base(address);
521
514
 
522
515
        address = state->m_battery_ram_enable ? state->m_battery_ram : &address[0x8000];
523
 
        memory_set_bankptr(machine, "bank2", address);
 
516
        state->membank("bank2")->set_base(address);
524
517
}
525
518
 
526
519
 
536
529
                address = (!(state->m_sound_port_bank & 0x04)) ? &state->m_master_base[0x10000] : &state->m_master_base[0x1c000];
537
530
        else
538
531
                address = (!(state->m_top_board_bank & 0x40)) ? &state->m_master_base[0x28000] : &state->m_master_base[0x30000];
539
 
        memory_set_bankptr(machine, "bank1", address);
 
532
        state->membank("bank1")->set_base(address);
540
533
 
541
534
        address = state->m_battery_ram_enable ? state->m_battery_ram : &address[0x8000];
542
 
        memory_set_bankptr(machine, "bank2", address);
 
535
        state->membank("bank2")->set_base(address);
543
536
}
544
537
 
545
538
 
553
546
        state->m_battery_ram_enable = ((state->m_alternate_bank & 3) == 1);
554
547
 
555
548
        address = &state->m_master_base[bank_list[state->m_alternate_bank & 3]];
556
 
        memory_set_bankptr(machine, "bank1", address);
 
549
        state->membank("bank1")->set_base(address);
557
550
 
558
551
        address = state->m_battery_ram_enable ? state->m_battery_ram : &state->m_master_base[0xa000];
559
 
        memory_set_bankptr(machine, "bank2", address);
 
552
        state->membank("bank2")->set_base(address);
560
553
}
561
554
 
562
555
 
575
568
                logerror("%s:Master bank %02X out of range!\n", machine.describe_context(), state->m_alternate_bank & 3);
576
569
                address = &state->m_master_base[bank_list[0]];
577
570
        }
578
 
        memory_set_bankptr(machine, "bank1", address);
 
571
        state->membank("bank1")->set_base(address);
579
572
 
580
573
        address = state->m_battery_ram_enable ? state->m_battery_ram : &state->m_master_base[0xa000];
581
 
        memory_set_bankptr(machine, "bank2", address);
 
574
        state->membank("bank2")->set_base(address);
582
575
}
583
576
 
584
577
 
597
590
                logerror("%s:Master bank %02X out of range!\n", machine.describe_context(), state->m_alternate_bank & 7);
598
591
                address = &state->m_master_base[bank_list[0]];
599
592
        }
600
 
        memory_set_bankptr(machine, "bank1", address);
 
593
        state->membank("bank1")->set_base(address);
601
594
 
602
595
        address = state->m_battery_ram_enable ? state->m_battery_ram : &state->m_master_base[0xa000];
603
 
        memory_set_bankptr(machine, "bank2", address);
 
596
        state->membank("bank2")->set_base(address);
604
597
}
605
598
 
606
599
 
623
616
                logerror("%s:Master bank %02X out of range!\n", machine.describe_context(), state->m_master_bank & 15);
624
617
                address = &state->m_master_base[bank_list[0]];
625
618
        }
626
 
        memory_set_bankptr(machine, "bank1", address);
 
619
        state->membank("bank1")->set_base(address);
627
620
 
628
621
        if (state->m_battery_ram_enable)
629
622
                address = state->m_battery_ram;
631
624
                address = &state->m_ataxx_qram[(state->m_master_bank & 0xc0) << 8];
632
625
        else
633
626
                address = &state->m_master_base[0xa000];
634
 
        memory_set_bankptr(machine, "bank2", address);
 
627
        state->membank("bank2")->set_base(address);
635
628
 
636
629
        state->m_wcol_enable = ((state->m_master_bank & 0x30) == 0x30);
637
630
}
831
824
 
832
825
READ8_DEVICE_HANDLER( ataxx_eeprom_r )
833
826
{
834
 
        int port = input_port_read(device->machine(), "IN2");
 
827
        int port = device->machine().root_device().ioport("IN2")->read();
835
828
        if (LOG_EEPROM) logerror("%s:EE read\n", device->machine().describe_context());
836
829
        return port;
837
830
}
855
848
 *
856
849
 *************************************/
857
850
 
858
 
WRITE8_HANDLER( leland_battery_ram_w )
 
851
WRITE8_MEMBER(leland_state::leland_battery_ram_w)
859
852
{
860
 
        leland_state *state = space->machine().driver_data<leland_state>();
861
 
        if (state->m_battery_ram_enable)
 
853
        if (m_battery_ram_enable)
862
854
        {
863
 
                if (LOG_BATTERY_RAM) logerror("%04X:BatteryW@%04X=%02X\n", cpu_get_pc(&space->device()), offset, data);
864
 
                state->m_battery_ram[offset] = data;
 
855
                if (LOG_BATTERY_RAM) logerror("%04X:BatteryW@%04X=%02X\n", cpu_get_pc(&space.device()), offset, data);
 
856
                m_battery_ram[offset] = data;
865
857
        }
866
858
        else
867
 
                logerror("%04X:BatteryW@%04X (invalid!)\n", cpu_get_pc(&space->device()), offset);
 
859
                logerror("%04X:BatteryW@%04X (invalid!)\n", cpu_get_pc(&space.device()), offset);
868
860
}
869
861
 
870
862
 
871
 
WRITE8_HANDLER( ataxx_battery_ram_w )
 
863
WRITE8_MEMBER(leland_state::ataxx_battery_ram_w)
872
864
{
873
 
        leland_state *state = space->machine().driver_data<leland_state>();
874
 
        if (state->m_battery_ram_enable)
 
865
        if (m_battery_ram_enable)
875
866
        {
876
 
                if (LOG_BATTERY_RAM) logerror("%04X:BatteryW@%04X=%02X\n", cpu_get_pc(&space->device()), offset, data);
877
 
                state->m_battery_ram[offset] = data;
 
867
                if (LOG_BATTERY_RAM) logerror("%04X:BatteryW@%04X=%02X\n", cpu_get_pc(&space.device()), offset, data);
 
868
                m_battery_ram[offset] = data;
878
869
        }
879
 
        else if ((state->m_master_bank & 0x30) == 0x20)
880
 
                state->m_ataxx_qram[((state->m_master_bank & 0xc0) << 8) + offset] = data;
 
870
        else if ((m_master_bank & 0x30) == 0x20)
 
871
                m_ataxx_qram[((m_master_bank & 0xc0) << 8) + offset] = data;
881
872
        else
882
 
                logerror("%04X:BatteryW@%04X (invalid!)\n", cpu_get_pc(&space->device()), offset);
 
873
                logerror("%04X:BatteryW@%04X (invalid!)\n", cpu_get_pc(&space.device()), offset);
883
874
}
884
875
 
885
876
 
1032
1023
 *
1033
1024
 *************************************/
1034
1025
 
1035
 
READ8_HANDLER( leland_master_analog_key_r )
 
1026
READ8_MEMBER(leland_state::leland_master_analog_key_r)
1036
1027
{
1037
 
        leland_state *state = space->machine().driver_data<leland_state>();
1038
1028
        int result = 0;
1039
1029
 
1040
1030
        switch (offset)
1041
1031
        {
1042
1032
                case 0x00:      /* FD = analog data read */
1043
 
                        result = state->m_analog_result;
 
1033
                        result = m_analog_result;
1044
1034
                        break;
1045
1035
 
1046
1036
                case 0x01:      /* FE = analog status read */
1049
1039
                        break;
1050
1040
 
1051
1041
                case 0x02:      /* FF = keycard serial data read */
1052
 
                        result = keycard_r(space->machine());
 
1042
                        result = keycard_r(machine());
1053
1043
 
1054
1044
                        /* bit 7 indicates the analog input is busy for some games */
1055
1045
                        result &= ~0x80;
1060
1050
 
1061
1051
 
1062
1052
 
1063
 
WRITE8_HANDLER( leland_master_analog_key_w )
 
1053
WRITE8_MEMBER(leland_state::leland_master_analog_key_w)
1064
1054
{
1065
 
        leland_state *state = space->machine().driver_data<leland_state>();
1066
1055
        static const char *const portnames[] = { "AN0", "AN1", "AN2", "AN3", "AN4", "AN5" };
1067
1056
 
1068
1057
        switch (offset)
1071
1060
                        break;
1072
1061
 
1073
1062
                case 0x01:      /* FE = analog port select/bankswitch */
1074
 
                        state->m_analog_result = input_port_read(space->machine(), portnames[data & 15]);
 
1063
                        m_analog_result = ioport(portnames[data & 15])->read();
1075
1064
 
1076
1065
                        /* update top board banking for some games */
1077
1066
                        if (LOG_BANKSWITCHING_M)
1078
 
                                if ((state->m_top_board_bank ^ data) & 0xc0)
1079
 
                                        logerror("%04X:top_board_bank = %02X\n", cpu_get_pc(&space->device()), data & 0xc0);
1080
 
                        state->m_top_board_bank = data & 0xc0;
1081
 
                        (*state->m_update_master_bank)(space->machine());
 
1067
                                if ((m_top_board_bank ^ data) & 0xc0)
 
1068
                                        logerror("%04X:top_board_bank = %02X\n", cpu_get_pc(&space.device()), data & 0xc0);
 
1069
                        m_top_board_bank = data & 0xc0;
 
1070
                        (*m_update_master_bank)(machine());
1082
1071
                        break;
1083
1072
 
1084
1073
                case 0x02:      /* FF = keycard data write */
1085
 
                        keycard_w(space->machine(), data);
 
1074
                        keycard_w(machine(), data);
1086
1075
                        break;
1087
1076
        }
1088
1077
}
1095
1084
 *
1096
1085
 *************************************/
1097
1086
 
1098
 
READ8_HANDLER( leland_master_input_r )
 
1087
READ8_MEMBER(leland_state::leland_master_input_r)
1099
1088
{
1100
1089
        int result = 0xff;
1101
1090
 
1102
1091
        switch (offset)
1103
1092
        {
1104
1093
                case 0x00:      /* /GIN0 */
1105
 
                        result = input_port_read(space->machine(), "IN0");
 
1094
                        result = ioport("IN0")->read();
1106
1095
                        break;
1107
1096
 
1108
1097
                case 0x01:      /* /GIN1 */
1109
 
                        result = input_port_read(space->machine(), "IN1");
1110
 
                        if (cpu_get_reg(space->machine().device("slave"), Z80_HALT))
 
1098
                        result = ioport("IN1")->read();
 
1099
                        if (cpu_get_reg(machine().device("slave"), Z80_HALT))
1111
1100
                                result ^= 0x01;
1112
1101
                        break;
1113
1102
 
1114
1103
                case 0x02:      /* /GIN2 */
1115
1104
                case 0x12:
1116
 
                        cputag_set_input_line(space->machine(), "master", INPUT_LINE_NMI, CLEAR_LINE);
 
1105
                        cputag_set_input_line(machine(), "master", INPUT_LINE_NMI, CLEAR_LINE);
1117
1106
                        break;
1118
1107
 
1119
1108
                case 0x03:      /* /IGID */
1120
1109
                case 0x13:
1121
 
                        result = ay8910_r(space->machine().device("ay8910.1"), offset);
 
1110
                        result = ay8910_r(machine().device("ay8910.1"), offset);
1122
1111
                        break;
1123
1112
 
1124
1113
                case 0x10:      /* /GIN0 */
1125
 
                        result = input_port_read(space->machine(), "IN2");
 
1114
                        result = ioport("IN2")->read();
1126
1115
                        break;
1127
1116
 
1128
1117
                case 0x11:      /* /GIN1 */
1129
 
                        result = input_port_read(space->machine(), "IN3");
1130
 
                        if (LOG_EEPROM) logerror("%04X:EE read\n", cpu_get_pc(&space->device()));
 
1118
                        result = ioport("IN3")->read();
 
1119
                        if (LOG_EEPROM) logerror("%04X:EE read\n", cpu_get_pc(&space.device()));
1131
1120
                        break;
1132
1121
 
1133
1122
                default:
1138
1127
}
1139
1128
 
1140
1129
 
1141
 
WRITE8_HANDLER( leland_master_output_w )
 
1130
WRITE8_MEMBER(leland_state::leland_master_output_w)
1142
1131
{
1143
 
        leland_state *state = space->machine().driver_data<leland_state>();
1144
1132
        eeprom_device *eeprom;
1145
1133
 
1146
1134
        switch (offset)
1147
1135
        {
1148
1136
                case 0x09:      /* /MCONT */
1149
 
                        cputag_set_input_line(space->machine(), "slave", INPUT_LINE_RESET, (data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
1150
 
                        state->m_wcol_enable = (data & 0x02);
1151
 
                        cputag_set_input_line(space->machine(), "slave", INPUT_LINE_NMI, (data & 0x04) ? CLEAR_LINE : ASSERT_LINE);
1152
 
                        cputag_set_input_line(space->machine(), "slave", 0, (data & 0x08) ? CLEAR_LINE : ASSERT_LINE);
 
1137
                        cputag_set_input_line(machine(), "slave", INPUT_LINE_RESET, (data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
 
1138
                        m_wcol_enable = (data & 0x02);
 
1139
                        cputag_set_input_line(machine(), "slave", INPUT_LINE_NMI, (data & 0x04) ? CLEAR_LINE : ASSERT_LINE);
 
1140
                        cputag_set_input_line(machine(), "slave", 0, (data & 0x08) ? CLEAR_LINE : ASSERT_LINE);
1153
1141
 
1154
 
                        eeprom = space->machine().device<eeprom_device>("eeprom");
1155
 
                        if (LOG_EEPROM) logerror("%04X:EE write %d%d%d\n", cpu_get_pc(&space->device()),
 
1142
                        eeprom = machine().device<eeprom_device>("eeprom");
 
1143
                        if (LOG_EEPROM) logerror("%04X:EE write %d%d%d\n", cpu_get_pc(&space.device()),
1156
1144
                                        (data >> 6) & 1, (data >> 5) & 1, (data >> 4) & 1);
1157
1145
                        eeprom->write_bit     ((data & 0x10) >> 4);
1158
1146
                        eeprom->set_clock_line((data & 0x20) ? ASSERT_LINE : CLEAR_LINE);
1161
1149
 
1162
1150
                case 0x0a:      /* /OGIA */
1163
1151
                case 0x0b:      /* /OGID */
1164
 
                        ay8910_address_data_w(space->machine().device("ay8910.1"), offset, data);
 
1152
                        ay8910_address_data_w(machine().device("ay8910.1"), offset, data);
1165
1153
                        break;
1166
1154
 
1167
1155
                case 0x0c:      /* /BKXL */
1178
1166
}
1179
1167
 
1180
1168
 
1181
 
READ8_HANDLER( ataxx_master_input_r )
 
1169
READ8_MEMBER(leland_state::ataxx_master_input_r)
1182
1170
{
1183
1171
        int result = 0xff;
1184
1172
 
1185
1173
        switch (offset)
1186
1174
        {
1187
1175
                case 0x06:      /* /GIN0 */
1188
 
                        result = input_port_read(space->machine(), "IN0");
 
1176
                        result = ioport("IN0")->read();
1189
1177
                        break;
1190
1178
 
1191
1179
                case 0x07:      /* /SLVBLK */
1192
 
                        result = input_port_read(space->machine(), "IN1");
1193
 
                        if (cpu_get_reg(space->machine().device("slave"), Z80_HALT))
 
1180
                        result = ioport("IN1")->read();
 
1181
                        if (cpu_get_reg(machine().device("slave"), Z80_HALT))
1194
1182
                                result ^= 0x01;
1195
1183
                        break;
1196
1184
 
1202
1190
}
1203
1191
 
1204
1192
 
1205
 
WRITE8_HANDLER( ataxx_master_output_w )
 
1193
WRITE8_MEMBER(leland_state::ataxx_master_output_w)
1206
1194
{
1207
 
        leland_state *state = space->machine().driver_data<leland_state>();
1208
1195
        switch (offset)
1209
1196
        {
1210
1197
                case 0x00:      /* /BKXL */
1216
1203
 
1217
1204
                case 0x04:      /* /MBNK */
1218
1205
                        if (LOG_BANKSWITCHING_M)
1219
 
                                if ((state->m_master_bank ^ data) & 0xff)
1220
 
                                        logerror("%04X:master_bank = %02X\n", cpu_get_pc(&space->device()), data & 0xff);
1221
 
                        state->m_master_bank = data;
1222
 
                        ataxx_bankswitch(space->machine());
 
1206
                                if ((m_master_bank ^ data) & 0xff)
 
1207
                                        logerror("%04X:master_bank = %02X\n", cpu_get_pc(&space.device()), data & 0xff);
 
1208
                        m_master_bank = data;
 
1209
                        ataxx_bankswitch(machine());
1223
1210
                        break;
1224
1211
 
1225
1212
                case 0x05:      /* /SLV0 */
1226
 
                        cputag_set_input_line(space->machine(), "slave", 0, (data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
1227
 
                        cputag_set_input_line(space->machine(), "slave", INPUT_LINE_NMI, (data & 0x04) ? CLEAR_LINE : ASSERT_LINE);
1228
 
                        cputag_set_input_line(space->machine(), "slave", INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
 
1213
                        cputag_set_input_line(machine(), "slave", 0, (data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
 
1214
                        cputag_set_input_line(machine(), "slave", INPUT_LINE_NMI, (data & 0x04) ? CLEAR_LINE : ASSERT_LINE);
 
1215
                        cputag_set_input_line(machine(), "slave", INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
1229
1216
                        break;
1230
1217
 
1231
1218
                case 0x08:      /*  */
1232
 
                        state->m_master_int_timer->adjust(space->machine().primary_screen->time_until_pos(data + 1), data + 1);
 
1219
                        m_master_int_timer->adjust(machine().primary_screen->time_until_pos(data + 1), data + 1);
1233
1220
                        break;
1234
1221
 
1235
1222
                default:
1246
1233
 *
1247
1234
 *************************************/
1248
1235
 
1249
 
WRITE8_HANDLER( leland_gated_paletteram_w )
 
1236
WRITE8_MEMBER(leland_state::leland_gated_paletteram_w)
1250
1237
{
1251
 
        leland_state *state = space->machine().driver_data<leland_state>();
1252
 
        if (state->m_wcol_enable)
1253
 
                paletteram_BBGGGRRR_w(space, offset, data);
 
1238
        if (m_wcol_enable)
 
1239
                paletteram_BBGGGRRR_byte_w(space, offset, data);
1254
1240
}
1255
1241
 
1256
1242
 
1257
 
READ8_HANDLER( leland_gated_paletteram_r )
 
1243
READ8_MEMBER(leland_state::leland_gated_paletteram_r)
1258
1244
{
1259
 
        leland_state *state = space->machine().driver_data<leland_state>();
1260
 
        if (state->m_wcol_enable)
1261
 
                return space->machine().generic.paletteram.u8[offset];
 
1245
        if (m_wcol_enable)
 
1246
                return m_generic_paletteram_8[offset];
1262
1247
        return 0xff;
1263
1248
}
1264
1249
 
1265
1250
 
1266
 
WRITE8_HANDLER( ataxx_paletteram_and_misc_w )
 
1251
WRITE8_MEMBER(leland_state::ataxx_paletteram_and_misc_w)
1267
1252
{
1268
 
        leland_state *state = space->machine().driver_data<leland_state>();
1269
 
        if (state->m_wcol_enable)
1270
 
                paletteram_xxxxRRRRGGGGBBBB_le_w(space, offset, data);
 
1253
        if (m_wcol_enable)
 
1254
                paletteram_xxxxRRRRGGGGBBBB_byte_le_w(space, offset, data);
1271
1255
        else if (offset == 0x7f8 || offset == 0x7f9)
1272
1256
                leland_master_video_addr_w(space, offset - 0x7f8, data);
1273
1257
        else if (offset == 0x7fc)
1274
1258
        {
1275
 
                state->m_xrom1_addr = (state->m_xrom1_addr & 0xff00) | (data & 0x00ff);
1276
 
                if (LOG_XROM) logerror("%04X:XROM1 address low write = %02X (addr=%04X)\n", cpu_get_pc(&space->device()), data, state->m_xrom1_addr);
 
1259
                m_xrom1_addr = (m_xrom1_addr & 0xff00) | (data & 0x00ff);
 
1260
                if (LOG_XROM) logerror("%04X:XROM1 address low write = %02X (addr=%04X)\n", cpu_get_pc(&space.device()), data, m_xrom1_addr);
1277
1261
        }
1278
1262
        else if (offset == 0x7fd)
1279
1263
        {
1280
 
                state->m_xrom1_addr = (state->m_xrom1_addr & 0x00ff) | ((data << 8) & 0xff00);
1281
 
                if (LOG_XROM) logerror("%04X:XROM1 address high write = %02X (addr=%04X)\n", cpu_get_pc(&space->device()), data, state->m_xrom1_addr);
 
1264
                m_xrom1_addr = (m_xrom1_addr & 0x00ff) | ((data << 8) & 0xff00);
 
1265
                if (LOG_XROM) logerror("%04X:XROM1 address high write = %02X (addr=%04X)\n", cpu_get_pc(&space.device()), data, m_xrom1_addr);
1282
1266
        }
1283
1267
        else if (offset == 0x7fe)
1284
1268
        {
1285
 
                state->m_xrom2_addr = (state->m_xrom2_addr & 0xff00) | (data & 0x00ff);
1286
 
                if (LOG_XROM) logerror("%04X:XROM2 address low write = %02X (addr=%04X)\n", cpu_get_pc(&space->device()), data, state->m_xrom2_addr);
 
1269
                m_xrom2_addr = (m_xrom2_addr & 0xff00) | (data & 0x00ff);
 
1270
                if (LOG_XROM) logerror("%04X:XROM2 address low write = %02X (addr=%04X)\n", cpu_get_pc(&space.device()), data, m_xrom2_addr);
1287
1271
        }
1288
1272
        else if (offset == 0x7ff)
1289
1273
        {
1290
 
                state->m_xrom2_addr = (state->m_xrom2_addr & 0x00ff) | ((data << 8) & 0xff00);
1291
 
                if (LOG_XROM) logerror("%04X:XROM2 address high write = %02X (addr=%04X)\n", cpu_get_pc(&space->device()), data, state->m_xrom2_addr);
 
1274
                m_xrom2_addr = (m_xrom2_addr & 0x00ff) | ((data << 8) & 0xff00);
 
1275
                if (LOG_XROM) logerror("%04X:XROM2 address high write = %02X (addr=%04X)\n", cpu_get_pc(&space.device()), data, m_xrom2_addr);
1292
1276
        }
1293
1277
        else
1294
 
                state->m_extra_tram[offset] = data;
 
1278
                m_extra_tram[offset] = data;
1295
1279
}
1296
1280
 
1297
1281
 
1298
 
READ8_HANDLER( ataxx_paletteram_and_misc_r )
 
1282
READ8_MEMBER(leland_state::ataxx_paletteram_and_misc_r)
1299
1283
{
1300
 
        leland_state *state = space->machine().driver_data<leland_state>();
1301
 
        if (state->m_wcol_enable)
1302
 
                return space->machine().generic.paletteram.u8[offset];
 
1284
        if (m_wcol_enable)
 
1285
                return m_generic_paletteram_8[offset];
1303
1286
        else if (offset == 0x7fc || offset == 0x7fd)
1304
1287
        {
1305
 
                int result = state->m_xrom_base[0x00000 | state->m_xrom1_addr | ((offset & 1) << 16)];
1306
 
                if (LOG_XROM) logerror("%04X:XROM1 read(%d) = %02X (addr=%04X)\n", cpu_get_pc(&space->device()), offset - 0x7fc, result, state->m_xrom1_addr);
 
1288
                int result = m_xrom_base[0x00000 | m_xrom1_addr | ((offset & 1) << 16)];
 
1289
                if (LOG_XROM) logerror("%04X:XROM1 read(%d) = %02X (addr=%04X)\n", cpu_get_pc(&space.device()), offset - 0x7fc, result, m_xrom1_addr);
1307
1290
                return result;
1308
1291
        }
1309
1292
        else if (offset == 0x7fe || offset == 0x7ff)
1310
1293
        {
1311
 
                int result = state->m_xrom_base[0x20000 | state->m_xrom2_addr | ((offset & 1) << 16)];
1312
 
                if (LOG_XROM) logerror("%04X:XROM2 read(%d) = %02X (addr=%04X)\n", cpu_get_pc(&space->device()), offset - 0x7fc, result, state->m_xrom2_addr);
 
1294
                int result = m_xrom_base[0x20000 | m_xrom2_addr | ((offset & 1) << 16)];
 
1295
                if (LOG_XROM) logerror("%04X:XROM2 read(%d) = %02X (addr=%04X)\n", cpu_get_pc(&space.device()), offset - 0x7fc, result, m_xrom2_addr);
1313
1296
                return result;
1314
1297
        }
1315
1298
        else
1316
 
                return state->m_extra_tram[offset];
 
1299
                return m_extra_tram[offset];
1317
1300
}
1318
1301
 
1319
1302
 
1357
1340
 *
1358
1341
 *************************************/
1359
1342
 
1360
 
WRITE8_HANDLER( leland_slave_small_banksw_w )
 
1343
WRITE8_MEMBER(leland_state::leland_slave_small_banksw_w)
1361
1344
{
1362
 
        leland_state *state = space->machine().driver_data<leland_state>();
1363
1345
        int bankaddress = 0x10000 + 0xc000 * (data & 1);
1364
1346
 
1365
 
        if (bankaddress >= state->m_slave_length)
 
1347
        if (bankaddress >= m_slave_length)
1366
1348
        {
1367
 
                logerror("%04X:Slave bank %02X out of range!", cpu_get_pc(&space->device()), data & 1);
 
1349
                logerror("%04X:Slave bank %02X out of range!", cpu_get_pc(&space.device()), data & 1);
1368
1350
                bankaddress = 0x10000;
1369
1351
        }
1370
 
        memory_set_bankptr(space->machine(), "bank3", &state->m_slave_base[bankaddress]);
 
1352
        membank("bank3")->set_base(&m_slave_base[bankaddress]);
1371
1353
 
1372
 
        if (LOG_BANKSWITCHING_S) logerror("%04X:Slave bank = %02X (%05X)\n", cpu_get_pc(&space->device()), data & 1, bankaddress);
 
1354
        if (LOG_BANKSWITCHING_S) logerror("%04X:Slave bank = %02X (%05X)\n", cpu_get_pc(&space.device()), data & 1, bankaddress);
1373
1355
}
1374
1356
 
1375
1357
 
1376
 
WRITE8_HANDLER( leland_slave_large_banksw_w )
 
1358
WRITE8_MEMBER(leland_state::leland_slave_large_banksw_w)
1377
1359
{
1378
 
        leland_state *state = space->machine().driver_data<leland_state>();
1379
1360
        int bankaddress = 0x10000 + 0x8000 * (data & 15);
1380
1361
 
1381
 
        if (bankaddress >= state->m_slave_length)
 
1362
        if (bankaddress >= m_slave_length)
1382
1363
        {
1383
 
                logerror("%04X:Slave bank %02X out of range!", cpu_get_pc(&space->device()), data & 15);
 
1364
                logerror("%04X:Slave bank %02X out of range!", cpu_get_pc(&space.device()), data & 15);
1384
1365
                bankaddress = 0x10000;
1385
1366
        }
1386
 
        memory_set_bankptr(space->machine(), "bank3", &state->m_slave_base[bankaddress]);
 
1367
        membank("bank3")->set_base(&m_slave_base[bankaddress]);
1387
1368
 
1388
 
        if (LOG_BANKSWITCHING_S) logerror("%04X:Slave bank = %02X (%05X)\n", cpu_get_pc(&space->device()), data & 15, bankaddress);
 
1369
        if (LOG_BANKSWITCHING_S) logerror("%04X:Slave bank = %02X (%05X)\n", cpu_get_pc(&space.device()), data & 15, bankaddress);
1389
1370
}
1390
1371
 
1391
1372
 
1392
 
WRITE8_HANDLER( ataxx_slave_banksw_w )
 
1373
WRITE8_MEMBER(leland_state::ataxx_slave_banksw_w)
1393
1374
{
1394
 
        leland_state *state = space->machine().driver_data<leland_state>();
1395
1375
        int bankaddress, bank = data & 15;
1396
1376
 
1397
1377
        if (bank == 0)
1399
1379
        else
1400
1380
        {
1401
1381
                bankaddress = 0x10000 * bank + 0x8000 * ((data >> 4) & 1);
1402
 
                if (state->m_slave_length > 0x100000)
 
1382
                if (m_slave_length > 0x100000)
1403
1383
                        bankaddress += 0x100000 * ((data >> 5) & 1);
1404
1384
        }
1405
1385
 
1406
 
        if (bankaddress >= state->m_slave_length)
 
1386
        if (bankaddress >= m_slave_length)
1407
1387
        {
1408
 
                logerror("%04X:Slave bank %02X out of range!", cpu_get_pc(&space->device()), data & 0x3f);
 
1388
                logerror("%04X:Slave bank %02X out of range!", cpu_get_pc(&space.device()), data & 0x3f);
1409
1389
                bankaddress = 0x2000;
1410
1390
        }
1411
 
        memory_set_bankptr(space->machine(), "bank3", &state->m_slave_base[bankaddress]);
 
1391
        membank("bank3")->set_base(&m_slave_base[bankaddress]);
1412
1392
 
1413
 
        if (LOG_BANKSWITCHING_S) logerror("%04X:Slave bank = %02X (%05X)\n", cpu_get_pc(&space->device()), data, bankaddress);
 
1393
        if (LOG_BANKSWITCHING_S) logerror("%04X:Slave bank = %02X (%05X)\n", cpu_get_pc(&space.device()), data, bankaddress);
1414
1394
}
1415
1395
 
1416
1396
 
1421
1401
 *
1422
1402
 *************************************/
1423
1403
 
1424
 
READ8_HANDLER( leland_raster_r )
 
1404
READ8_MEMBER(leland_state::leland_raster_r)
1425
1405
{
1426
 
        return space->machine().primary_screen->vpos();
 
1406
        return machine().primary_screen->vpos();
1427
1407
}
1428
1408
 
1429
1409
 
1438
1418
void leland_rotate_memory(running_machine &machine, const char *cpuname)
1439
1419
{
1440
1420
        int startaddr = 0x10000;
1441
 
        int banks = (machine.region(cpuname)->bytes() - startaddr) / 0x8000;
1442
 
        UINT8 *ram = machine.region(cpuname)->base();
 
1421
        int banks = (machine.root_device().memregion(cpuname)->bytes() - startaddr) / 0x8000;
 
1422
        UINT8 *ram = machine.root_device().memregion(cpuname)->base();
1443
1423
        UINT8 temp[0x2000];
1444
1424
        int i;
1445
1425