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Viewing changes to src/mame/drivers/funybubl.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/funybubl.c
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#include "includes/funybubl.h"
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static WRITE8_HANDLER ( funybubl_vidram_bank_w )
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{
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        memory_set_bank(space->machine(), "bank1", data & 1);
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}
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static WRITE8_HANDLER ( funybubl_cpurombank_w )
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{
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        memory_set_bank(space->machine(), "bank2", data & 0x3f);        // should we add a check that (data&0x3f) < #banks?
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}
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static WRITE8_HANDLER( funybubl_soundcommand_w )
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{
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        funybubl_state *state = space->machine().driver_data<funybubl_state>();
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        soundlatch_w(space, 0, data);
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        device_set_input_line(state->m_audiocpu, 0, HOLD_LINE);
 
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WRITE8_MEMBER(funybubl_state::funybubl_vidram_bank_w)
 
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{
 
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        membank("bank1")->set_entry(data & 1);
 
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}
 
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WRITE8_MEMBER(funybubl_state::funybubl_cpurombank_w)
 
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{
 
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        membank("bank2")->set_entry(data & 0x3f);       // should we add a check that (data&0x3f) < #banks?
 
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}
 
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WRITE8_MEMBER(funybubl_state::funybubl_soundcommand_w)
 
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{
 
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        soundlatch_byte_w(space, 0, data);
 
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        device_set_input_line(m_audiocpu, 0, HOLD_LINE);
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}
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static WRITE8_DEVICE_HANDLER( funybubl_oki_bank_sw )
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}
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static ADDRESS_MAP_START( funybubl_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( funybubl_map, AS_PROGRAM, 8, funybubl_state )
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank2") // banked port 1?
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        AM_RANGE(0xc400, 0xcfff) AM_RAM_WRITE(funybubl_paldatawrite) AM_BASE_MEMBER(funybubl_state, m_paletteram) // palette
 
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        AM_RANGE(0xc400, 0xcfff) AM_RAM_WRITE(funybubl_paldatawrite) AM_SHARE("paletteram") // palette
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        AM_RANGE(0xd000, 0xdfff) AM_RAMBANK("bank1") // banked port 0?
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        AM_RANGE(0xe000, 0xffff) AM_RAM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( io_map, AS_IO, 8 )
 
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static ADDRESS_MAP_START( io_map, AS_IO, 8, funybubl_state )
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        ADDRESS_MAP_GLOBAL_MASK(0xff)
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        AM_RANGE(0x00, 0x00) AM_READ_PORT("SYSTEM") AM_WRITE(funybubl_vidram_bank_w)    // vidram bank
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        AM_RANGE(0x01, 0x01) AM_READ_PORT("P1") AM_WRITE(funybubl_cpurombank_w)         // rom bank?
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/* Sound CPU */
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static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, funybubl_state )
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0x8000, 0x87ff) AM_RAM
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        AM_RANGE(0x9000, 0x9000) AM_DEVWRITE("oki", funybubl_oki_bank_sw)
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        AM_RANGE(0x9800, 0x9800) AM_DEVREADWRITE_MODERN("oki", okim6295_device, read, write)
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        AM_RANGE(0xa000, 0xa000) AM_READ(soundlatch_r)
 
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        AM_RANGE(0x9000, 0x9000) AM_DEVWRITE_LEGACY("oki", funybubl_oki_bank_sw)
 
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        AM_RANGE(0x9800, 0x9800) AM_DEVREADWRITE("oki", okim6295_device, read, write)
 
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        AM_RANGE(0xa000, 0xa000) AM_READ(soundlatch_byte_r)
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ADDRESS_MAP_END
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static MACHINE_START( funybubl )
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{
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        funybubl_state *state = machine.driver_data<funybubl_state>();
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        UINT8 *ROM = machine.region("maincpu")->base();
 
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        UINT8 *ROM = state->memregion("maincpu")->base();
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        state->m_audiocpu = machine.device("audiocpu");
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        state->save_item(NAME(state->m_banked_vram));
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        memory_configure_bank(machine, "bank1", 0, 2, &state->m_banked_vram[0x0000], 0x1000);
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        memory_configure_bank(machine, "bank2", 0, 0x10, &ROM[0x10000], 0x4000);
 
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        state->membank("bank1")->configure_entries(0, 2, &state->m_banked_vram[0x0000], 0x1000);
 
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        state->membank("bank2")->configure_entries(0, 0x10, &ROM[0x10000], 0x4000);
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        memory_set_bank(machine, "bank1", 0);
 
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        state->membank("bank1")->set_entry(0);
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}
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