← Back to branch summary

~ubuntu-branches/debian/sid/mame/sid

« back to all changes in this revision

Viewing changes to src/mame/drivers/taito_l.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

Show diffs side-by-side

added added

removed removed

Lines of Context:
src/mame/drivers/taito_l.c
169
169
                state->m_cur_rambank[i] = 0x80;
170
170
                state->m_current_notifier[i] = palette_notifier;
171
171
                state->m_current_base[i] = state->m_palette_ram;
172
 
                memory_set_bankptr(machine, bankname[i], state->m_current_base[i]);
 
172
                state->membank(bankname[i])->set_base(state->m_current_base[i]);
173
173
        }
174
174
 
175
175
        state->m_cur_rombank = state->m_cur_rombank2 = 0;
176
 
        memory_set_bankptr(machine, "bank1", machine.region("maincpu")->base() + 0x10000);
 
176
        state->membank("bank1")->set_base(machine.root_device().memregion("maincpu")->base() + 0x10000);
177
177
 
178
178
        gfx_element_set_source(machine.gfx[2], state->m_rambanks);
179
179
 
337
337
        }
338
338
}
339
339
 
340
 
static WRITE8_HANDLER( irq_adr_w )
 
340
WRITE8_MEMBER(taitol_state::irq_adr_w)
341
341
{
342
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
343
342
        //logerror("irq_adr_table[%d] = %02x\n", offset, data);
344
 
        state->m_irq_adr_table[offset] = data;
345
 
}
346
 
 
347
 
static READ8_HANDLER( irq_adr_r )
348
 
{
349
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
350
 
        return state->m_irq_adr_table[offset];
351
 
}
352
 
 
353
 
static WRITE8_HANDLER( irq_enable_w )
354
 
{
355
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
 
343
        m_irq_adr_table[offset] = data;
 
344
}
 
345
 
 
346
READ8_MEMBER(taitol_state::irq_adr_r)
 
347
{
 
348
        return m_irq_adr_table[offset];
 
349
}
 
350
 
 
351
WRITE8_MEMBER(taitol_state::irq_enable_w)
 
352
{
356
353
        //logerror("irq_enable = %02x\n",data);
357
 
        state->m_irq_enable = data;
 
354
        m_irq_enable = data;
358
355
 
359
356
        // fix Plotting test mode
360
 
        if ((state->m_irq_enable & (1 << state->m_last_irq_level)) == 0)
361
 
                device_set_input_line(state->m_maincpu, 0, CLEAR_LINE);
362
 
}
363
 
 
364
 
static READ8_HANDLER( irq_enable_r )
365
 
{
366
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
367
 
        return state->m_irq_enable;
368
 
}
369
 
 
370
 
 
371
 
static WRITE8_HANDLER( rombankswitch_w )
372
 
{
373
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
374
 
 
375
 
        if (state->m_cur_rombank != data)
 
357
        if ((m_irq_enable & (1 << m_last_irq_level)) == 0)
 
358
                device_set_input_line(m_maincpu, 0, CLEAR_LINE);
 
359
}
 
360
 
 
361
READ8_MEMBER(taitol_state::irq_enable_r)
 
362
{
 
363
        return m_irq_enable;
 
364
}
 
365
 
 
366
 
 
367
WRITE8_MEMBER(taitol_state::rombankswitch_w)
 
368
{
 
369
 
 
370
        if (m_cur_rombank != data)
376
371
        {
377
 
                if (data > state->m_high)
 
372
                if (data > m_high)
378
373
                {
379
 
                        state->m_high = data;
380
 
                        logerror("New rom size : %x\n", (state->m_high + 1) * 0x2000);
 
374
                        m_high = data;
 
375
                        logerror("New rom size : %x\n", (m_high + 1) * 0x2000);
381
376
                }
382
377
 
383
 
                //logerror("robs %d, %02x (%04x)\n", offset, data, cpu_get_pc(&space->device()));
384
 
                state->m_cur_rombank = data;
385
 
                memory_set_bankptr(space->machine(), "bank1", space->machine().region("maincpu")->base() + 0x10000 + 0x2000 * state->m_cur_rombank);
 
378
                //logerror("robs %d, %02x (%04x)\n", offset, data, cpu_get_pc(&space.device()));
 
379
                m_cur_rombank = data;
 
380
                membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() + 0x10000 + 0x2000 * m_cur_rombank);
386
381
        }
387
382
}
388
383
 
389
 
static WRITE8_HANDLER( rombank2switch_w )
 
384
WRITE8_MEMBER(taitol_state::rombank2switch_w)
390
385
{
391
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
392
386
 
393
387
        data &= 0xf;
394
388
 
395
 
        if (state->m_cur_rombank2 != data)
 
389
        if (m_cur_rombank2 != data)
396
390
        {
397
 
                if (data > state->m_high2)
 
391
                if (data > m_high2)
398
392
                {
399
 
                        state->m_high2 = data;
400
 
                        logerror("New rom2 size : %x\n", (state->m_high2 + 1) * 0x4000);
 
393
                        m_high2 = data;
 
394
                        logerror("New rom2 size : %x\n", (m_high2 + 1) * 0x4000);
401
395
                }
402
396
 
403
 
                //logerror("robs2 %02x (%04x)\n", data, cpu_get_pc(&space->device()));
 
397
                //logerror("robs2 %02x (%04x)\n", data, cpu_get_pc(&space.device()));
404
398
 
405
 
                state->m_cur_rombank2 = data;
406
 
                memory_set_bankptr(space->machine(), "bank6", space->machine().region("slave")->base() + 0x10000 + 0x4000 * state->m_cur_rombank2);
 
399
                m_cur_rombank2 = data;
 
400
                membank("bank6")->set_base(machine().root_device().memregion("slave")->base() + 0x10000 + 0x4000 * m_cur_rombank2);
407
401
        }
408
402
}
409
403
 
410
 
static READ8_HANDLER( rombankswitch_r )
411
 
{
412
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
413
 
        return state->m_cur_rombank;
414
 
}
415
 
 
416
 
static READ8_HANDLER( rombank2switch_r )
417
 
{
418
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
419
 
        return state->m_cur_rombank2;
420
 
}
421
 
 
422
 
static WRITE8_HANDLER( rambankswitch_w )
423
 
{
424
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
425
 
 
426
 
        if (state->m_cur_rambank[offset] != data)
 
404
READ8_MEMBER(taitol_state::rombankswitch_r)
 
405
{
 
406
        return m_cur_rombank;
 
407
}
 
408
 
 
409
READ8_MEMBER(taitol_state::rombank2switch_r)
 
410
{
 
411
        return m_cur_rombank2;
 
412
}
 
413
 
 
414
WRITE8_MEMBER(taitol_state::rambankswitch_w)
 
415
{
 
416
 
 
417
        if (m_cur_rambank[offset] != data)
427
418
        {
428
 
                state->m_cur_rambank[offset] = data;
429
 
//logerror("rabs %d, %02x (%04x)\n", offset, data, cpu_get_pc(&space->device()));
 
419
                m_cur_rambank[offset] = data;
 
420
//logerror("rabs %d, %02x (%04x)\n", offset, data, cpu_get_pc(&space.device()));
430
421
                if (data >= 0x14 && data <= 0x1f)
431
422
                {
432
423
                        data -= 0x14;
433
 
                        state->m_current_notifier[offset] = rambank_modify_notifiers[data].notifier;
434
 
                        state->m_current_base[offset] = state->m_rambanks + rambank_modify_notifiers[data].offset;
 
424
                        m_current_notifier[offset] = rambank_modify_notifiers[data].notifier;
 
425
                        m_current_base[offset] = m_rambanks + rambank_modify_notifiers[data].offset;
435
426
                }
436
427
                else if (data == 0x80)
437
428
                {
438
 
                        state->m_current_notifier[offset] = palette_notifier;
439
 
                        state->m_current_base[offset] = state->m_palette_ram;
 
429
                        m_current_notifier[offset] = palette_notifier;
 
430
                        m_current_base[offset] = m_palette_ram;
440
431
                }
441
432
                else
442
433
                {
443
 
                        logerror("unknown rambankswitch %d, %02x (%04x)\n", offset, data, cpu_get_pc(&space->device()));
444
 
                        state->m_current_notifier[offset] = 0;
445
 
                        state->m_current_base[offset] = state->m_empty_ram;
 
434
                        logerror("unknown rambankswitch %d, %02x (%04x)\n", offset, data, cpu_get_pc(&space.device()));
 
435
                        m_current_notifier[offset] = 0;
 
436
                        m_current_base[offset] = m_empty_ram;
446
437
                }
447
 
                memory_set_bankptr(space->machine(), bankname[offset], state->m_current_base[offset]);
 
438
                membank(bankname[offset])->set_base(m_current_base[offset]);
448
439
        }
449
440
}
450
441
 
451
 
static READ8_HANDLER( rambankswitch_r )
 
442
READ8_MEMBER(taitol_state::rambankswitch_r)
452
443
{
453
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
454
 
        return state->m_cur_rambank[offset];
 
444
        return m_cur_rambank[offset];
455
445
}
456
446
 
457
447
static void bank_w(address_space *space, offs_t offset, UINT8 data, int banknum )
466
456
        }
467
457
}
468
458
 
469
 
static WRITE8_HANDLER( bank0_w )
470
 
{
471
 
        bank_w(space, offset, data, 0);
472
 
}
473
 
 
474
 
static WRITE8_HANDLER( bank1_w )
475
 
{
476
 
        bank_w(space, offset, data, 1);
477
 
}
478
 
 
479
 
static WRITE8_HANDLER( bank2_w )
480
 
{
481
 
        bank_w(space, offset, data, 2);
482
 
}
483
 
 
484
 
static WRITE8_HANDLER( bank3_w )
485
 
{
486
 
        bank_w(space, offset, data, 3);
487
 
}
488
 
 
489
 
static WRITE8_HANDLER( control2_w )
490
 
{
491
 
        coin_lockout_w(space->machine(), 0, ~data & 0x01);
492
 
        coin_lockout_w(space->machine(), 1, ~data & 0x02);
493
 
        coin_counter_w(space->machine(), 0, data & 0x04);
494
 
        coin_counter_w(space->machine(), 1, data & 0x08);
 
459
WRITE8_MEMBER(taitol_state::bank0_w)
 
460
{
 
461
        bank_w(&space, offset, data, 0);
 
462
}
 
463
 
 
464
WRITE8_MEMBER(taitol_state::bank1_w)
 
465
{
 
466
        bank_w(&space, offset, data, 1);
 
467
}
 
468
 
 
469
WRITE8_MEMBER(taitol_state::bank2_w)
 
470
{
 
471
        bank_w(&space, offset, data, 2);
 
472
}
 
473
 
 
474
WRITE8_MEMBER(taitol_state::bank3_w)
 
475
{
 
476
        bank_w(&space, offset, data, 3);
 
477
}
 
478
 
 
479
WRITE8_MEMBER(taitol_state::control2_w)
 
480
{
 
481
        coin_lockout_w(machine(), 0, ~data & 0x01);
 
482
        coin_lockout_w(machine(), 1, ~data & 0x02);
 
483
        coin_counter_w(machine(), 0, data & 0x04);
 
484
        coin_counter_w(machine(), 1, data & 0x08);
495
485
}
496
486
 
497
487
static READ8_DEVICE_HANDLER( portA_r )
498
488
{
499
489
        taitol_state *state = device->machine().driver_data<taitol_state>();
500
 
        return input_port_read(device->machine(), (state->m_extport == 0) ? state->m_porte0_tag : state->m_porte1_tag);
 
490
        return state->ioport((state->m_extport == 0) ? state->m_porte0_tag : state->m_porte1_tag)->read();
501
491
}
502
492
 
503
493
static READ8_DEVICE_HANDLER( portB_r )
504
494
{
505
495
        taitol_state *state = device->machine().driver_data<taitol_state>();
506
 
        return input_port_read(device->machine(), (state->m_extport == 0) ? state->m_portf0_tag : state->m_portf1_tag);
 
496
        return state->ioport((state->m_extport == 0) ? state->m_portf0_tag : state->m_portf1_tag)->read();
507
497
}
508
498
 
509
499
static READ8_DEVICE_HANDLER( extport_select_and_ym2203_r )
513
503
        return ym2203_r(device, offset & 1);
514
504
}
515
505
 
516
 
static WRITE8_HANDLER( mcu_data_w )
 
506
WRITE8_MEMBER(taitol_state::mcu_data_w)
517
507
{
518
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
519
 
        state->m_last_data = data;
520
 
        state->m_last_data_adr = cpu_get_pc(&space->device());
521
 
//  logerror("mcu write %02x (%04x)\n", data, cpu_get_pc(&space->device()));
 
508
        m_last_data = data;
 
509
        m_last_data_adr = cpu_get_pc(&space.device());
 
510
//  logerror("mcu write %02x (%04x)\n", data, cpu_get_pc(&space.device()));
522
511
        switch (data)
523
512
        {
524
513
        case 0x43:
525
 
                state->m_mcu_pos = 0;
526
 
                state->m_mcu_reply_len = ARRAY_LENGTH(puzznic_mcu_reply);
 
514
                m_mcu_pos = 0;
 
515
                m_mcu_reply_len = ARRAY_LENGTH(puzznic_mcu_reply);
527
516
                break;
528
517
        }
529
518
}
530
519
 
531
 
static WRITE8_HANDLER( mcu_control_w )
 
520
WRITE8_MEMBER(taitol_state::mcu_control_w)
532
521
{
533
 
//  logerror("mcu control %02x (%04x)\n", data, cpu_get_pc(&space->device()));
 
522
//  logerror("mcu control %02x (%04x)\n", data, cpu_get_pc(&space.device()));
534
523
}
535
524
 
536
 
static READ8_HANDLER( mcu_data_r )
 
525
READ8_MEMBER(taitol_state::mcu_data_r)
537
526
{
538
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
539
527
 
540
 
//  logerror("mcu read (%04x) [%02x, %04x]\n", cpu_get_pc(&space->device()), last_data, last_data_adr);
541
 
        if (state->m_mcu_pos == state->m_mcu_reply_len)
 
528
//  logerror("mcu read (%04x) [%02x, %04x]\n", cpu_get_pc(&space.device()), last_data, last_data_adr);
 
529
        if (m_mcu_pos == m_mcu_reply_len)
542
530
                return 0;
543
531
 
544
 
        return state->m_mcu_reply[state->m_mcu_pos++];
 
532
        return m_mcu_reply[m_mcu_pos++];
545
533
}
546
534
 
547
 
static READ8_HANDLER( mcu_control_r )
 
535
READ8_MEMBER(taitol_state::mcu_control_r)
548
536
{
549
 
//  logerror("mcu control read (%04x)\n", cpu_get_pc(&space->device()));
 
537
//  logerror("mcu control read (%04x)\n", cpu_get_pc(&space.device()));
550
538
        return 0x1;
551
539
}
552
540
 
553
541
#if 0
554
 
static WRITE8_HANDLER( sound_w )
 
542
WRITE8_MEMBER(taitol_state::sound_w)
555
543
{
556
 
        logerror("Sound_w %02x (%04x)\n", data, cpu_get_pc(&space->device()));
 
544
        logerror("Sound_w %02x (%04x)\n", data, cpu_get_pc(&space.device()));
557
545
}
558
546
#endif
559
547
 
560
 
static READ8_HANDLER( mux_r )
 
548
READ8_MEMBER(taitol_state::mux_r)
561
549
{
562
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
563
550
 
564
 
        switch (state->m_mux_ctrl)
 
551
        switch (m_mux_ctrl)
565
552
        {
566
553
        case 0:
567
 
                return input_port_read(space->machine(), "DSWA");
 
554
                return ioport("DSWA")->read();
568
555
        case 1:
569
 
                return input_port_read(space->machine(), "DSWB");
 
556
                return ioport("DSWB")->read();
570
557
        case 2:
571
 
                return input_port_read(space->machine(), "IN0");
 
558
                return ioport("IN0")->read();
572
559
        case 3:
573
 
                return input_port_read(space->machine(), "IN1");
 
560
                return ioport("IN1")->read();
574
561
        case 7:
575
 
                return input_port_read(space->machine(), "IN2");
 
562
                return ioport("IN2")->read();
576
563
        default:
577
 
                logerror("Mux read from unknown port %d (%04x)\n", state->m_mux_ctrl, cpu_get_pc(&space->device()));
 
564
                logerror("Mux read from unknown port %d (%04x)\n", m_mux_ctrl, cpu_get_pc(&space.device()));
578
565
                return 0xff;
579
566
        }
580
567
}
581
568
 
582
 
static WRITE8_HANDLER( mux_w )
 
569
WRITE8_MEMBER(taitol_state::mux_w)
583
570
{
584
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
585
571
 
586
 
        switch (state->m_mux_ctrl)
 
572
        switch (m_mux_ctrl)
587
573
        {
588
574
        case 4:
589
575
                control2_w(space, 0, data);
590
576
                break;
591
577
        default:
592
 
                logerror("Mux write to unknown port %d, %02x (%04x)\n", state->m_mux_ctrl, data, cpu_get_pc(&space->device()));
 
578
                logerror("Mux write to unknown port %d, %02x (%04x)\n", m_mux_ctrl, data, cpu_get_pc(&space.device()));
593
579
        }
594
580
}
595
581
 
596
 
static WRITE8_HANDLER( mux_ctrl_w )
 
582
WRITE8_MEMBER(taitol_state::mux_ctrl_w)
597
583
{
598
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
599
 
        state->m_mux_ctrl = data;
 
584
        m_mux_ctrl = data;
600
585
}
601
586
 
602
587
 
611
596
        }
612
597
        else
613
598
        {
614
 
                state->m_adpcm_data = device->machine().region("adpcm")->base()[state->m_adpcm_pos];
 
599
                state->m_adpcm_data = device->machine().root_device().memregion("adpcm")->base()[state->m_adpcm_pos];
615
600
                state->m_adpcm_pos = (state->m_adpcm_pos + 1) & 0x1ffff;
616
601
                msm5205_data_w(device, state->m_adpcm_data >> 4);
617
602
        }
618
603
}
619
604
 
620
 
static WRITE8_HANDLER( champwr_msm5205_lo_w )
 
605
WRITE8_MEMBER(taitol_state::champwr_msm5205_lo_w)
621
606
{
622
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
623
 
        state->m_adpcm_pos = (state->m_adpcm_pos & 0xff00ff) | (data << 8);
 
607
        m_adpcm_pos = (m_adpcm_pos & 0xff00ff) | (data << 8);
624
608
}
625
609
 
626
 
static WRITE8_HANDLER( champwr_msm5205_hi_w )
 
610
WRITE8_MEMBER(taitol_state::champwr_msm5205_hi_w)
627
611
{
628
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
629
 
        state->m_adpcm_pos = ((state->m_adpcm_pos & 0x00ffff) | (data << 16)) & 0x1ffff;
 
612
        m_adpcm_pos = ((m_adpcm_pos & 0x00ffff) | (data << 16)) & 0x1ffff;
630
613
}
631
614
 
632
615
static WRITE8_DEVICE_HANDLER( champwr_msm5205_start_w )
649
632
        sound->set_output_gain(0, data / 255.0);
650
633
}
651
634
 
652
 
static READ8_HANDLER( horshoes_tracky_reset_r )
653
 
{
654
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
655
 
 
656
 
        /* reset the trackball counter */
657
 
        state->m_tracky = input_port_read(space->machine(), "AN0");
658
 
        return 0;
659
 
}
660
 
 
661
 
static READ8_HANDLER( horshoes_trackx_reset_r )
662
 
{
663
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
664
 
 
665
 
        /* reset the trackball counter */
666
 
        state->m_trackx = input_port_read(space->machine(), "AN1");
667
 
        return 0;
668
 
}
669
 
 
670
 
static READ8_HANDLER( horshoes_tracky_lo_r )
671
 
{
672
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
673
 
        return (input_port_read(space->machine(), "AN0") - state->m_tracky) & 0xff;
674
 
}
675
 
 
676
 
static READ8_HANDLER( horshoes_tracky_hi_r )
677
 
{
678
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
679
 
        return (input_port_read(space->machine(), "AN0") - state->m_tracky) >> 8;
680
 
}
681
 
 
682
 
static READ8_HANDLER( horshoes_trackx_lo_r )
683
 
{
684
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
685
 
        return (input_port_read(space->machine(), "AN1") - state->m_trackx) & 0xff;
686
 
}
687
 
 
688
 
static READ8_HANDLER( horshoes_trackx_hi_r )
689
 
{
690
 
        taitol_state *state = space->machine().driver_data<taitol_state>();
691
 
        return (input_port_read(space->machine(), "AN1") - state->m_trackx) >> 8;
 
635
READ8_MEMBER(taitol_state::horshoes_tracky_reset_r)
 
636
{
 
637
 
 
638
        /* reset the trackball counter */
 
639
        m_tracky = ioport("AN0")->read();
 
640
        return 0;
 
641
}
 
642
 
 
643
READ8_MEMBER(taitol_state::horshoes_trackx_reset_r)
 
644
{
 
645
 
 
646
        /* reset the trackball counter */
 
647
        m_trackx = ioport("AN1")->read();
 
648
        return 0;
 
649
}
 
650
 
 
651
READ8_MEMBER(taitol_state::horshoes_tracky_lo_r)
 
652
{
 
653
        return (ioport("AN0")->read() - m_tracky) & 0xff;
 
654
}
 
655
 
 
656
READ8_MEMBER(taitol_state::horshoes_tracky_hi_r)
 
657
{
 
658
        return (ioport("AN0")->read() - m_tracky) >> 8;
 
659
}
 
660
 
 
661
READ8_MEMBER(taitol_state::horshoes_trackx_lo_r)
 
662
{
 
663
        return (ioport("AN1")->read() - m_trackx) & 0xff;
 
664
}
 
665
 
 
666
READ8_MEMBER(taitol_state::horshoes_trackx_hi_r)
 
667
{
 
668
        return (ioport("AN1")->read() - m_trackx) >> 8;
692
669
}
693
670
 
694
671
 
707
684
        AM_RANGE(0xff08, 0xff08) AM_READWRITE(rombankswitch_r, rombankswitch_w)
708
685
 
709
686
#define COMMON_SINGLE_MAP \
710
 
        AM_RANGE(0xa000, 0xa003) AM_DEVREADWRITE("ymsnd", extport_select_and_ym2203_r, ym2203_w)        \
 
687
        AM_RANGE(0xa000, 0xa003) AM_DEVREADWRITE_LEGACY("ymsnd", extport_select_and_ym2203_r, ym2203_w) \
711
688
        AM_RANGE(0x8000, 0x9fff) AM_RAM
712
689
 
713
690
 
714
691
 
715
 
static ADDRESS_MAP_START( fhawk_map, AS_PROGRAM, 8 )
 
692
static ADDRESS_MAP_START( fhawk_map, AS_PROGRAM, 8, taitol_state )
716
693
        COMMON_BANKS_MAP
717
694
        AM_RANGE(0x8000, 0x9fff) AM_RAM AM_SHARE("share1")
718
695
        AM_RANGE(0xa000, 0xbfff) AM_RAM
719
696
ADDRESS_MAP_END
720
697
 
721
 
static ADDRESS_MAP_START( fhawk_2_map, AS_PROGRAM, 8 )
 
698
static ADDRESS_MAP_START( fhawk_2_map, AS_PROGRAM, 8, taitol_state )
722
699
        AM_RANGE(0x0000, 0x7fff) AM_ROM
723
700
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank6")
724
701
        AM_RANGE(0xc000, 0xc000) AM_WRITE(rombank2switch_w)
725
 
        AM_RANGE(0xc800, 0xc800) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_port_w)
726
 
        AM_RANGE(0xc801, 0xc801) AM_DEVREADWRITE("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
 
702
        AM_RANGE(0xc800, 0xc800) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_port_w)
 
703
        AM_RANGE(0xc801, 0xc801) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
727
704
        AM_RANGE(0xd000, 0xd000) AM_READ_PORT("DSWA") AM_WRITENOP       // Direct copy of input port 0
728
705
        AM_RANGE(0xd001, 0xd001) AM_READ_PORT("DSWB")
729
706
        AM_RANGE(0xd002, 0xd002) AM_READ_PORT("IN0")
734
711
        AM_RANGE(0xe000, 0xffff) AM_RAM AM_SHARE("share1")
735
712
ADDRESS_MAP_END
736
713
 
737
 
static ADDRESS_MAP_START( fhawk_3_map, AS_PROGRAM, 8 )
 
714
static ADDRESS_MAP_START( fhawk_3_map, AS_PROGRAM, 8, taitol_state )
738
715
        AM_RANGE(0x0000, 0x3fff) AM_ROM
739
716
        AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank7")
740
717
        AM_RANGE(0x8000, 0x9fff) AM_RAM
741
 
        AM_RANGE(0xe000, 0xe000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_slave_port_w)
742
 
        AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
743
 
        AM_RANGE(0xf000, 0xf001) AM_DEVREADWRITE("ymsnd", ym2203_r, ym2203_w)
 
718
        AM_RANGE(0xe000, 0xe000) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_slave_port_w)
 
719
        AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
 
720
        AM_RANGE(0xf000, 0xf001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
744
721
ADDRESS_MAP_END
745
722
 
746
723
 
747
 
static ADDRESS_MAP_START( raimais_map, AS_PROGRAM, 8 )
 
724
static ADDRESS_MAP_START( raimais_map, AS_PROGRAM, 8, taitol_state )
748
725
        COMMON_BANKS_MAP
749
726
        AM_RANGE(0x8000, 0x87ff) AM_RAM AM_SHARE("share1")
750
727
        AM_RANGE(0x8800, 0x8800) AM_READWRITE(mux_r, mux_w)
751
728
        AM_RANGE(0x8801, 0x8801) AM_WRITE(mux_ctrl_w) AM_READNOP        // Watchdog or interrupt ack (value ignored)
752
 
        AM_RANGE(0x8c00, 0x8c00) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_port_w)
753
 
        AM_RANGE(0x8c01, 0x8c01) AM_DEVREADWRITE("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
 
729
        AM_RANGE(0x8c00, 0x8c00) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_port_w)
 
730
        AM_RANGE(0x8c01, 0x8c01) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
754
731
        AM_RANGE(0xa000, 0xbfff) AM_RAM
755
732
ADDRESS_MAP_END
756
733
 
757
 
static ADDRESS_MAP_START( raimais_2_map, AS_PROGRAM, 8 )
 
734
static ADDRESS_MAP_START( raimais_2_map, AS_PROGRAM, 8, taitol_state )
758
735
        AM_RANGE(0x0000, 0xbfff) AM_ROM
759
736
        AM_RANGE(0xc000, 0xdfff) AM_RAM
760
737
        AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_SHARE("share1")
761
738
ADDRESS_MAP_END
762
739
 
763
740
 
764
 
static WRITE8_HANDLER( sound_bankswitch_w )
 
741
WRITE8_MEMBER(taitol_state::sound_bankswitch_w)
765
742
{
766
 
        UINT8 *RAM = space->machine().region("audiocpu")->base();
 
743
        UINT8 *RAM = memregion("audiocpu")->base();
767
744
        int banknum = (data - 1) & 3;
768
745
 
769
 
        memory_set_bankptr (space->machine(), "bank7", &RAM [0x10000 + (banknum * 0x4000)]);
 
746
        membank ("bank7")->set_base (&RAM [0x10000 + (banknum * 0x4000)]);
770
747
}
771
748
 
772
 
static ADDRESS_MAP_START( raimais_3_map, AS_PROGRAM, 8 )
 
749
static ADDRESS_MAP_START( raimais_3_map, AS_PROGRAM, 8, taitol_state )
773
750
        AM_RANGE(0x0000, 0x3fff) AM_ROM
774
751
        AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank7")
775
752
        AM_RANGE(0xc000, 0xdfff) AM_RAM
776
 
        AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ymsnd", ym2610_r, ym2610_w)
777
 
        AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_slave_port_w)
778
 
        AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
 
753
        AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
 
754
        AM_RANGE(0xe200, 0xe200) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_slave_port_w)
 
755
        AM_RANGE(0xe201, 0xe201) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
779
756
        AM_RANGE(0xe400, 0xe403) AM_WRITENOP /* pan */
780
757
        AM_RANGE(0xe600, 0xe600) AM_WRITENOP /* ? */
781
758
        AM_RANGE(0xee00, 0xee00) AM_WRITENOP /* ? */
784
761
ADDRESS_MAP_END
785
762
 
786
763
 
787
 
static ADDRESS_MAP_START( champwr_map, AS_PROGRAM, 8 )
 
764
static ADDRESS_MAP_START( champwr_map, AS_PROGRAM, 8, taitol_state )
788
765
        COMMON_BANKS_MAP
789
766
        AM_RANGE(0x8000, 0x9fff) AM_RAM
790
767
        AM_RANGE(0xa000, 0xbfff) AM_RAM AM_SHARE("share1")
791
768
ADDRESS_MAP_END
792
769
 
793
 
static ADDRESS_MAP_START( champwr_2_map, AS_PROGRAM, 8 )
 
770
static ADDRESS_MAP_START( champwr_2_map, AS_PROGRAM, 8, taitol_state )
794
771
        AM_RANGE(0x0000, 0x7fff) AM_ROM
795
772
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank6")
796
773
        AM_RANGE(0xc000, 0xdfff) AM_RAM AM_SHARE("share1")
801
778
        AM_RANGE(0xe004, 0xe004) AM_WRITE(control2_w)
802
779
        AM_RANGE(0xe007, 0xe007) AM_READ_PORT("IN2")
803
780
        AM_RANGE(0xe008, 0xe00f) AM_READNOP
804
 
        AM_RANGE(0xe800, 0xe800) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_port_w)
805
 
        AM_RANGE(0xe801, 0xe801) AM_DEVREADWRITE("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
 
781
        AM_RANGE(0xe800, 0xe800) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_port_w)
 
782
        AM_RANGE(0xe801, 0xe801) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
806
783
        AM_RANGE(0xf000, 0xf000) AM_READWRITE(rombank2switch_r, rombank2switch_w)
807
784
ADDRESS_MAP_END
808
785
 
809
 
static ADDRESS_MAP_START( champwr_3_map, AS_PROGRAM, 8 )
 
786
static ADDRESS_MAP_START( champwr_3_map, AS_PROGRAM, 8, taitol_state )
810
787
        AM_RANGE(0x0000, 0x3fff) AM_ROM
811
788
        AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank7")
812
789
        AM_RANGE(0x8000, 0x8fff) AM_RAM
813
 
        AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2203_r, ym2203_w)
814
 
        AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_slave_port_w)
815
 
        AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
 
790
        AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
 
791
        AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_slave_port_w)
 
792
        AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
816
793
        AM_RANGE(0xb000, 0xb000) AM_WRITE(champwr_msm5205_hi_w)
817
794
        AM_RANGE(0xc000, 0xc000) AM_WRITE(champwr_msm5205_lo_w)
818
 
        AM_RANGE(0xd000, 0xd000) AM_DEVWRITE("msm", champwr_msm5205_start_w)
819
 
        AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("msm", champwr_msm5205_stop_w)
 
795
        AM_RANGE(0xd000, 0xd000) AM_DEVWRITE_LEGACY("msm", champwr_msm5205_start_w)
 
796
        AM_RANGE(0xe000, 0xe000) AM_DEVWRITE_LEGACY("msm", champwr_msm5205_stop_w)
820
797
ADDRESS_MAP_END
821
798
 
822
799
 
823
800
 
824
 
static ADDRESS_MAP_START( kurikint_map, AS_PROGRAM, 8 )
 
801
static ADDRESS_MAP_START( kurikint_map, AS_PROGRAM, 8, taitol_state )
825
802
        COMMON_BANKS_MAP
826
803
        AM_RANGE(0x8000, 0x9fff) AM_RAM
827
804
        AM_RANGE(0xa000, 0xa7ff) AM_RAM AM_SHARE("share1")
829
806
        AM_RANGE(0xa801, 0xa801) AM_WRITE(mux_ctrl_w) AM_READNOP        // Watchdog or interrupt ack (value ignored)
830
807
ADDRESS_MAP_END
831
808
 
832
 
static ADDRESS_MAP_START( kurikint_2_map, AS_PROGRAM, 8 )
 
809
static ADDRESS_MAP_START( kurikint_2_map, AS_PROGRAM, 8, taitol_state )
833
810
        AM_RANGE(0x0000, 0x7fff) AM_ROM
834
811
        AM_RANGE(0xc000, 0xdfff) AM_RAM
835
812
        AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_SHARE("share1")
836
 
        AM_RANGE(0xe800, 0xe801) AM_DEVREADWRITE("ymsnd", ym2203_r, ym2203_w)
 
813
        AM_RANGE(0xe800, 0xe801) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
837
814
#if 0
838
815
        AM_RANGE(0xc000, 0xc000) AM_WRITE(rombank2switch_w)
839
816
        AM_RANGE(0xd000, 0xd000) AM_READ_PORT("DSWA")
846
823
 
847
824
 
848
825
 
849
 
static ADDRESS_MAP_START( puzznic_map, AS_PROGRAM, 8 )
 
826
static ADDRESS_MAP_START( puzznic_map, AS_PROGRAM, 8, taitol_state )
850
827
        COMMON_BANKS_MAP
851
828
        COMMON_SINGLE_MAP
852
829
        AM_RANGE(0xa800, 0xa800) AM_READNOP     // Watchdog
857
834
ADDRESS_MAP_END
858
835
 
859
836
/* bootleg, doesn't have the MCU */
860
 
static ADDRESS_MAP_START( puzznici_map, AS_PROGRAM, 8 )
 
837
static ADDRESS_MAP_START( puzznici_map, AS_PROGRAM, 8, taitol_state )
861
838
        COMMON_BANKS_MAP
862
839
        COMMON_SINGLE_MAP
863
840
        AM_RANGE(0xa800, 0xa800) AM_READNOP     // Watchdog
869
846
ADDRESS_MAP_END
870
847
 
871
848
 
872
 
static ADDRESS_MAP_START( plotting_map, AS_PROGRAM, 8 )
 
849
static ADDRESS_MAP_START( plotting_map, AS_PROGRAM, 8, taitol_state )
873
850
        COMMON_BANKS_MAP
874
851
        COMMON_SINGLE_MAP
875
852
        AM_RANGE(0xa800, 0xa800) AM_WRITENOP    // Watchdog or interrupt ack
877
854
ADDRESS_MAP_END
878
855
 
879
856
 
880
 
static ADDRESS_MAP_START( palamed_map, AS_PROGRAM, 8 )
 
857
static ADDRESS_MAP_START( palamed_map, AS_PROGRAM, 8, taitol_state )
881
858
        COMMON_BANKS_MAP
882
859
        COMMON_SINGLE_MAP
883
860
        AM_RANGE(0xa800, 0xa800) AM_READ_PORT("IN0")
889
866
ADDRESS_MAP_END
890
867
 
891
868
 
892
 
static ADDRESS_MAP_START( cachat_map, AS_PROGRAM, 8 )
 
869
static ADDRESS_MAP_START( cachat_map, AS_PROGRAM, 8, taitol_state )
893
870
        COMMON_BANKS_MAP
894
871
        COMMON_SINGLE_MAP
895
872
        AM_RANGE(0xa800, 0xa800) AM_READ_PORT("IN0")
902
879
ADDRESS_MAP_END
903
880
 
904
881
 
905
 
static ADDRESS_MAP_START( horshoes_map, AS_PROGRAM, 8 )
 
882
static ADDRESS_MAP_START( horshoes_map, AS_PROGRAM, 8, taitol_state )
906
883
        COMMON_BANKS_MAP
907
884
        COMMON_SINGLE_MAP
908
885
        AM_RANGE(0xa800, 0xa800) AM_READ(horshoes_tracky_lo_r)
916
893
        AM_RANGE(0xbc00, 0xbc00) AM_WRITENOP
917
894
ADDRESS_MAP_END
918
895
 
919
 
static ADDRESS_MAP_START( evilston_map, AS_PROGRAM, 8 )
 
896
static ADDRESS_MAP_START( evilston_map, AS_PROGRAM, 8, taitol_state )
920
897
        COMMON_BANKS_MAP
921
898
        AM_RANGE(0x8000, 0x9fff) AM_RAM
922
899
        AM_RANGE(0xa000, 0xa7ff) AM_RAM AM_SHARE("share1")
928
905
        AM_RANGE(0xa807, 0xa807) AM_READ_PORT("IN2")
929
906
ADDRESS_MAP_END
930
907
 
931
 
static ADDRESS_MAP_START( evilston_2_map, AS_PROGRAM, 8 )
 
908
static ADDRESS_MAP_START( evilston_2_map, AS_PROGRAM, 8, taitol_state )
932
909
        AM_RANGE(0x0000, 0xbfff) AM_ROM
933
910
        AM_RANGE(0xc000, 0xdfff) AM_RAM
934
911
        AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_SHARE("share1")
935
 
        AM_RANGE(0xe800, 0xe801) AM_DEVREADWRITE("ymsnd", ym2203_r, ym2203_w)
 
912
        AM_RANGE(0xe800, 0xe801) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
936
913
        AM_RANGE(0xf000, 0xf7ff) AM_ROMBANK("bank7")
937
914
ADDRESS_MAP_END
938
915
 
1555
1532
        PORT_DIPSETTING(    0x08, "Mode A" )
1556
1533
        PORT_DIPSETTING(    0x00, "Mode B" )
1557
1534
        PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )           PORT_DIPLOCATION("SW1:5,6")
1558
 
        PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1559
 
        PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1560
 
        PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1561
 
        PORT_DIPSETTING(    0x20, DEF_STR( 1C_2C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1562
 
        PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
1563
 
        PORT_DIPSETTING(    0x10, DEF_STR( 3C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
1564
 
        PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
1565
 
        PORT_DIPSETTING(    0x20, DEF_STR( 1C_4C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
 
1535
        PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1536
        PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1537
        PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1538
        PORT_DIPSETTING(    0x20, DEF_STR( 1C_2C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1539
        PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
 
1540
        PORT_DIPSETTING(    0x10, DEF_STR( 3C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
 
1541
        PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
 
1542
        PORT_DIPSETTING(    0x20, DEF_STR( 1C_4C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
1566
1543
        PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) )           PORT_DIPLOCATION("SW1:7,8")
1567
 
        PORT_DIPSETTING(    0x40, DEF_STR( 2C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1568
 
        PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1569
 
        PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1570
 
        PORT_DIPSETTING(    0x80, DEF_STR( 1C_2C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x08)
1571
 
        PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
1572
 
        PORT_DIPSETTING(    0x40, DEF_STR( 3C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
1573
 
        PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
1574
 
        PORT_DIPSETTING(    0x80, DEF_STR( 1C_4C ) ) PORT_CONDITION("DSWA", 0x08, PORTCOND_EQUALS, 0x00)
 
1544
        PORT_DIPSETTING(    0x40, DEF_STR( 2C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1545
        PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1546
        PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1547
        PORT_DIPSETTING(    0x80, DEF_STR( 1C_2C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x08)
 
1548
        PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
 
1549
        PORT_DIPSETTING(    0x40, DEF_STR( 3C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
 
1550
        PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
 
1551
        PORT_DIPSETTING(    0x80, DEF_STR( 1C_4C ) ) PORT_CONDITION("DSWA", 0x08, EQUALS, 0x00)
1575
1552
 
1576
1553
        PORT_START("DSWB")
1577
1554
        TAITO_DIFFICULTY_LOC(SW2)                               /* Difficulty controls the number of hits requiered to destroy enemies */
1807
1784
        if (state->m_cur_bank != (data & 0x03))
1808
1785
        {
1809
1786
                int bankaddress;
1810
 
                UINT8 *RAM = device->machine().region("audiocpu")->base();
 
1787
                UINT8 *RAM = state->memregion("audiocpu")->base();
1811
1788
 
1812
1789
                state->m_cur_bank = data & 0x03;
1813
1790
                bankaddress = 0x10000 + (state->m_cur_bank - 1) * 0x4000;
1814
 
                memory_set_bankptr(device->machine(), "bank7", &RAM[bankaddress]);
 
1791
                state->membank("bank7")->set_base(&RAM[bankaddress]);
1815
1792
                //logerror ("YM2203 bank change val=%02x  pc=%04x\n", state->m_cur_bank, cpu_get_pc(&space->device()) );
1816
1793
        }
1817
1794
}
1938
1915
        /* sound hardware */
1939
1916
        MCFG_SOUND_MODIFY("ymsnd")
1940
1917
        MCFG_SOUND_CONFIG(ym2203_interface_champwr)
1941
 
        MCFG_SOUND_ROUTE(0, "mono", 0.20)
1942
 
        MCFG_SOUND_ROUTE(1, "mono", 0.20)
1943
 
        MCFG_SOUND_ROUTE(2, "mono", 0.20)
1944
 
        MCFG_SOUND_ROUTE(3, "mono", 0.80)
1945
1918
 
1946
1919
        MCFG_SOUND_ADD("msm", MSM5205, XTAL_384kHz)
1947
1920
        MCFG_SOUND_CONFIG(msm5205_config)
2745
2718
                                v |= 1 << (7 - j);
2746
2719
                tab[i] = v;
2747
2720
        }
2748
 
        p = machine.region("maincpu")->base();
 
2721
        p = machine.root_device().memregion("maincpu")->base();
2749
2722
        for (i = 0; i < 0x20000; i++)
2750
2723
        {
2751
2724
                *p = tab[*p];