5
5
/******************************************************************************/
7
WRITE16_HANDLER(tatsumi_sprite_control_w)
7
WRITE16_MEMBER(tatsumi_state::tatsumi_sprite_control_w)
9
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
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COMBINE_DATA(&state->m_sprite_control_ram[offset]);
9
COMBINE_DATA(&m_sprite_control_ram[offset]);
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11
/* 0xe0 is bank switch, others unknown */
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12
// if ((offset==0xe0 && data&0xefff) || offset!=0xe0)
14
// logerror("%08x: Tatsumi TZB215 sprite control %04x %08x\n", cpu_get_pc(&space->device()), offset, data);
13
// logerror("%08x: Tatsumi TZB215 sprite control %04x %08x\n", cpu_get_pc(&space.device()), offset, data);
17
16
/******************************************************************************/
19
WRITE16_HANDLER( apache3_road_z_w )
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WRITE16_MEMBER(tatsumi_state::apache3_road_z_w)
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tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
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state->m_apache3_road_z = data & 0xff;
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m_apache3_road_z = data & 0xff;
25
WRITE8_HANDLER( apache3_road_x_w )
23
WRITE8_MEMBER(tatsumi_state::apache3_road_x_w)
27
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
28
25
// Note: Double buffered. Yes, this is correct :)
29
state->m_apache3_road_x_ram[data] = offset;
32
READ16_HANDLER( roundup5_vram_r )
34
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
35
offset+=((state->m_control_word&0x0c00)>>10) * 0xc000;
36
return state->m_roundup5_vram[offset];
39
WRITE16_HANDLER( roundup5_vram_w )
41
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
42
offset+=((state->m_control_word&0x0c00)>>10) * 0xc000;
26
m_apache3_road_x_ram[data] = offset;
29
READ16_MEMBER(tatsumi_state::roundup5_vram_r)
31
offset+=((m_control_word&0x0c00)>>10) * 0xc000;
32
return m_roundup5_vram[offset];
35
WRITE16_MEMBER(tatsumi_state::roundup5_vram_w)
37
offset+=((m_control_word&0x0c00)>>10) * 0xc000;
44
39
// if (offset>=0x30000)
45
// logerror("effective write to vram %06x %02x (control %04x)\n",offset,data,state->m_control_word);
40
// logerror("effective write to vram %06x %02x (control %04x)\n",offset,data,m_control_word);
47
COMBINE_DATA(&state->m_roundup5_vram[offset]);
42
COMBINE_DATA(&m_roundup5_vram[offset]);
49
44
offset=offset%0xc000;
51
gfx_element_mark_dirty(space->machine().gfx[1],offset/0x10);
46
gfx_element_mark_dirty(machine().gfx[1],offset/0x10);
55
WRITE16_HANDLER( roundup5_palette_w )
50
WRITE16_MEMBER(tatsumi_state::roundup5_palette_w)
57
52
// static int hack=0;
60
COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
55
COMBINE_DATA(&m_generic_paletteram_16[offset]);
62
57
// if (offset==0xbfe)
79
74
// logerror("PAL: %04x %02x\n",offset,data);
82
word = ((space->machine().generic.paletteram.u16[offset] & 0xff)<<8) | (space->machine().generic.paletteram.u16[offset+1] & 0xff);
83
palette_set_color_rgb(space->machine(),offset/2,pal5bit(word >> 10),pal5bit(word >> 5),pal5bit(word >> 0));
77
word = ((m_generic_paletteram_16[offset] & 0xff)<<8) | (m_generic_paletteram_16[offset+1] & 0xff);
78
palette_set_color_rgb(machine(),offset/2,pal5bit(word >> 10),pal5bit(word >> 5),pal5bit(word >> 0));
87
WRITE16_HANDLER( apache3_palette_w )
82
WRITE16_MEMBER(tatsumi_state::apache3_palette_w)
89
84
// static int hack=0;
91
COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
86
COMBINE_DATA(&m_generic_paletteram_16[offset]);
93
88
// if (offset==0xbfe)
110
105
// logerror("PAL: %04x %02x\n",offset,data);
112
data = space->machine().generic.paletteram.u16[offset];
113
palette_set_color_rgb(space->machine(),offset,pal5bit(data >> 10),pal5bit(data >> 5),pal5bit(data >> 0));
107
data = m_generic_paletteram_16[offset];
108
palette_set_color_rgb(machine(),offset,pal5bit(data >> 10),pal5bit(data >> 5),pal5bit(data >> 0));
117
WRITE16_HANDLER( roundup5_text_w )
112
WRITE16_MEMBER(tatsumi_state::roundup5_text_w)
119
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
120
UINT16 *videoram = state->m_videoram;
114
UINT16 *videoram = m_videoram;
121
115
COMBINE_DATA(&videoram[offset]);
122
state->m_tx_layer->mark_tile_dirty(offset);
125
READ16_HANDLER( cyclwarr_videoram0_r )
127
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
128
return state->m_cyclwarr_videoram0[offset];
131
READ16_HANDLER( cyclwarr_videoram1_r )
133
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
134
return state->m_cyclwarr_videoram1[offset];
137
WRITE16_HANDLER( cyclwarr_videoram0_w )
139
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
140
COMBINE_DATA(&state->m_cyclwarr_videoram0[offset]);
143
state->m_layer0->mark_tile_dirty(offset-0x400);
144
state->m_layer1->mark_tile_dirty(offset-0x400);
148
WRITE16_HANDLER( cyclwarr_videoram1_w )
150
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
151
COMBINE_DATA(&state->m_cyclwarr_videoram1[offset]);
154
state->m_layer2->mark_tile_dirty(offset-0x400);
155
state->m_layer3->mark_tile_dirty(offset-0x400);
159
WRITE16_HANDLER( roundup5_crt_w )
161
tatsumi_state *state = space->machine().driver_data<tatsumi_state>();
116
m_tx_layer->mark_tile_dirty(offset);
119
READ16_MEMBER(tatsumi_state::cyclwarr_videoram0_r)
121
return m_cyclwarr_videoram0[offset];
124
READ16_MEMBER(tatsumi_state::cyclwarr_videoram1_r)
126
return m_cyclwarr_videoram1[offset];
129
WRITE16_MEMBER(tatsumi_state::cyclwarr_videoram0_w)
131
COMBINE_DATA(&m_cyclwarr_videoram0[offset]);
134
m_layer0->mark_tile_dirty(offset-0x400);
135
m_layer1->mark_tile_dirty(offset-0x400);
139
WRITE16_MEMBER(tatsumi_state::cyclwarr_videoram1_w)
141
COMBINE_DATA(&m_cyclwarr_videoram1[offset]);
144
m_layer2->mark_tile_dirty(offset-0x400);
145
m_layer3->mark_tile_dirty(offset-0x400);
149
WRITE16_MEMBER(tatsumi_state::roundup5_crt_w)
162
151
if (offset==0 && ACCESSING_BITS_0_7)
163
state->m_roundupt_crt_selected_reg=data&0x3f;
152
m_roundupt_crt_selected_reg=data&0x3f;
164
153
if (offset==1 && ACCESSING_BITS_0_7) {
165
state->m_roundupt_crt_reg[state->m_roundupt_crt_selected_reg]=data;
166
// if (state->m_roundupt_crt_selected_reg!=0xa && state->m_roundupt_crt_selected_reg!=0xb && state->m_roundupt_crt_selected_reg!=29)
167
// logerror("%08x: Crt write %02x %02x\n",cpu_get_pc(&space->device()),state->m_roundupt_crt_selected_reg,data);
154
m_roundupt_crt_reg[m_roundupt_crt_selected_reg]=data;
155
// if (m_roundupt_crt_selected_reg!=0xa && m_roundupt_crt_selected_reg!=0xb && m_roundupt_crt_selected_reg!=29)
156
// logerror("%08x: Crt write %02x %02x\n",cpu_get_pc(&space.device()),m_roundupt_crt_selected_reg,data);