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Viewing changes to src/mame/drivers/xtom3d.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/xtom3d.c
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***************************************************************************/
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#define ADDRESS_MAP_MODERN
41
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#include "emu.h"
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#include "cpu/i386/i386.h"
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        DECLARE_WRITE32_MEMBER( bios_ext4_ram_w );
101
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102
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        DECLARE_WRITE32_MEMBER( bios_ram_w );
 
102
        DECLARE_READ8_MEMBER(at_page8_r);
 
103
        DECLARE_WRITE8_MEMBER(at_page8_w);
 
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        DECLARE_READ8_MEMBER(pc_dma_read_byte);
 
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        DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
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};
104
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105
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// Intel 82439TX System Controller (MXTC)
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                case 0x59: // PAM0
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                {
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                        if (data & 0x10)                // enable RAM access to region 0xf0000 - 0xfffff
145
 
                                memory_set_bankptr(busdevice->machine(), "bios_bank", state->m_bios_ram);
 
148
                                state->membank("bios_bank")->set_base(state->m_bios_ram);
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                        else                                    // disable RAM access (reads go to BIOS ROM)
147
 
                                memory_set_bankptr(busdevice->machine(), "bios_bank", busdevice->machine().region("bios")->base() + 0x10000);
 
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                                state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x10000);
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                        break;
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                }
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                case 0x5a: // PAM1
151
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                {
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                        if (data & 0x1)
153
 
                                memory_set_bankptr(busdevice->machine(), "video_bank1", state->m_isa_ram1);
 
156
                                state->membank("video_bank1")->set_base(state->m_isa_ram1);
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                        else
155
 
                                memory_set_bankptr(busdevice->machine(), "video_bank1", busdevice->machine().region("video_bios")->base() + 0);
 
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                                state->membank("video_bank1")->set_base(state->memregion("video_bios")->base() + 0);
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                        if (data & 0x10)
158
 
                                memory_set_bankptr(busdevice->machine(), "video_bank2", state->m_isa_ram2);
 
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                                state->membank("video_bank2")->set_base(state->m_isa_ram2);
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                        else
160
 
                                memory_set_bankptr(busdevice->machine(), "video_bank2", busdevice->machine().region("video_bios")->base() + 0x4000);
 
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                                state->membank("video_bank2")->set_base(state->memregion("video_bios")->base() + 0x4000);
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                        break;
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                }
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                case 0x5e: // PAM5
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                {
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                        if (data & 0x1)
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                                memory_set_bankptr(busdevice->machine(), "bios_ext1", state->m_bios_ext1_ram);
 
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                                state->membank("bios_ext1")->set_base(state->m_bios_ext1_ram);
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                        else
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                                memory_set_bankptr(busdevice->machine(), "bios_ext1", busdevice->machine().region("bios")->base() + 0);
 
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                                state->membank("bios_ext1")->set_base(state->memregion("bios")->base() + 0);
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                        if (data & 0x10)
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                                memory_set_bankptr(busdevice->machine(), "bios_ext2", state->m_bios_ext2_ram);
 
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                                state->membank("bios_ext2")->set_base(state->m_bios_ext2_ram);
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                        else
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                                memory_set_bankptr(busdevice->machine(), "bios_ext2", busdevice->machine().region("bios")->base() + 0x4000);
 
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                                state->membank("bios_ext2")->set_base(state->memregion("bios")->base() + 0x4000);
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                        break;
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                }
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                case 0x5f: // PAM6
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                {
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                        if (data & 0x1)
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                                memory_set_bankptr(busdevice->machine(), "bios_ext3", state->m_bios_ext3_ram);
 
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                                state->membank("bios_ext3")->set_base(state->m_bios_ext3_ram);
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                        else
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                                memory_set_bankptr(busdevice->machine(), "bios_ext3", busdevice->machine().region("bios")->base() + 0x8000);
 
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                                state->membank("bios_ext3")->set_base(state->memregion("bios")->base() + 0x8000);
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                        if (data & 0x10)
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                                memory_set_bankptr(busdevice->machine(), "bios_ext4", state->m_bios_ext4_ram);
 
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                                state->membank("bios_ext4")->set_base(state->m_bios_ext4_ram);
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                        else
188
 
                                memory_set_bankptr(busdevice->machine(), "bios_ext4", busdevice->machine().region("bios")->base() + 0xc000);
 
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                                state->membank("bios_ext4")->set_base(state->memregion("bios")->base() + 0xc000);
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                        break;
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                }
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        ide_controller32_w(device, 0x3f0/4 + offset, data, mem_mask);
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}
392
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static READ8_HANDLER(at_page8_r)
 
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READ8_MEMBER(xtom3d_state::at_page8_r)
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{
395
 
        xtom3d_state *state = space->machine().driver_data<xtom3d_state>();
396
 
        UINT8 data = state->m_at_pages[offset % 0x10];
 
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        UINT8 data = m_at_pages[offset % 0x10];
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        switch(offset % 8) {
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        case 1:
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                data = state->m_dma_offset[(offset / 8) & 1][2];
 
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                data = m_dma_offset[(offset / 8) & 1][2];
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                break;
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        case 2:
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                data = state->m_dma_offset[(offset / 8) & 1][3];
 
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                data = m_dma_offset[(offset / 8) & 1][3];
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                break;
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        case 3:
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                data = state->m_dma_offset[(offset / 8) & 1][1];
 
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                data = m_dma_offset[(offset / 8) & 1][1];
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                break;
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        case 7:
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                data = state->m_dma_offset[(offset / 8) & 1][0];
 
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                data = m_dma_offset[(offset / 8) & 1][0];
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                break;
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        }
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        return data;
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}
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static WRITE8_HANDLER(at_page8_w)
 
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WRITE8_MEMBER(xtom3d_state::at_page8_w)
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{
418
 
        xtom3d_state *state = space->machine().driver_data<xtom3d_state>();
419
 
        state->m_at_pages[offset % 0x10] = data;
 
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        m_at_pages[offset % 0x10] = data;
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        switch(offset % 8) {
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        case 1:
423
 
                state->m_dma_offset[(offset / 8) & 1][2] = data;
 
424
                m_dma_offset[(offset / 8) & 1][2] = data;
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                break;
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        case 2:
426
 
                state->m_dma_offset[(offset / 8) & 1][3] = data;
 
427
                m_dma_offset[(offset / 8) & 1][3] = data;
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                break;
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        case 3:
429
 
                state->m_dma_offset[(offset / 8) & 1][1] = data;
 
430
                m_dma_offset[(offset / 8) & 1][1] = data;
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                break;
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        case 7:
432
 
                state->m_dma_offset[(offset / 8) & 1][0] = data;
 
433
                m_dma_offset[(offset / 8) & 1][0] = data;
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                break;
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        }
435
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}
436
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437
 
static READ32_HANDLER(at_page32_r)
438
 
{
439
 
        return read32le_with_read8_handler(at_page8_r, space, offset, mem_mask);
440
 
}
441
 
 
442
 
 
443
 
static WRITE32_HANDLER(at_page32_w)
444
 
{
445
 
        write32le_with_write8_handler(at_page8_w, space, offset, data, mem_mask);
446
 
}
447
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448
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static READ8_DEVICE_HANDLER(at_dma8237_2_r)
449
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{
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}
478
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479
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480
 
static READ8_HANDLER( pc_dma_read_byte )
 
471
READ8_MEMBER(xtom3d_state::pc_dma_read_byte)
481
472
{
482
 
        xtom3d_state *state = space->machine().driver_data<xtom3d_state>();
483
 
        offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
 
473
        offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
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                & 0xFF0000;
485
475
 
486
 
        return space->read_byte(page_offset + offset);
 
476
        return space.read_byte(page_offset + offset);
487
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}
488
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489
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490
 
static WRITE8_HANDLER( pc_dma_write_byte )
 
480
WRITE8_MEMBER(xtom3d_state::pc_dma_write_byte)
491
481
{
492
 
        xtom3d_state *state = space->machine().driver_data<xtom3d_state>();
493
 
        offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
 
482
        offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
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                & 0xFF0000;
495
484
 
496
 
        space->write_byte(page_offset + offset, data);
 
485
        space.write_byte(page_offset + offset, data);
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}
498
487
 
499
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static void set_dma_channel(device_t *device, int channel, int state)
511
500
{
512
501
        DEVCB_LINE(pc_dma_hrq_changed),
513
502
        DEVCB_NULL,
514
 
        DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
515
 
        DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
 
503
        DEVCB_DRIVER_MEMBER(xtom3d_state, pc_dma_read_byte),
 
504
        DEVCB_DRIVER_MEMBER(xtom3d_state, pc_dma_write_byte),
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505
        { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
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506
        { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
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        { DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
549
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        AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, 0xffffffff)
550
539
        AM_RANGE(0x0060, 0x006f) AM_READWRITE_LEGACY(kbdc8042_32le_r,                   kbdc8042_32le_w)
551
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        AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff) /* todo: nvram (CMOS Setup Save)*/
552
 
        AM_RANGE(0x0080, 0x009f) AM_READWRITE_LEGACY(at_page32_r,                               at_page32_w)
 
541
        AM_RANGE(0x0080, 0x009f) AM_READWRITE8(at_page8_r,      at_page8_w, 0xffffffff)
553
542
        AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8_LEGACY("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
554
543
        AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE_LEGACY("dma8237_2", at32_dma8237_2_r, at32_dma8237_2_w)
555
544
        AM_RANGE(0x00e8, 0x00ef) AM_NOP
677
666
 
678
667
static MACHINE_RESET( xtom3d )
679
668
{
680
 
        memory_set_bankptr(machine, "bios_bank", machine.region("bios")->base() + 0x10000);
681
 
        memory_set_bankptr(machine, "bios_ext1", machine.region("bios")->base() + 0);
682
 
        memory_set_bankptr(machine, "bios_ext2", machine.region("bios")->base() + 0x4000);
683
 
        memory_set_bankptr(machine, "bios_ext3", machine.region("bios")->base() + 0x8000);
684
 
        memory_set_bankptr(machine, "bios_ext4", machine.region("bios")->base() + 0xc000);
685
 
        memory_set_bankptr(machine, "video_bank1", machine.region("video_bios")->base() + 0);
686
 
        memory_set_bankptr(machine, "video_bank2", machine.region("video_bios")->base() + 0x4000);
 
669
        machine.root_device().membank("bios_bank")->set_base(machine.root_device().memregion("bios")->base() + 0x10000);
 
670
        machine.root_device().membank("bios_ext1")->set_base(machine.root_device().memregion("bios")->base() + 0);
 
671
        machine.root_device().membank("bios_ext2")->set_base(machine.root_device().memregion("bios")->base() + 0x4000);
 
672
        machine.root_device().membank("bios_ext3")->set_base(machine.root_device().memregion("bios")->base() + 0x8000);
 
673
        machine.root_device().membank("bios_ext4")->set_base(machine.root_device().memregion("bios")->base() + 0xc000);
 
674
        machine.root_device().membank("video_bank1")->set_base(machine.root_device().memregion("video_bios")->base() + 0);
 
675
        machine.root_device().membank("video_bank2")->set_base(machine.root_device().memregion("video_bios")->base() + 0x4000);
687
676
}
688
677
 
689
678
 
707
696
        MCFG_PCI_BUS_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
708
697
        MCFG_PCI_BUS_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
709
698
 
710
 
        MCFG_IDE_CONTROLLER_ADD("ide", ide_interrupt)
 
699
        MCFG_IDE_CONTROLLER_ADD("ide", ide_interrupt, ide_devices, "hdd", NULL)
711
700
 
712
701
        /* video hardware */
713
702
        MCFG_FRAGMENT_ADD( pcvideo_vga )