← Back to branch summary

~ubuntu-branches/debian/sid/mame/sid

« back to all changes in this revision

Viewing changes to src/mame/drivers/poolshrk.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

Show diffs side-by-side

added added

removed removed

Lines of Context:
src/mame/drivers/poolshrk.c
14
14
 
15
15
static DRIVER_INIT( poolshrk )
16
16
{
17
 
        UINT8* pSprite = machine.region("gfx1")->base();
18
 
        UINT8* pOffset = machine.region("proms")->base();
 
17
        UINT8* pSprite = machine.root_device().memregion("gfx1")->base();
 
18
        UINT8* pOffset = machine.root_device().memregion("proms")->base();
19
19
 
20
20
        int i;
21
21
        int j;
45
45
}
46
46
 
47
47
 
48
 
static WRITE8_HANDLER( poolshrk_da_latch_w )
 
48
WRITE8_MEMBER(poolshrk_state::poolshrk_da_latch_w)
49
49
{
50
 
        poolshrk_state *state = space->machine().driver_data<poolshrk_state>();
51
 
        state->m_da_latch = data & 15;
 
50
        m_da_latch = data & 15;
52
51
}
53
52
 
54
53
 
55
 
static WRITE8_HANDLER( poolshrk_led_w )
 
54
WRITE8_MEMBER(poolshrk_state::poolshrk_led_w)
56
55
{
57
56
        if (offset & 2)
58
 
                set_led_status(space->machine(), 0, offset & 1);
 
57
                set_led_status(machine(), 0, offset & 1);
59
58
        if (offset & 4)
60
 
                set_led_status(space->machine(), 1, offset & 1);
 
59
                set_led_status(machine(), 1, offset & 1);
61
60
}
62
61
 
63
62
 
64
 
static WRITE8_HANDLER( poolshrk_watchdog_w )
 
63
WRITE8_MEMBER(poolshrk_state::poolshrk_watchdog_w)
65
64
{
66
65
        if ((offset & 3) == 3)
67
66
        {
70
69
}
71
70
 
72
71
 
73
 
static READ8_HANDLER( poolshrk_input_r )
 
72
READ8_MEMBER(poolshrk_state::poolshrk_input_r)
74
73
{
75
 
        poolshrk_state *state = space->machine().driver_data<poolshrk_state>();
76
74
        static const char *const portnames[] = { "IN0", "IN1", "IN2", "IN3" };
77
 
        UINT8 val = input_port_read(space->machine(), portnames[offset & 3]);
78
 
 
79
 
        int x = input_port_read(space->machine(), (offset & 1) ? "AN1" : "AN0");
80
 
        int y = input_port_read(space->machine(), (offset & 1) ? "AN3" : "AN2");
81
 
 
82
 
        if (x >= state->m_da_latch) val |= 8;
83
 
        if (y >= state->m_da_latch) val |= 4;
 
75
        UINT8 val = ioport(portnames[offset & 3])->read();
 
76
 
 
77
        int x = ioport((offset & 1) ? "AN1" : "AN0")->read();
 
78
        int y = ioport((offset & 1) ? "AN3" : "AN2")->read();
 
79
 
 
80
        if (x >= m_da_latch) val |= 8;
 
81
        if (y >= m_da_latch) val |= 4;
84
82
 
85
83
        if ((offset & 3) == 3)
86
84
        {
91
89
}
92
90
 
93
91
 
94
 
static READ8_HANDLER( poolshrk_irq_reset_r )
 
92
READ8_MEMBER(poolshrk_state::poolshrk_irq_reset_r)
95
93
{
96
 
        cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
 
94
        cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
97
95
 
98
96
        return 0;
99
97
}
100
98
 
101
99
 
102
 
static ADDRESS_MAP_START( poolshrk_cpu_map, AS_PROGRAM, 8 )
 
100
static ADDRESS_MAP_START( poolshrk_cpu_map, AS_PROGRAM, 8, poolshrk_state )
103
101
        ADDRESS_MAP_GLOBAL_MASK(0x7fff)
104
102
        AM_RANGE(0x0000, 0x00ff) AM_MIRROR(0x2300) AM_RAM
105
 
        AM_RANGE(0x0400, 0x07ff) AM_MIRROR(0x2000) AM_WRITEONLY AM_BASE_MEMBER(poolshrk_state, m_playfield_ram)
106
 
        AM_RANGE(0x0800, 0x080f) AM_MIRROR(0x23f0) AM_WRITEONLY AM_BASE_MEMBER(poolshrk_state, m_hpos_ram)
107
 
        AM_RANGE(0x0c00, 0x0c0f) AM_MIRROR(0x23f0) AM_WRITEONLY AM_BASE_MEMBER(poolshrk_state, m_vpos_ram)
 
103
        AM_RANGE(0x0400, 0x07ff) AM_MIRROR(0x2000) AM_WRITEONLY AM_SHARE("playfield_ram")
 
104
        AM_RANGE(0x0800, 0x080f) AM_MIRROR(0x23f0) AM_WRITEONLY AM_SHARE("hpos_ram")
 
105
        AM_RANGE(0x0c00, 0x0c0f) AM_MIRROR(0x23f0) AM_WRITEONLY AM_SHARE("vpos_ram")
108
106
        AM_RANGE(0x1000, 0x13ff) AM_MIRROR(0x2000) AM_READWRITE(poolshrk_input_r, poolshrk_watchdog_w)
109
 
        AM_RANGE(0x1400, 0x17ff) AM_MIRROR(0x2000) AM_DEVWRITE("discrete", poolshrk_scratch_sound_w)
110
 
        AM_RANGE(0x1800, 0x1bff) AM_MIRROR(0x2000) AM_DEVWRITE("discrete", poolshrk_score_sound_w)
111
 
        AM_RANGE(0x1c00, 0x1fff) AM_MIRROR(0x2000) AM_DEVWRITE("discrete", poolshrk_click_sound_w)
 
107
        AM_RANGE(0x1400, 0x17ff) AM_MIRROR(0x2000) AM_DEVWRITE_LEGACY("discrete", poolshrk_scratch_sound_w)
 
108
        AM_RANGE(0x1800, 0x1bff) AM_MIRROR(0x2000) AM_DEVWRITE_LEGACY("discrete", poolshrk_score_sound_w)
 
109
        AM_RANGE(0x1c00, 0x1fff) AM_MIRROR(0x2000) AM_DEVWRITE_LEGACY("discrete", poolshrk_click_sound_w)
112
110
        AM_RANGE(0x4000, 0x4000) AM_NOP /* diagnostic ROM location */
113
111
        AM_RANGE(0x6000, 0x63ff) AM_WRITE(poolshrk_da_latch_w)
114
 
        AM_RANGE(0x6400, 0x67ff) AM_DEVWRITE("discrete", poolshrk_bump_sound_w)
 
112
        AM_RANGE(0x6400, 0x67ff) AM_DEVWRITE_LEGACY("discrete", poolshrk_bump_sound_w)
115
113
        AM_RANGE(0x6800, 0x6bff) AM_READ(poolshrk_irq_reset_r)
116
114
        AM_RANGE(0x6c00, 0x6fff) AM_WRITE(poolshrk_led_w)
117
115
        AM_RANGE(0x7000, 0x7fff) AM_ROM