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Viewing changes to src/mame/drivers/shougi.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/shougi.c
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{
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public:
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        shougi_state(const machine_config &mconfig, device_type type, const char *tag)
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                : driver_device(mconfig, type, tag) { }
 
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                : driver_device(mconfig, type, tag) ,
 
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                m_videoram(*this, "videoram"){ }
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        UINT8 *m_videoram;
 
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        required_shared_ptr<UINT8> m_videoram;
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        int m_nmi_enabled;
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        //UINT8 *m_cpu_sharedram;
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        //UINT8 m_cpu_sharedram_control_val;
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        int m_r;
 
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        DECLARE_WRITE8_MEMBER(cpu_sharedram_sub_w);
 
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        DECLARE_WRITE8_MEMBER(cpu_sharedram_main_w);
 
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        DECLARE_READ8_MEMBER(cpu_sharedram_r);
 
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        DECLARE_WRITE8_MEMBER(cpu_shared_ctrl_sub_w);
 
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        DECLARE_WRITE8_MEMBER(cpu_shared_ctrl_main_w);
 
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        DECLARE_WRITE8_MEMBER(shougi_watchdog_reset_w);
 
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        DECLARE_WRITE8_MEMBER(shougi_mcu_halt_off_w);
 
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        DECLARE_WRITE8_MEMBER(shougi_mcu_halt_on_w);
 
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        DECLARE_WRITE8_MEMBER(nmi_disable_and_clear_line_w);
 
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        DECLARE_WRITE8_MEMBER(nmi_enable_w);
 
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        DECLARE_READ8_MEMBER(dummy_r);
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};
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static PALETTE_INIT( shougi )
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{
 
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        const UINT8 *color_prom = machine.root_device().memregion("proms")->base();
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        int i;
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        static const int resistances_b[2]  = { 470, 220 };
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        static const int resistances_rg[3] = { 1000, 470, 220 };
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//to do:
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// add separate sharedram/r/w() for both CPUs and use control value to verify access
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static WRITE8_HANDLER ( cpu_sharedram_sub_w )
 
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WRITE8_MEMBER(shougi_state::cpu_sharedram_sub_w)
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{
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        if (cpu_sharedram_control_val!=0) logerror("sub CPU access to shared RAM when access set for main cpu\n");
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        cpu_sharedram[offset] = data;
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}
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static WRITE8_HANDLER ( cpu_sharedram_main_w )
 
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WRITE8_MEMBER(shougi_state::cpu_sharedram_main_w)
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{
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        if (cpu_sharedram_control_val!=1) logerror("main CPU access to shared RAM when access set for sub cpu\n");
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        cpu_sharedram[offset] = data;
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}
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static READ8_HANDLER ( cpu_sharedram_r )
 
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READ8_MEMBER(shougi_state::cpu_sharedram_r)
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{
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        return cpu_sharedram[offset];
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}
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#endif
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static WRITE8_HANDLER ( cpu_shared_ctrl_sub_w )
 
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WRITE8_MEMBER(shougi_state::cpu_shared_ctrl_sub_w)
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{
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        //cpu_sharedram_control_val = 0;
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        //logerror("cpu_sharedram_ctrl=SUB");
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}
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static WRITE8_HANDLER ( cpu_shared_ctrl_main_w )
 
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WRITE8_MEMBER(shougi_state::cpu_shared_ctrl_main_w)
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{
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        //cpu_sharedram_control_val = 1;
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        //logerror("cpu_sharedram_ctrl=MAIN");
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}
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static WRITE8_HANDLER( shougi_watchdog_reset_w )
 
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WRITE8_MEMBER(shougi_state::shougi_watchdog_reset_w)
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{
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        watchdog_reset_w(space,0,data);
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}
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static WRITE8_HANDLER( shougi_mcu_halt_off_w )
 
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WRITE8_MEMBER(shougi_state::shougi_mcu_halt_off_w)
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{
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        /* logerror("mcu HALT OFF"); */
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        cputag_set_input_line(space->machine(), "mcu", INPUT_LINE_HALT, CLEAR_LINE);
 
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        cputag_set_input_line(machine(), "mcu", INPUT_LINE_HALT, CLEAR_LINE);
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}
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static WRITE8_HANDLER( shougi_mcu_halt_on_w )
 
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WRITE8_MEMBER(shougi_state::shougi_mcu_halt_on_w)
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{
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        /* logerror("mcu HALT ON"); */
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        cputag_set_input_line(space->machine(), "mcu", INPUT_LINE_HALT,ASSERT_LINE);
 
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        cputag_set_input_line(machine(), "mcu", INPUT_LINE_HALT,ASSERT_LINE);
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}
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static WRITE8_HANDLER( nmi_disable_and_clear_line_w )
 
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WRITE8_MEMBER(shougi_state::nmi_disable_and_clear_line_w)
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{
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        shougi_state *state = space->machine().driver_data<shougi_state>();
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        state->m_nmi_enabled = 0; /* disable NMIs */
 
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        m_nmi_enabled = 0; /* disable NMIs */
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        /* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */
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        cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
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        cputag_set_input_line(space->machine(), "sub", INPUT_LINE_NMI, CLEAR_LINE);
 
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        cputag_set_input_line(machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
 
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        cputag_set_input_line(machine(), "sub", INPUT_LINE_NMI, CLEAR_LINE);
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}
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static WRITE8_HANDLER( nmi_enable_w )
 
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WRITE8_MEMBER(shougi_state::nmi_enable_w)
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{
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        shougi_state *state = space->machine().driver_data<shougi_state>();
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        state->m_nmi_enabled = 1; /* enable NMIs */
 
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        m_nmi_enabled = 1; /* enable NMIs */
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}
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static INTERRUPT_GEN( shougi_vblank_nmi )
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}
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static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, shougi_state )
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        AM_RANGE(0x0000, 0x3fff) AM_ROM
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        AM_RANGE(0x4000, 0x43ff) AM_RAM         /* 2114 x 2 (0x400 x 4bit each) */
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        AM_RANGE(0x5000, 0x5000) AM_READ_PORT("P1")
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        AM_RANGE(0x5800, 0x5800) AM_READ_PORT("P2") AM_WRITE(shougi_watchdog_reset_w)   /* game won't boot if watchdog doesn't work */
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        AM_RANGE(0x6000, 0x6000) AM_DEVWRITE("aysnd", ay8910_address_w)
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        AM_RANGE(0x6800, 0x6800) AM_DEVWRITE("aysnd", ay8910_data_w)
 
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        AM_RANGE(0x6000, 0x6000) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
 
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        AM_RANGE(0x6800, 0x6800) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
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        AM_RANGE(0x7000, 0x73ff) AM_RAM AM_SHARE("share1") /* 2114 x 2 (0x400 x 4bit each) */
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        AM_RANGE(0x7800, 0x7bff) AM_RAM AM_SHARE("share2") /* 2114 x 2 (0x400 x 4bit each) */
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        AM_RANGE(0x8000, 0xffff) AM_RAM AM_BASE_MEMBER(shougi_state,m_videoram) /* 4116 x 16 (32K) */
 
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        AM_RANGE(0x8000, 0xffff) AM_RAM AM_SHARE("videoram")    /* 4116 x 16 (32K) */
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ADDRESS_MAP_END
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/* sub */
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static READ8_HANDLER ( dummy_r )
 
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READ8_MEMBER(shougi_state::dummy_r)
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{
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        shougi_state *state = space->machine().driver_data<shougi_state>();
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        state->m_r ^= 1;
 
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        m_r ^= 1;
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        if(state->m_r)
 
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        if(m_r)
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                return 0xff;
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        else
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                return 0;
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}
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static ADDRESS_MAP_START( readport_sub, AS_IO, 8 )
 
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static ADDRESS_MAP_START( readport_sub, AS_IO, 8, shougi_state )
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        ADDRESS_MAP_GLOBAL_MASK( 0x00ff )
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        AM_RANGE(0x00, 0x00) AM_READ(dummy_r)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8, shougi_state )
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        AM_RANGE(0x0000, 0x5fff) AM_ROM
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        AM_RANGE(0x6000, 0x63ff) AM_RAM AM_SHARE("share2") /* 2114 x 2 (0x400 x 4bit each) */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, shougi_state )
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        AM_RANGE(0x0000, 0x03ff) AM_RAM AM_SHARE("share1")
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ADDRESS_MAP_END
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