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Viewing changes to src/mame/drivers/champbas.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/champbas.c
115
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 *
116
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 *************************************/
117
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118
 
static WRITE8_HANDLER( champbas_watchdog_reset_w )
119
 
{
120
 
        champbas_state *state = space->machine().driver_data<champbas_state>();
121
 
        state->m_watchdog_count = 0;
122
 
}
123
 
 
124
 
static CUSTOM_INPUT( champbas_watchdog_bit2 )
125
 
{
126
 
        champbas_state *state = field.machine().driver_data<champbas_state>();
127
 
        return BIT(state->m_watchdog_count, 2);
128
 
}
129
 
 
130
 
 
131
 
static WRITE8_HANDLER( irq_enable_w )
132
 
{
133
 
        champbas_state *state = space->machine().driver_data<champbas_state>();
134
 
 
135
 
        state->m_irq_mask = data & 1;
136
 
 
137
 
        if (!state->m_irq_mask)
138
 
                device_set_input_line(state->m_maincpu, 0, CLEAR_LINE);
 
118
WRITE8_MEMBER(champbas_state::champbas_watchdog_reset_w)
 
119
{
 
120
        m_watchdog_count = 0;
 
121
}
 
122
 
 
123
CUSTOM_INPUT_MEMBER(champbas_state::champbas_watchdog_bit2)
 
124
{
 
125
        return BIT(m_watchdog_count, 2);
 
126
}
 
127
 
 
128
 
 
129
WRITE8_MEMBER(champbas_state::irq_enable_w)
 
130
{
 
131
 
 
132
        m_irq_mask = data & 1;
 
133
 
 
134
        if (!m_irq_mask)
 
135
                device_set_input_line(m_maincpu, 0, CLEAR_LINE);
139
136
}
140
137
 
141
138
static TIMER_CALLBACK( exctsccr_fm_callback )
157
154
 *
158
155
 *************************************/
159
156
 
160
 
static WRITE8_HANDLER( champbas_mcu_switch_w )
 
157
WRITE8_MEMBER(champbas_state::champbas_mcu_switch_w)
161
158
{
162
159
        // switch shared RAM between CPU and MCU bus
163
160
        // FIXME not implemented
164
161
}
165
162
 
166
 
static WRITE8_HANDLER( champbas_mcu_halt_w )
 
163
WRITE8_MEMBER(champbas_state::champbas_mcu_halt_w)
167
164
{
168
 
        champbas_state *state = space->machine().driver_data<champbas_state>();
169
165
 
170
166
        // MCU not present/not used in champbas
171
 
        if (state->m_mcu == NULL)
 
167
        if (m_mcu == NULL)
172
168
                return;
173
169
 
174
170
        data &= 1;
175
 
        device_set_input_line(state->m_mcu, INPUT_LINE_HALT, data ? ASSERT_LINE : CLEAR_LINE);
 
171
        device_set_input_line(m_mcu, INPUT_LINE_HALT, data ? ASSERT_LINE : CLEAR_LINE);
176
172
}
177
173
 
178
174
 
179
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/* champbja another protection */
180
 
static READ8_HANDLER( champbja_alt_protection_r )
 
176
READ8_MEMBER(champbas_state::champbja_alt_protection_r)
181
177
{
182
178
        UINT8 data = 0;
183
179
        /*
217
213
 *
218
214
 *************************************/
219
215
 
220
 
static ADDRESS_MAP_START( talbot_map, AS_PROGRAM, 8 )
 
216
static ADDRESS_MAP_START( talbot_map, AS_PROGRAM, 8, champbas_state )
221
217
        AM_RANGE(0x0000, 0x5fff) AM_ROM
222
218
        AM_RANGE(0x6000, 0x63ff) AM_RAM AM_SHARE("share1") /* MCU shared RAM */
223
 
        AM_RANGE(0x7000, 0x7001) AM_DEVWRITE("aysnd", ay8910_data_address_w)
224
 
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_BASE_MEMBER(champbas_state, m_bg_videoram)
 
219
        AM_RANGE(0x7000, 0x7001) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
 
220
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_SHARE("bg_videoram")
225
221
        AM_RANGE(0x8800, 0x8fef) AM_RAM
226
 
        AM_RANGE(0x8ff0, 0x8fff) AM_RAM AM_BASE_SIZE_MEMBER(champbas_state, m_spriteram, m_spriteram_size)
 
222
        AM_RANGE(0x8ff0, 0x8fff) AM_RAM AM_SHARE("spriteram")
227
223
 
228
224
        AM_RANGE(0xa000, 0xa000) AM_READ_PORT("P1")
229
225
        AM_RANGE(0xa040, 0xa040) AM_READ_PORT("P2")
239
235
        AM_RANGE(0xa006, 0xa006) AM_WRITE(champbas_mcu_halt_w)
240
236
        AM_RANGE(0xa007, 0xa007) AM_WRITE(champbas_mcu_switch_w)
241
237
 
242
 
        AM_RANGE(0xa060, 0xa06f) AM_WRITEONLY AM_BASE_MEMBER(champbas_state, m_spriteram_2)
 
238
        AM_RANGE(0xa060, 0xa06f) AM_WRITEONLY AM_SHARE("spriteram_2")
243
239
        AM_RANGE(0xa0c0, 0xa0c0) AM_WRITE(champbas_watchdog_reset_w)
244
240
ADDRESS_MAP_END
245
241
 
246
242
 
247
 
static ADDRESS_MAP_START( champbas_main_map, AS_PROGRAM, 8 )
 
243
static ADDRESS_MAP_START( champbas_main_map, AS_PROGRAM, 8, champbas_state )
248
244
        AM_RANGE(0x0000, 0x5fff) AM_ROM
249
245
        AM_RANGE(0x6000, 0x63ff) AM_RAM AM_SHARE("share1")
250
 
        AM_RANGE(0x7000, 0x7001) AM_DEVWRITE("aysnd", ay8910_data_address_w)
 
246
        AM_RANGE(0x7000, 0x7001) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
251
247
        AM_RANGE(0x7800, 0x7fff) AM_ROM // champbb2 only
252
 
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_BASE_MEMBER(champbas_state, m_bg_videoram)
 
248
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_SHARE("bg_videoram")
253
249
        AM_RANGE(0x8800, 0x8fef) AM_RAM
254
 
        AM_RANGE(0x8ff0, 0x8fff) AM_RAM AM_BASE_SIZE_MEMBER(champbas_state, m_spriteram, m_spriteram_size)
 
250
        AM_RANGE(0x8ff0, 0x8fff) AM_RAM AM_SHARE("spriteram")
255
251
 
256
252
        AM_RANGE(0xa000, 0xa000) AM_READ_PORT("P1")
257
253
        AM_RANGE(0xa040, 0xa040) AM_READ_PORT("P2")
267
263
        AM_RANGE(0xa006, 0xa006) AM_WRITE(champbas_mcu_halt_w)  // MCU not present/not used in champbas
268
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        AM_RANGE(0xa007, 0xa007) AM_WRITE(champbas_mcu_switch_w)        // MCU not present/not used in champbas
269
265
 
270
 
        AM_RANGE(0xa060, 0xa06f) AM_RAM AM_BASE_MEMBER(champbas_state, m_spriteram_2)
271
 
        AM_RANGE(0xa080, 0xa080) AM_WRITE(soundlatch_w)
 
266
        AM_RANGE(0xa060, 0xa06f) AM_RAM AM_SHARE("spriteram_2")
 
267
        AM_RANGE(0xa080, 0xa080) AM_WRITE(soundlatch_byte_w)
272
268
/*  AM_RANGE(0xa0a0, 0xa0a0)    ???? */
273
269
        AM_RANGE(0xa0c0, 0xa0c0) AM_WRITE(champbas_watchdog_reset_w)
274
270
 
276
272
        AM_RANGE(0x6800, 0x68ff) AM_READ(champbja_alt_protection_r)
277
273
ADDRESS_MAP_END
278
274
 
279
 
static ADDRESS_MAP_START( exctsccrb_main_map, AS_PROGRAM, 8 )
 
275
static ADDRESS_MAP_START( exctsccrb_main_map, AS_PROGRAM, 8, champbas_state )
280
276
        AM_RANGE(0x0000, 0x5fff) AM_ROM
281
277
//  AM_RANGE(0x6000, 0x63ff) AM_RAM AM_SHARE("share1") // MCU not used (though it's present on the board)
282
 
        AM_RANGE(0x7000, 0x7001) AM_DEVWRITE("aysnd", ay8910_data_address_w)
 
278
        AM_RANGE(0x7000, 0x7001) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
283
279
//  AM_RANGE(0x7800, 0x7fff) AM_ROM // champbb2 only
284
 
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_BASE_MEMBER(champbas_state, m_bg_videoram)
285
 
        AM_RANGE(0x8800, 0x8fff) AM_RAM AM_BASE_MEMBER(champbas_state, m_spriteram_2) /* ??? */
 
280
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_SHARE("bg_videoram")
 
281
        AM_RANGE(0x8800, 0x8fff) AM_RAM AM_SHARE("spriteram_2") /* ??? */
286
282
 
287
283
        AM_RANGE(0xa000, 0xa000) AM_READ_PORT("P1")
288
284
        AM_RANGE(0xa040, 0xa040) AM_READ_PORT("P2")
296
292
        AM_RANGE(0xa006, 0xa006) AM_WRITENOP    /* MCU is not used, but some leftover code still writes here */
297
293
        AM_RANGE(0xa007, 0xa007) AM_WRITENOP    /* MCU is not used, but some leftover code still writes here */
298
294
 
299
 
        AM_RANGE(0xa040, 0xa06f) AM_WRITEONLY AM_BASE_MEMBER(champbas_state, m_spriteram) /* Sprite Pos */
300
 
        AM_RANGE(0xa080, 0xa080) AM_WRITE(soundlatch_w)
 
295
        AM_RANGE(0xa040, 0xa06f) AM_WRITEONLY AM_SHARE("spriteram") /* Sprite Pos */
 
296
        AM_RANGE(0xa080, 0xa080) AM_WRITE(soundlatch_byte_w)
301
297
        AM_RANGE(0xa0c0, 0xa0c0) AM_WRITE(watchdog_reset_w)
302
298
ADDRESS_MAP_END
303
299
 
304
300
 
305
 
static ADDRESS_MAP_START( exctsccr_main_map, AS_PROGRAM, 8 )
 
301
static ADDRESS_MAP_START( exctsccr_main_map, AS_PROGRAM, 8, champbas_state )
306
302
        AM_RANGE(0x0000, 0x5fff) AM_ROM
307
303
        AM_RANGE(0x6000, 0x63ff) AM_RAM AM_SHARE("share1")
308
304
        AM_RANGE(0x7c00, 0x7fff) AM_RAM
309
 
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_BASE_MEMBER(champbas_state, m_bg_videoram)
310
 
        AM_RANGE(0x8800, 0x8bff) AM_RAM AM_BASE_MEMBER(champbas_state, m_spriteram_2) /* ??? */
 
305
        AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(champbas_bg_videoram_w) AM_SHARE("bg_videoram")
 
306
        AM_RANGE(0x8800, 0x8bff) AM_RAM AM_SHARE("spriteram_2") /* ??? */
311
307
 
312
308
        AM_RANGE(0xa000, 0xa000) AM_READ_PORT("P1")
313
309
        AM_RANGE(0xa040, 0xa040) AM_READ_PORT("P2")
321
317
        AM_RANGE(0xa006, 0xa006) AM_WRITE(champbas_mcu_halt_w)
322
318
        AM_RANGE(0xa007, 0xa007) AM_WRITENOP /* This is also MCU control, but i dont need it */
323
319
 
324
 
        AM_RANGE(0xa040, 0xa06f) AM_WRITEONLY AM_BASE_MEMBER(champbas_state, m_spriteram) /* Sprite pos */
325
 
        AM_RANGE(0xa080, 0xa080) AM_WRITE(soundlatch_w)
 
320
        AM_RANGE(0xa040, 0xa06f) AM_WRITEONLY AM_SHARE("spriteram") /* Sprite pos */
 
321
        AM_RANGE(0xa080, 0xa080) AM_WRITE(soundlatch_byte_w)
326
322
        AM_RANGE(0xa0c0, 0xa0c0) AM_WRITE(watchdog_reset_w)
327
323
ADDRESS_MAP_END
328
324
 
329
325
 
330
326
 
331
 
static ADDRESS_MAP_START( champbas_sub_map, AS_PROGRAM, 8 )
 
327
static ADDRESS_MAP_START( champbas_sub_map, AS_PROGRAM, 8, champbas_state )
332
328
        AM_RANGE(0x0000, 0x5fff) AM_ROM
333
 
        AM_RANGE(0x6000, 0x7fff) AM_READ(soundlatch_r)
 
329
        AM_RANGE(0x6000, 0x7fff) AM_READ(soundlatch_byte_r)
334
330
        AM_RANGE(0x8000, 0x9fff) AM_WRITENOP    // 4-bit return code to main CPU (not used)
335
 
        AM_RANGE(0xa000, 0xbfff) AM_WRITE(soundlatch_clear_w)
336
 
        AM_RANGE(0xc000, 0xdfff) AM_DEVWRITE("dac", champbas_dac_w)
 
331
        AM_RANGE(0xa000, 0xbfff) AM_WRITE(soundlatch_clear_byte_w)
 
332
        AM_RANGE(0xc000, 0xdfff) AM_DEVWRITE_LEGACY("dac", champbas_dac_w)
337
333
        AM_RANGE(0xe000, 0xe3ff) AM_MIRROR(0x1c00) AM_RAM
338
334
ADDRESS_MAP_END
339
335
 
340
336
 
341
 
static ADDRESS_MAP_START( exctsccr_sub_map, AS_PROGRAM, 8 )
 
337
static ADDRESS_MAP_START( exctsccr_sub_map, AS_PROGRAM, 8, champbas_state )
342
338
        AM_RANGE(0x0000, 0x8fff) AM_ROM
343
339
        AM_RANGE(0xa000, 0xa7ff) AM_RAM
344
 
        AM_RANGE(0xc008, 0xc008) AM_DEVWRITE("dac1", champbas_dac_w)
345
 
        AM_RANGE(0xc009, 0xc009) AM_DEVWRITE("dac2", champbas_dac_w)
346
 
        AM_RANGE(0xc00c, 0xc00c) AM_WRITE(soundlatch_clear_w)
347
 
        AM_RANGE(0xc00d, 0xc00d) AM_READ(soundlatch_r)
 
340
        AM_RANGE(0xc008, 0xc008) AM_DEVWRITE_LEGACY("dac1", champbas_dac_w)
 
341
        AM_RANGE(0xc009, 0xc009) AM_DEVWRITE_LEGACY("dac2", champbas_dac_w)
 
342
        AM_RANGE(0xc00c, 0xc00c) AM_WRITE(soundlatch_clear_byte_w)
 
343
        AM_RANGE(0xc00d, 0xc00d) AM_READ(soundlatch_byte_r)
348
344
//  AM_RANGE(0xc00f, 0xc00f) AM_WRITENOP /* ??? */
349
345
ADDRESS_MAP_END
350
346
 
351
 
static ADDRESS_MAP_START( exctsccr_sound_io_map, AS_IO, 8 )
 
347
static ADDRESS_MAP_START( exctsccr_sound_io_map, AS_IO, 8, champbas_state )
352
348
        ADDRESS_MAP_GLOBAL_MASK( 0x00ff )
353
 
        AM_RANGE(0x82, 0x83) AM_DEVWRITE("ay1", ay8910_data_address_w)
354
 
        AM_RANGE(0x86, 0x87) AM_DEVWRITE("ay2", ay8910_data_address_w)
355
 
        AM_RANGE(0x8a, 0x8b) AM_DEVWRITE("ay3", ay8910_data_address_w)
356
 
        AM_RANGE(0x8e, 0x8f) AM_DEVWRITE("ay4", ay8910_data_address_w)
 
349
        AM_RANGE(0x82, 0x83) AM_DEVWRITE_LEGACY("ay1", ay8910_data_address_w)
 
350
        AM_RANGE(0x86, 0x87) AM_DEVWRITE_LEGACY("ay2", ay8910_data_address_w)
 
351
        AM_RANGE(0x8a, 0x8b) AM_DEVWRITE_LEGACY("ay3", ay8910_data_address_w)
 
352
        AM_RANGE(0x8e, 0x8f) AM_DEVWRITE_LEGACY("ay4", ay8910_data_address_w)
357
353
ADDRESS_MAP_END
358
354
 
359
355
 
360
 
static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8 )
 
356
static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, champbas_state )
361
357
        AM_RANGE(0x0000, 0x03ff) AM_RAM AM_SHARE("share1") /* main CPU shared RAM */
362
358
ADDRESS_MAP_END
363
359
 
405
401
        PORT_DIPNAME( 0x40, 0x00, DEF_STR( Cabinet ) )
406
402
        PORT_DIPSETTING(    0x00, DEF_STR( Upright ) )
407
403
        PORT_DIPSETTING(    0x40, DEF_STR( Cocktail ) )
408
 
        PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(champbas_watchdog_bit2, NULL)  // bit 2 of the watchdog counter
 
404
        PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, champbas_state,champbas_watchdog_bit2, NULL)       // bit 2 of the watchdog counter
409
405
 
410
406
        PORT_START("SYSTEM")
411
407
        PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
452
448
        PORT_DIPSETTING(    0x20, DEF_STR( Easy ) )
453
449
        PORT_DIPSETTING(    0x00, DEF_STR( Hard ))
454
450
        PORT_DIPUNKNOWN( 0x40, 0x00 )
455
 
        PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(champbas_watchdog_bit2, NULL)  // bit 2 of the watchdog counter
 
451
        PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, champbas_state,champbas_watchdog_bit2, NULL)       // bit 2 of the watchdog counter
456
452
INPUT_PORTS_END
457
453
 
458
454
static INPUT_PORTS_START( exctsccr )
478
474
        PORT_DIPSETTING(    0x00, "2 Min." )
479
475
        PORT_DIPSETTING(    0x60, "3 Min." )
480
476
        PORT_DIPSETTING(    0x40, "4 Min." )
481
 
        PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(champbas_watchdog_bit2, NULL)  // bit 2 of the watchdog counter
 
477
        PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, champbas_state,champbas_watchdog_bit2, NULL)       // bit 2 of the watchdog counter
482
478
INPUT_PORTS_END
483
479
 
484
480
 
1181
1177
static DRIVER_INIT(champbas)
1182
1178
{
1183
1179
        // chars and sprites are mixed in the same ROMs, so rearrange them for easier decoding
1184
 
        UINT8 *rom1 = machine.region("gfx1")->base();
1185
 
        UINT8 *rom2 = machine.region("gfx2")->base();
1186
 
        int len = machine.region("gfx1")->bytes();
 
1180
        UINT8 *rom1 = machine.root_device().memregion("gfx1")->base();
 
1181
        UINT8 *rom2 = machine.root_device().memregion("gfx2")->base();
 
1182
        int len = machine.root_device().memregion("gfx1")->bytes();
1187
1183
        int i;
1188
1184
 
1189
1185
        for (i = 0; i < len/2; ++i)
1198
1194
static DRIVER_INIT( exctsccr )
1199
1195
{
1200
1196
        // chars and sprites are mixed in the same ROMs, so rearrange them for easier decoding
1201
 
        UINT8 *rom1 = machine.region("gfx1")->base();
1202
 
        UINT8 *rom2 = machine.region("gfx2")->base();
 
1197
        UINT8 *rom1 = machine.root_device().memregion("gfx1")->base();
 
1198
        UINT8 *rom2 = machine.root_device().memregion("gfx2")->base();
1203
1199
        int i;
1204
1200
 
1205
1201
        // planes 0,1
1241
1237
 
1242
1238
GAME( 1983, exctsccr,   0,        exctsccr, exctsccr, exctsccr, ROT270, "Alpha Denshi Co.", "Exciting Soccer", GAME_SUPPORTS_SAVE )
1243
1239
GAME( 1983, exctsccra,  exctsccr, exctsccr, exctsccr, exctsccr, ROT270, "Alpha Denshi Co.", "Exciting Soccer (alternate music)", GAME_SUPPORTS_SAVE )
1244
 
GAME( 1983, exctsccrj,  exctsccr, exctsccr, exctsccr, exctsccr, ROT270, "Alpha Denshi Co.", "Exciting Soccer (Japan)", GAME_SUPPORTS_SAVE )
 
1240
GAME( 1983, exctsccrj,  exctsccr, exctsccr, exctsccr, exctsccr, ROT270, "Alpha Denshi Co.", "Exciting Soccer (Japan set 1)", GAME_SUPPORTS_SAVE )
1245
1241
GAME( 1983, exctsccrj2, exctsccr, exctsccr, exctsccr, exctsccr, ROT270, "Alpha Denshi Co.", "Exciting Soccer (Japan set 2)", GAME_SUPPORTS_SAVE )
1246
1242
GAME( 1983, exctsccrb,  exctsccr, exctsccrb,exctsccr, exctsccr, ROT270, "bootleg",          "Exciting Soccer (bootleg)", GAME_SUPPORTS_SAVE )
1247
1243
GAME( 1984, exctscc2,   0,        exctsccr, exctsccr, exctsccr, ROT270, "Alpha Denshi Co.", "Exciting Soccer II", GAME_SUPPORTS_SAVE )