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Viewing changes to board/Marvell/include/mv_gen_reg.h

  • Committer: Bazaar Package Importer
  • Author(s): Oliver Grawert
  • Date: 2010-03-22 15:06:23 UTC
  • Revision ID: james.westby@ubuntu.com-20100322150623-i21g8rgiyl5dohag
Tags: upstream-2010.3git20100315
Import upstream version 2010.3git20100315

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board/Marvell/include/mv_gen_reg.h
 
1
/* mv_gen_reg.h - Internal registers definition file */
 
2
/* Copyright - Galileo technology. */
 
3
 
 
4
 
 
5
/*******************************************************************************
 
6
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
 
7
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
 
8
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
 
9
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
 
10
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
 
11
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
 
12
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
 
13
*                                                                              *
 
14
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
 
15
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
 
16
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
 
17
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
 
18
********************************************************************************
 
19
* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file.
 
20
*
 
21
* DESCRIPTION:
 
22
*       None.
 
23
*
 
24
* DEPENDENCIES:
 
25
*       None.
 
26
*
 
27
*******************************************************************************/
 
28
 
 
29
#ifndef __INCmv_gen_regh
 
30
#define __INCmv_gen_regh
 
31
 
 
32
 
 
33
/* Supported by the Atlantis */
 
34
#define INCLUDE_PCI_1
 
35
#define INCLUDE_PCI_0_ARBITER
 
36
#define INCLUDE_PCI_1_ARBITER
 
37
#define INCLUDE_SNOOP_SUPPORT
 
38
#define INCLUDE_P2P
 
39
#define INCLUDE_ETH_PORT_2
 
40
#define INCLUDE_CPU_MAPPING
 
41
#define INCLUDE_MPSC
 
42
 
 
43
/* Not supported features */
 
44
#undef  INCLUDE_CNTMR_4_7
 
45
#undef  INCLUDE_DMA_4_7
 
46
 
 
47
 
 
48
/****************************************/
 
49
/* Processor Address Space                              */
 
50
/****************************************/
 
51
/* DDR SDRAM BAR and size registers */
 
52
 
 
53
/* Sdram's BAR'S */
 
54
#define SCS_0_LOW_DECODE_ADDRESS                        0x008
 
55
#define SCS_0_HIGH_DECODE_ADDRESS                       0x010
 
56
#define SCS_1_LOW_DECODE_ADDRESS                        0x208
 
57
#define SCS_1_HIGH_DECODE_ADDRESS                       0x210
 
58
#define SCS_2_LOW_DECODE_ADDRESS                        0x018
 
59
#define SCS_2_HIGH_DECODE_ADDRESS                       0x020
 
60
#define SCS_3_LOW_DECODE_ADDRESS                        0x218
 
61
#define SCS_3_HIGH_DECODE_ADDRESS                       0x220
 
62
 
 
63
/* Make it fit the MV64360 and MV64460 Lowlevel driver */
 
64
#define CS_0_BASE_ADDR                  SCS_0_LOW_DECODE_ADDRESS
 
65
#define CS_0_SIZE                       SCS_0_HIGH_DECODE_ADDRESS
 
66
#define CS_1_BASE_ADDR          SCS_1_LOW_DECODE_ADDRESS
 
67
#define CS_1_SIZE                       SCS_1_HIGH_DECODE_ADDRESS
 
68
#define CS_2_BASE_ADDR          SCS_2_LOW_DECODE_ADDRESS
 
69
#define CS_2_SIZE                       SCS_2_HIGH_DECODE_ADDRESS
 
70
#define CS_3_BASE_ADDR          SCS_3_LOW_DECODE_ADDRESS
 
71
#define CS_3_SIZE                       SCS_3_HIGH_DECODE_ADDRESS
 
72
 
 
73
/* Devices BAR'S */
 
74
#define CS_0_LOW_DECODE_ADDRESS                 0x028
 
75
#define CS_0_HIGH_DECODE_ADDRESS                        0x030
 
76
#define CS_1_LOW_DECODE_ADDRESS                 0x228
 
77
#define CS_1_HIGH_DECODE_ADDRESS                        0x230
 
78
#define CS_2_LOW_DECODE_ADDRESS                 0x248
 
79
#define CS_2_HIGH_DECODE_ADDRESS                        0x250
 
80
#define CS_3_LOW_DECODE_ADDRESS                 0x038
 
81
#define CS_3_HIGH_DECODE_ADDRESS                        0x040
 
82
#define BOOTCS_LOW_DECODE_ADDRESS                       0x238
 
83
#define BOOTCS_HIGH_DECODE_ADDRESS                      0x240
 
84
 
 
85
/* Make it fit the MV64360 and MV64460 Lowlevel driver */
 
86
/* Devices BAR and size registers */
 
87
 
 
88
#define DEV_CS0_BASE_ADDR       CS_0_LOW_DECODE_ADDRESS
 
89
#define DEV_CS0_SIZE                    CS_0_HIGH_DECODE_ADDRESS
 
90
#define DEV_CS1_BASE_ADDR       CS_1_LOW_DECODE_ADDRESS
 
91
#define DEV_CS1_SIZE            CS_1_HIGH_DECODE_ADDRESS
 
92
#define DEV_CS2_BASE_ADDR       CS_2_LOW_DECODE_ADDRESS
 
93
#define DEV_CS2_SIZE                    CS_2_HIGH_DECODE_ADDRESS
 
94
#define DEV_CS3_BASE_ADDR               CS_3_LOW_DECODE_ADDRESS
 
95
#define DEV_CS3_SIZE            CS_3_HIGH_DECODE_ADDRESS
 
96
#define BOOTCS_BASE_ADDR        BOOTCS_LOW_DECODE_ADDRESS
 
97
#define BOOTCS_SIZE             BOOTCS_HIGH_DECODE_ADDRESS
 
98
 
 
99
/* PCI 0 BAR and size registers  old names of evb64260*/
 
100
 
 
101
#define PCI_0I_O_LOW_DECODE_ADDRESS                     0x048
 
102
#define PCI_0I_O_HIGH_DECODE_ADDRESS                    0x050
 
103
#define PCI_0MEMORY0_LOW_DECODE_ADDRESS         0x058
 
104
#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS                0x060
 
105
#define PCI_0MEMORY1_LOW_DECODE_ADDRESS         0x080
 
106
#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS                0x088
 
107
#define PCI_0MEMORY2_LOW_DECODE_ADDRESS         0x258
 
108
#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS                0x260
 
109
#define PCI_0MEMORY3_LOW_DECODE_ADDRESS         0x280
 
110
#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS                0x288
 
111
 
 
112
/* Make it fit the MV64360 and MV64460 Lowlevel driver */
 
113
#define PCI_0_IO_BASE_ADDR                                              0x048
 
114
#define PCI_0_IO_SIZE                                                   0x050
 
115
#define PCI_0_MEMORY0_BASE_ADDR                                 0x058
 
116
#define PCI_0_MEMORY0_SIZE                                              0x060
 
117
#define PCI_0_MEMORY1_BASE_ADDR                                 0x080
 
118
#define PCI_0_MEMORY1_SIZE                                              0x088
 
119
#define PCI_0_MEMORY2_BASE_ADDR                                 0x258
 
120
#define PCI_0_MEMORY2_SIZE                                              0x260
 
121
#define PCI_0_MEMORY3_BASE_ADDR                                 0x280
 
122
#define PCI_0_MEMORY3_SIZE                                              0x288
 
123
 
 
124
/* PCI 1 BAR and size registers  old names of evb64260*/
 
125
#define PCI_1I_O_LOW_DECODE_ADDRESS                     0x090
 
126
#define PCI_1I_O_HIGH_DECODE_ADDRESS                    0x098
 
127
#define PCI_1MEMORY0_LOW_DECODE_ADDRESS         0x0a0
 
128
#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS                0x0a8
 
129
#define PCI_1MEMORY1_LOW_DECODE_ADDRESS         0x0b0
 
130
#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS                0x0b8
 
131
#define PCI_1MEMORY2_LOW_DECODE_ADDRESS         0x2a0
 
132
#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS                0x2a8
 
133
#define PCI_1MEMORY3_LOW_DECODE_ADDRESS         0x2b0
 
134
#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS                0x2b8
 
135
 
 
136
/* Make it fit the MV64360 and MV64460 Lowlevel driver */
 
137
#define PCI_1_IO_BASE_ADDR                                              0x090
 
138
#define PCI_1_IO_SIZE                                                   0x098
 
139
#define PCI_1_MEMORY0_BASE_ADDR                                 0x0a0
 
140
#define PCI_1_MEMORY0_SIZE                                              0x0a8
 
141
#define PCI_1_MEMORY1_BASE_ADDR                                 0x0b0
 
142
#define PCI_1_MEMORY1_SIZE                                              0x0b8
 
143
#define PCI_1_MEMORY2_BASE_ADDR                                 0x2a0
 
144
#define PCI_1_MEMORY2_SIZE                                              0x2a8
 
145
#define PCI_1_MEMORY3_BASE_ADDR                                 0x2b0
 
146
#define PCI_1_MEMORY3_SIZE                                              0x2b8
 
147
 
 
148
/* internal registers space base address */
 
149
#define INTERNAL_SPACE_DECODE                           0x068
 
150
#define INTERNAL_SPACE_BASE_ADDR                                INTERNAL_SPACE_DECODE
 
151
 
 
152
/* SRAM base address */
 
153
#define INTEGRATED_SRAM_BASE_ADDR                               0x268
 
154
 
 
155
/* Enables the CS , DEV_CS , PCI 0 and PCI 1
 
156
   windows above */
 
157
#define BASE_ADDR_ENABLE                                                0x278
 
158
 
 
159
 
 
160
#define CPU_0_LOW_DECODE_ADDRESS                                0x290
 
161
#define CPU_0_HIGH_DECODE_ADDRESS                               0x298
 
162
#define CPU_1_LOW_DECODE_ADDRESS                                0x2c0
 
163
#define CPU_1_HIGH_DECODE_ADDRESS                               0x2c8
 
164
 
 
165
/****************************************/
 
166
/* PCI remap registers                  */
 
167
/****************************************/
 
168
/*****************************************************************************************/
 
169
      /* PCI 0 */
 
170
/* old fashion evb 64260 */
 
171
#define PCI_0I_O_ADDRESS_REMAP                          0x0f0
 
172
#define PCI_0MEMORY0_ADDRESS_REMAP                      0x0f8
 
173
#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP         0x320
 
174
#define PCI_0MEMORY1_ADDRESS_REMAP                      0x100
 
175
#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP         0x328
 
176
#define PCI_0MEMORY2_ADDRESS_REMAP                      0x2f8
 
177
#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP         0x330
 
178
#define PCI_0MEMORY3_ADDRESS_REMAP                      0x300
 
179
#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP         0x338
 
180
 
 
181
#define PCI_0_IO_ADDR_REMAP                                             PCI_0I_O_ADDRESS_REMAP
 
182
#define PCI_0_MEMORY0_LOW_ADDR_REMAP                            PCI_0MEMORY0_ADDRESS_REMAP
 
183
#define PCI_0_MEMORY0_HIGH_ADDR_REMAP                           PCI_0MEMORY0_HIGH_ADDRESS_REMAP
 
184
#define PCI_0_MEMORY1_LOW_ADDR_REMAP                            PCI_0MEMORY1_ADDRESS_REMAP
 
185
#define PCI_0_MEMORY1_HIGH_ADDR_REMAP                           PCI_0MEMORY1_HIGH_ADDRESS_REMAP
 
186
#define PCI_0_MEMORY2_LOW_ADDR_REMAP                            PCI_0MEMORY2_ADDRESS_REMAP
 
187
#define PCI_0_MEMORY2_HIGH_ADDR_REMAP                           PCI_0MEMORY2_HIGH_ADDRESS_REMAP
 
188
#define PCI_0_MEMORY3_LOW_ADDR_REMAP                            PCI_0MEMORY3_ADDRESS_REMAP
 
189
#define PCI_0_MEMORY3_HIGH_ADDR_REMAP                           PCI_0MEMORY3_HIGH_ADDRESS_REMAP
 
190
 
 
191
       /* PCI 1 */
 
192
/* old fashion evb 64260 */
 
193
#define PCI_1I_O_ADDRESS_REMAP                          0x108
 
194
#define PCI_1MEMORY0_ADDRESS_REMAP                      0x110
 
195
#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP         0x340
 
196
#define PCI_1MEMORY1_ADDRESS_REMAP                      0x118
 
197
#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP         0x348
 
198
#define PCI_1MEMORY2_ADDRESS_REMAP                      0x310
 
199
#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP         0x350
 
200
#define PCI_1MEMORY3_ADDRESS_REMAP                      0x318
 
201
#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP         0x358
 
202
 
 
203
#define PCI_1_IO_ADDR_REMAP                                             PCI_1I_O_ADDRESS_REMAP
 
204
#define PCI_1_MEMORY0_LOW_ADDR_REMAP                            PCI_1MEMORY0_ADDRESS_REMAP
 
205
#define PCI_1_MEMORY0_HIGH_ADDR_REMAP                           PCI_1MEMORY0_HIGH_ADDRESS_REMAP
 
206
#define PCI_1_MEMORY1_LOW_ADDR_REMAP                            PCI_1MEMORY1_ADDRESS_REMAP
 
207
#define PCI_1_MEMORY1_HIGH_ADDR_REMAP                           PCI_1MEMORY1_HIGH_ADDRESS_REMAP
 
208
#define PCI_1_MEMORY2_LOW_ADDR_REMAP                            PCI_1MEMORY2_ADDRESS_REMAP
 
209
#define PCI_1_MEMORY2_HIGH_ADDR_REMAP                           PCI_1MEMORY2_HIGH_ADDRESS_REMAP
 
210
#define PCI_1_MEMORY3_LOW_ADDR_REMAP                            PCI_1MEMORY3_ADDRESS_REMAP
 
211
#define PCI_1_MEMORY3_HIGH_ADDR_REMAP                           PCI_1MEMORY3_HIGH_ADDRESS_REMAP
 
212
 
 
213
/* old fashion evb 64260 */
 
214
#define CPU_PCI_0_HEADERS_RETARGET_CONTROL                      0x3b0
 
215
#define CPU_PCI_0_HEADERS_RETARGET_BASE                         0x3b8
 
216
#define CPU_PCI_1_HEADERS_RETARGET_CONTROL                      0x3c0
 
217
#define CPU_PCI_1_HEADERS_RETARGET_BASE                         0x3c8
 
218
#define CPU_GE_HEADERS_RETARGET_CONTROL                         0x3d0
 
219
#define CPU_GE_HEADERS_RETARGET_BASE                            0x3d8
 
220
 
 
221
/* MV64360 and MV64460 no changes needed*/
 
222
/*****************************************************************************************/
 
223
 
 
224
/****************************************/
 
225
/*         CPU Control Registers        */
 
226
/****************************************/
 
227
/* CPU MASTER CONTROL REGISTER */
 
228
#define CPU_CONFIGURATION                               0x000
 
229
#define CPU_MASTER_CONTROL                              0x160
 
230
 
 
231
#define CPU_CONFIG                                                      0x000
 
232
#define CPU_MODE                                                        0x120
 
233
#define CPU_MASTER_CONTROL                                              0x160
 
234
/* new in MV64360 and MV64460 */
 
235
#define CPU_CROSS_BAR_CONTROL_LOW                               0x150
 
236
#define CPU_CROSS_BAR_CONTROL_HIGH                              0x158
 
237
#define CPU_CROSS_BAR_TIMEOUT                                   0x168
 
238
 
 
239
/****************************************/
 
240
/* SMP RegisterS                        */
 
241
/****************************************/
 
242
 
 
243
#define SMP_WHO_AM_I                                                    0x200
 
244
#define SMP_CPU0_DOORBELL                                               0x214
 
245
#define SMP_CPU0_DOORBELL_CLEAR                                 0x21C
 
246
#define SMP_CPU1_DOORBELL                                               0x224
 
247
#define SMP_CPU1_DOORBELL_CLEAR                                 0x22C
 
248
#define SMP_CPU0_DOORBELL_MASK                                  0x234
 
249
#define SMP_CPU1_DOORBELL_MASK                                  0x23C
 
250
#define SMP_SEMAPHOR0                                                   0x244
 
251
#define SMP_SEMAPHOR1                                                   0x24c
 
252
#define SMP_SEMAPHOR2                                                   0x254
 
253
#define SMP_SEMAPHOR3                                                   0x25c
 
254
#define SMP_SEMAPHOR4                                                   0x264
 
255
#define SMP_SEMAPHOR5                                                   0x26c
 
256
#define SMP_SEMAPHOR6                                                   0x274
 
257
#define SMP_SEMAPHOR7                                                   0x27c
 
258
 
 
259
 
 
260
/****************************************/
 
261
/* CPU Sync Barrier                             */
 
262
/****************************************/
 
263
#define CPU_0_SYNC_BARRIER_TRIGGER                              0x0c0
 
264
#define CPU_0_SYNC_BARRIER_VIRTUAL                              0x0c8
 
265
#define CPU_1_SYNC_BARRIER_TRIGGER                              0x0d0
 
266
#define CPU_1_SYNC_BARRIER_VIRTUAL                              0x0d8
 
267
 
 
268
 
 
269
/****************************************/
 
270
/* CPU Access Protect                   */
 
271
/****************************************/
 
272
 
 
273
#define CPU_LOW_PROTECT_ADDRESS_0                           0x180
 
274
#define CPU_HIGH_PROTECT_ADDRESS_0                          0x188
 
275
#define CPU_LOW_PROTECT_ADDRESS_1                           0x190
 
276
#define CPU_HIGH_PROTECT_ADDRESS_1                          0x198
 
277
#define CPU_LOW_PROTECT_ADDRESS_2                           0x1a0
 
278
#define CPU_HIGH_PROTECT_ADDRESS_2                          0x1a8
 
279
#define CPU_LOW_PROTECT_ADDRESS_3                           0x1b0
 
280
#define CPU_HIGH_PROTECT_ADDRESS_3                          0x1b8
 
281
/*#define CPU_LOW_PROTECT_ADDRESS_4                           0x1c0
 
282
#define CPU_HIGH_PROTECT_ADDRESS_4                          0x1c8
 
283
#define CPU_LOW_PROTECT_ADDRESS_5                           0x1d0
 
284
#define CPU_HIGH_PROTECT_ADDRESS_5                          0x1d8
 
285
#define CPU_LOW_PROTECT_ADDRESS_6                           0x1e0
 
286
#define CPU_HIGH_PROTECT_ADDRESS_6                          0x1e8
 
287
#define CPU_LOW_PROTECT_ADDRESS_7                           0x1f0
 
288
#define CPU_HIGH_PROTECT_ADDRESS_7                          0x1f8
 
289
*/
 
290
 
 
291
#define CPU_PROTECT_WINDOW_0_BASE_ADDR               CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */
 
292
#define CPU_PROTECT_WINDOW_0_SIZE                           CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */
 
293
#define CPU_PROTECT_WINDOW_1_BASE_ADDR               CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */
 
294
#define CPU_PROTECT_WINDOW_1_SIZE                           CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */
 
295
#define CPU_PROTECT_WINDOW_2_BASE_ADDR               CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */
 
296
#define CPU_PROTECT_WINDOW_2_SIZE                           CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */
 
297
#define CPU_PROTECT_WINDOW_3_BASE_ADDR               CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */
 
298
#define CPU_PROTECT_WINDOW_3_SIZE                           CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */
 
299
 
 
300
 
 
301
/****************************************/
 
302
/*          Snoop Control                       */
 
303
/****************************************/
 
304
 
 
305
/*#define SNOOP_BASE_ADDRESS_0                                0x380
 
306
#define SNOOP_TOP_ADDRESS_0                                 0x388
 
307
#define SNOOP_BASE_ADDRESS_1                                0x390
 
308
#define SNOOP_TOP_ADDRESS_1                                 0x398
 
309
#define SNOOP_BASE_ADDRESS_2                                0x3a0
 
310
#define SNOOP_TOP_ADDRESS_2                                 0x3a8
 
311
#define SNOOP_BASE_ADDRESS_3                                0x3b0
 
312
#define SNOOP_TOP_ADDRESS_3                                 0x3b8
 
313
*/
 
314
 
 
315
/****************************************/
 
316
/*  Integrated SRAM Registers           */
 
317
/****************************************/
 
318
 
 
319
#define SRAM_CONFIG                                             0x380
 
320
#define SRAM_TEST_MODE                                          0x3F4
 
321
#define SRAM_ERROR_CAUSE                                        0x388
 
322
#define SRAM_ERROR_ADDR                                         0x390
 
323
#define SRAM_ERROR_ADDR_HIGH                                    0x3F8
 
324
#define SRAM_ERROR_DATA_LOW                                     0x398
 
325
#define SRAM_ERROR_DATA_HIGH                                    0x3a0
 
326
#define SRAM_ERROR_DATA_PARITY                                  0x3a8
 
327
 
 
328
/****************************************/
 
329
/*          CPU Error Report                    */
 
330
/****************************************/
 
331
 
 
332
#define CPU_ERROR_ADDRESS_LOW           0x070
 
333
#define CPU_ERROR_ADDRESS_HIGH          0x078
 
334
#define CPU_ERROR_DATA_LOW                                      0x128
 
335
#define CPU_ERROR_DATA_HIGH                                     0x130
 
336
#define CPU_ERROR_PARITY                                        0x138
 
337
#define CPU_ERROR_CAUSE                                         0x140
 
338
#define CPU_ERROR_MASK                                          0x148
 
339
 
 
340
#define CPU_ERROR_ADDR_LOW                                      CPU_ERROR_ADDRESS_LOW  /* 0x0701 */
 
341
#define CPU_ERROR_ADDR_HIGH                                     CPU_ERROR_ADDRESS_HIGH  /* 0x0781 */
 
342
 
 
343
/****************************************/
 
344
/*          Pslave Debug                        */
 
345
/*      CPU Interface Debug Registers   */
 
346
/****************************************/
 
347
 
 
348
#define X_0_ADDRESS                                             0x360
 
349
#define X_0_COMMAND_ID                                          0x368
 
350
#define X_1_ADDRESS                                             0x370
 
351
#define X_1_COMMAND_ID                                          0x378
 
352
 /*#define WRITE_DATA_LOW                                       0x3c01 */
 
353
 /*#define WRITE_DATA_HIGH                                      0x3c81 */
 
354
 /*#define WRITE_BYTE_ENABLE                                    0x3e01 */
 
355
 /*#define READ_DATA_LOW                                        0x3d01 */
 
356
 /*#define READ_DATA_HIGH                                       0x3d81 */
 
357
 /*#define READ_ID                                              0x3e81 */
 
358
 
 
359
#define PUNIT_SLAVE_DEBUG_LOW                                   X_0_ADDRESS  /* 0x3601 */
 
360
#define PUNIT_SLAVE_DEBUG_HIGH                                  X_0_COMMAND_ID  /* 0x3681 */
 
361
#define PUNIT_MASTER_DEBUG_LOW                                  X_1_ADDRESS  /* 0x3701 */
 
362
#define PUNIT_MASTER_DEBUG_HIGH                            X_1_COMMAND_ID  /* 0x3781 */
 
363
#define PUNIT_MMASK                                             0x3e4
 
364
 
 
365
 
 
366
/****************************************/
 
367
/* SDRAM and Device Address Space               */
 
368
/****************************************/
 
369
 
 
370
/****************************************/
 
371
/* SDRAM Configuration                  */
 
372
/****************************************/
 
373
#define SDRAM_CONFIG                                            0x1400  /* MV64260 0x448 some changes*/
 
374
#define D_UNIT_CONTROL_LOW                                      0x1404  /* NEW in MV64360 and MV64460 */
 
375
#define D_UNIT_CONTROL_HIGH                                     0x1424  /* NEW in MV64360 and MV64460 */
 
376
#define SDRAM_TIMING_CONTROL_LOW                        0x1408  /* MV64260 0x4b4 new SDRAM TIMING REGISTER */
 
377
#define SDRAM_TIMING_CONTROL_HIGH                       0x140c  /* MV64260 0x4b4 new SDRAM TIMING REGISTER */
 
378
#define SDRAM_ADDR_CONTROL                                  0x1410      /* MV64260 0x47c some changes*/
 
379
#define SDRAM_OPEN_PAGES_CONTROL                        0x1414  /* NEW in MV64360 and MV64460 */
 
380
#define SDRAM_OPERATION                                         0x1418  /* MV64260 0x474 some changes*/
 
381
#define SDRAM_MODE                                              0x141c  /* NEW in MV64360 and MV64460 */
 
382
#define EXTENDED_DRAM_MODE                                      0x1420  /* NEW in MV64360 and MV64460 */
 
383
#define SDRAM_CROSS_BAR_CONTROL_LOW                     0x1430  /* MV64260 0x4a8 NO changes*/
 
384
#define SDRAM_CROSS_BAR_CONTROL_HIGH                    0x1434  /* MV64260 0x4ac NO changes*/
 
385
#define SDRAM_CROSS_BAR_TIMEOUT                         0x1438  /* MV64260 0x4b0 NO changes*/
 
386
#define SDRAM_ADDR_CTRL_PADS_CALIBRATION        0x14c0  /* what is this ??? */
 
387
#define SDRAM_DATA_PADS_CALIBRATION                     0x14c4  /* what is this ??? */
 
388
/****************************************/
 
389
/* SDRAM Configuration MV64260                  */
 
390
/****************************************/
 
391
 /*#define SDRAM_CONFIGURATION                  0x4481 */
 
392
 /*#define SDRAM_OPERATION_MODE                 0x4741 */
 
393
 /*#define SDRAM_ADDRESS_DECODE         0x47c1 */
 
394
 /*#define SDRAM_UMA_CONTROL                    0x4a4   eliminated in MV64360 and MV64460 */
 
395
 /*#define SDRAM_CROSS_BAR_CONTROL_LOW  0x4a81 */
 
396
 /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */
 
397
 /*#define SDRAM_CROSS_BAR_TIMEOUT              0x4b01 */
 
398
 /*#define SDRAM_TIMING                         0x4b41 */
 
399
 
 
400
 
 
401
/****************************************/
 
402
/* SDRAM Error Report                   */
 
403
/****************************************/
 
404
#define SDRAM_ERROR_DATA_LOW                            0x1444  /* MV64260 0x484 NO changes*/
 
405
#define SDRAM_ERROR_DATA_HIGH                                   0x1440  /* MV64260 0x480 NO changes*/
 
406
#define SDRAM_ERROR_ADDR                                        0x1450  /* MV64260 0x490 NO changes*/
 
407
#define SDRAM_RECEIVED_ECC                                      0x1448  /* MV64260 0x488 NO changes*/
 
408
#define SDRAM_CALCULATED_ECC                                    0x144c  /* MV64260 0x48c NO changes*/
 
409
#define SDRAM_ECC_CONTROL                                       0x1454  /* MV64260 0x494 NO changes*/
 
410
#define SDRAM_ECC_ERROR_COUNTER                         0x1458  /* MV64260 0x498 NO changes*/
 
411
#define SDRAM_MMASK                                     0x1B40  /* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/
 
412
/****************************************/
 
413
/* SDRAM Error Report MV64260                   */
 
414
/****************************************/
 
415
 /*#define SDRAM_ERROR_DATA_LOW                                 0x4841 */
 
416
 /*#define SDRAM_ERROR_DATA_HIGH                                0x4801 */
 
417
 /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS               0x4901 */
 
418
 /*#define SDRAM_RECEIVED_ECC                                  0x4881 */
 
419
 /*#define SDRAM_CALCULATED_ECC                                 0x48c1 */
 
420
 /*#define SDRAM_ECC_CONTROL                                    0x4941 */
 
421
 /*#define SDRAM_ECC_ERROR_COUNTER                      0x4981 */
 
422
 
 
423
/******************************************/
 
424
/*  Controlled Delay Line (CDL) Registers */
 
425
/******************************************/
 
426
#define DFCDL_CONFIG0                                           0x1480
 
427
#define DFCDL_CONFIG1                                           0x1484
 
428
#define DLL_WRITE                                               0x1488
 
429
#define DLL_READ                                                0x148c
 
430
#define SRAM_ADDR                                               0x1490
 
431
#define SRAM_DATA0                                              0x1494
 
432
#define SRAM_DATA1                                              0x1498
 
433
#define SRAM_DATA2                                              0x149c
 
434
#define DFCL_PROBE                                              0x14a0
 
435
 
 
436
 
 
437
/****************************************/
 
438
/* SDRAM Parameters only in MV64260                     */
 
439
/****************************************/
 
440
 
 
441
 /*#define SDRAM_BANK0PARAMETERS                                0x44C   eliminated in MV64360 and MV64460 */
 
442
 /*#define SDRAM_BANK1PARAMETERS                                0x450   eliminated in MV64360 and MV64460 */
 
443
 /*#define SDRAM_BANK2PARAMETERS                                0x454   eliminated in MV64360 and MV64460 */
 
444
 /*#define SDRAM_BANK3PARAMETERS                                0x458   eliminated in MV64360 and MV64460 */
 
445
 
 
446
/******************************************/
 
447
/*   Debug Registers                      */
 
448
/******************************************/
 
449
 
 
450
#define DUNIT_DEBUG_LOW                                         0x1460
 
451
#define DUNIT_DEBUG_HIGH                                        0x1464
 
452
#define DUNIT_MMASK                                             0x1b40
 
453
 
 
454
/****************************************/
 
455
/* SDunit Debug (for internal use)      */
 
456
/****************************************/
 
457
 
 
458
#define X0_ADDRESS                                          0x500
 
459
#define X0_COMMAND_AND_ID                                   0x504
 
460
#define X0_WRITE_DATA_LOW                                   0x508
 
461
#define X0_WRITE_DATA_HIGH                                  0x50c
 
462
#define X0_WRITE_BYTE_ENABLE                                0x518
 
463
#define X0_READ_DATA_LOW                                    0x510
 
464
#define X0_READ_DATA_HIGH                                   0x514
 
465
#define X0_READ_ID                                          0x51c
 
466
#define X1_ADDRESS                                          0x520
 
467
#define X1_COMMAND_AND_ID                                   0x524
 
468
#define X1_WRITE_DATA_LOW                                   0x528
 
469
#define X1_WRITE_DATA_HIGH                                  0x52c
 
470
#define X1_WRITE_BYTE_ENABLE                                0x538
 
471
#define X1_READ_DATA_LOW                                    0x530
 
472
#define X1_READ_DATA_HIGH                                   0x534
 
473
#define X1_READ_ID                                          0x53c
 
474
#define X0_SNOOP_ADDRESS                                    0x540
 
475
#define X0_SNOOP_COMMAND                                    0x544
 
476
#define X1_SNOOP_ADDRESS                                    0x548
 
477
#define X1_SNOOP_COMMAND                                    0x54c
 
478
 
 
479
/****************************************/
 
480
/* Device Parameters                                    */
 
481
/****************************************/
 
482
 
 
483
#define DEVICE_BANK0PARAMETERS                          0x45c
 
484
#define DEVICE_BANK1PARAMETERS                          0x460
 
485
#define DEVICE_BANK2PARAMETERS                          0x464
 
486
#define DEVICE_BANK3PARAMETERS                          0x468
 
487
#define DEVICE_BOOT_BANK_PARAMETERS                     0x46c
 
488
#define DEVICE_CONTROL                                                  0x4c0
 
489
#define DEVICE_CROSS_BAR_CONTROL_LOW                            0x4c8
 
490
#define DEVICE_CROSS_BAR_CONTROL_HIGH                           0x4cc
 
491
#define DEVICE_CROSS_BAR_TIMEOUT                                0x4c4
 
492
 
 
493
/****************************************/
 
494
/* Device Parameters                                    */
 
495
/****************************************/
 
496
 
 
497
#define DEVICE_BANK0_PARAMETERS                 DEVICE_BANK0PARAMETERS  /* 0x45c1 */
 
498
#define DEVICE_BANK1_PARAMETERS                 DEVICE_BANK1PARAMETERS  /* 0x4601 */
 
499
#define DEVICE_BANK2_PARAMETERS                 DEVICE_BANK2PARAMETERS  /* 0x4641 */
 
500
#define DEVICE_BANK3_PARAMETERS                 DEVICE_BANK3PARAMETERS  /* 0x4681 */
 
501
/*#define DEVICE_BOOT_BANK_PARAMETERS                    0x46c1 */
 
502
#define DEVICE_INTERFACE_CONTROL                                DEVICE_CONTROL  /* 0x4c01 */
 
503
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW          DEVICE_CROSS_BAR_CONTROL_LOW  /* 0x4c81 */
 
504
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH         DEVICE_CROSS_BAR_CONTROL_HIGH  /* 0x4cc1 */
 
505
#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT                      DEVICE_CROSS_BAR_TIMEOUT  /* 0x4c41 */
 
506
 
 
507
 
 
508
/****************************************/
 
509
/* Device Interrupt                                     */
 
510
/****************************************/
 
511
 
 
512
#define DEVICE_INTERRUPT_CAUSE                                          0x4d0
 
513
#define DEVICE_INTERRUPT_MASK                                           0x4d4
 
514
#define DEVICE_ERROR_ADDRESS                                            0x4d8
 
515
 /*#define DEVICE_INTERRUPT_CAUSE                               0x4d01 */
 
516
 /*#define DEVICE_INTERRUPT_MASK                                0x4d41 */
 
517
#define DEVICE_ERROR_ADDR                               DEVICE_ERROR_ADDRESS  /*0x4d81 */
 
518
#define DEVICE_ERROR_DATA                               0x4dc
 
519
#define DEVICE_ERROR_PARITY                                     0x4e0
 
520
 
 
521
/****************************************/
 
522
/* Device debug registers                       */
 
523
/****************************************/
 
524
 
 
525
#define DEVICE_DEBUG_LOW                                        0x4e4
 
526
#define DEVICE_DEBUG_HIGH                               0x4e8
 
527
#define RUNIT_MMASK                                                     0x4f0
 
528
 
 
529
/****************************************/
 
530
/* DMA Record                                                   */
 
531
/****************************************/
 
532
 
 
533
 /*#define CHANNEL4_DMA_BYTE_COUNT                      0x9001 */
 
534
 /*#define CHANNEL5_DMA_BYTE_COUNT                      0x9041 */
 
535
 /*#define CHANNEL6_DMA_BYTE_COUNT                      0x9081 */
 
536
 /*#define CHANNEL7_DMA_BYTE_COUNT                      0x90C1 */
 
537
 /*#define CHANNEL4_DMA_SOURCE_ADDRESS          0x9101 */
 
538
 /*#define CHANNEL5_DMA_SOURCE_ADDRESS          0x9141 */
 
539
 /*#define CHANNEL6_DMA_SOURCE_ADDRESS          0x9181 */
 
540
 /*#define CHANNEL7_DMA_SOURCE_ADDRESS          0x91C1 */
 
541
 /*#define CHANNEL4_DMA_DESTINATION_ADDRESS             0x9201 */
 
542
 /*#define CHANNEL5_DMA_DESTINATION_ADDRESS             0x9241 */
 
543
 /*#define CHANNEL6_DMA_DESTINATION_ADDRESS             0x9281 */
 
544
 /*#define CHANNEL7_DMA_DESTINATION_ADDRESS             0x92C1 */
 
545
 /*#define CHANNEL4NEXT_RECORD_POINTER                  0x9301 */
 
546
 /*#define CHANNEL5NEXT_RECORD_POINTER                  0x9341 */
 
547
 /*#define CHANNEL6NEXT_RECORD_POINTER                  0x9381 */
 
548
 /*#define CHANNEL7NEXT_RECORD_POINTER                  0x93C1 */
 
549
 /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER           0x9701 */
 
550
 /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER           0x9741 */
 
551
 /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER           0x9781 */
 
552
 /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER           0x97C1 */
 
553
 /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS                0x8901 */
 
554
 /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS                0x8941 */
 
555
 /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS                0x8981 */
 
556
 /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS                0x89c1 */
 
557
 /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS                0x9901 */
 
558
 /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS                0x9941 */
 
559
 /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS                0x9981 */
 
560
 /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS                0x99c1 */
 
561
 /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a01 */
 
562
 /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a41 */
 
563
 /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a81 */
 
564
 /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8ac1 */
 
565
 /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a01 */
 
566
 /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a41 */
 
567
 /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a81 */
 
568
 /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9ac1 */
 
569
 /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b01 */
 
570
 /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b41 */
 
571
 /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b81 */
 
572
 /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc1 */
 
573
 /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b01 */
 
574
 /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b41 */
 
575
 /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b81 */
 
576
 /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc1 */
 
577
 
 
578
/****************************************/
 
579
/* DMA Channel Control                                  */
 
580
/****************************************/
 
581
 
 
582
#define CHANNEL0CONTROL                                 0x840
 
583
#define CHANNEL0CONTROL_HIGH                            0x880
 
584
#define CHANNEL1CONTROL                                 0x844
 
585
#define CHANNEL1CONTROL_HIGH                            0x884
 
586
#define CHANNEL2CONTROL                                 0x848
 
587
#define CHANNEL2CONTROL_HIGH                            0x888
 
588
#define CHANNEL3CONTROL                                 0x84C
 
589
#define CHANNEL3CONTROL_HIGH                            0x88C
 
590
 
 
591
#define DMA_CHANNEL0_CONTROL                            CHANNEL0CONTROL  /*0x8401 */
 
592
#define DMA_CHANNEL0_CONTROL_HIGH                       CHANNEL0CONTROL_HIGH  /*0x8801 */
 
593
#define DMA_CHANNEL1_CONTROL                            CHANNEL1CONTROL  /* 0x8441 */
 
594
#define DMA_CHANNEL1_CONTROL_HIGH                       CHANNEL1CONTROL_HIGH  /*0x8841 */
 
595
#define DMA_CHANNEL2_CONTROL                            CHANNEL2CONTROL  /*0x8481 */
 
596
#define DMA_CHANNEL2_CONTROL_HIGH                       CHANNEL2CONTROL_HIGH  /*0x8881 */
 
597
#define DMA_CHANNEL3_CONTROL                            CHANNEL3CONTROL  /*0x84C1 */
 
598
#define DMA_CHANNEL3_CONTROL_HIGH                       CHANNEL3CONTROL_HIGH  /*0x88C1 */
 
599
 
 
600
 /*#define CHANNEL4CONTROL                              0x9401 */
 
601
 /*#define CHANNEL4CONTROL_HIGH                         0x9801 */
 
602
 /*#define CHANNEL5CONTROL                              0x9441 */
 
603
 /*#define CHANNEL5CONTROL_HIGH                         0x9841 */
 
604
 /*#define CHANNEL6CONTROL                              0x9481 */
 
605
 /*#define CHANNEL6CONTROL_HIGH                         0x9881 */
 
606
 /*#define CHANNEL7CONTROL                              0x94C1 */
 
607
 /*#define CHANNEL7CONTROL_HIGH                         0x98C1 */
 
608
 
 
609
 
 
610
/****************************************/
 
611
/* DMA Arbiter                                                  */
 
612
/****************************************/
 
613
 
 
614
 /*#define ARBITER_CONTROL_0_3                          0x8601 */
 
615
#define ARBITER_CONTROL_4_7                             0x960
 
616
/****************************************/
 
617
/*           IDMA Registers             */
 
618
/****************************************/
 
619
 
 
620
#define DMA_CHANNEL0_BYTE_COUNT                                 CHANNEL0_DMA_BYTE_COUNT  /*0x8001 */
 
621
#define DMA_CHANNEL1_BYTE_COUNT                                 CHANNEL1_DMA_BYTE_COUNT  /*0x8041 */
 
622
#define DMA_CHANNEL2_BYTE_COUNT                                 CHANNEL2_DMA_BYTE_COUNT  /*0x8081 */
 
623
#define DMA_CHANNEL3_BYTE_COUNT                                 CHANNEL3_DMA_BYTE_COUNT  /*0x80C1 */
 
624
#define DMA_CHANNEL0_SOURCE_ADDR                                CHANNEL0_DMA_SOURCE_ADDRESS  /*0x8101 */
 
625
#define DMA_CHANNEL1_SOURCE_ADDR                                CHANNEL1_DMA_SOURCE_ADDRESS  /*0x8141 */
 
626
#define DMA_CHANNEL2_SOURCE_ADDR                                CHANNEL2_DMA_SOURCE_ADDRESS  /*0x8181 */
 
627
#define DMA_CHANNEL3_SOURCE_ADDR                                CHANNEL3_DMA_SOURCE_ADDRESS  /*0x81c1 */
 
628
#define DMA_CHANNEL0_DESTINATION_ADDR                           CHANNEL0_DMA_DESTINATION_ADDRESS  /*0x8201 */
 
629
#define DMA_CHANNEL1_DESTINATION_ADDR                           CHANNEL1_DMA_DESTINATION_ADDRESS  /*0x8241 */
 
630
#define DMA_CHANNEL2_DESTINATION_ADDR                           CHANNEL2_DMA_DESTINATION_ADDRESS  /*0x8281 */
 
631
#define DMA_CHANNEL3_DESTINATION_ADDR                           CHANNEL3_DMA_DESTINATION_ADDRESS  /*0x82C1 */
 
632
#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER            CHANNEL0NEXT_RECORD_POINTER  /*0x8301 */
 
633
#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER            CHANNEL1NEXT_RECORD_POINTER  /*0x8341 */
 
634
#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER            CHANNEL2NEXT_RECORD_POINTER  /*0x8381 */
 
635
#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER            CHANNEL3NEXT_RECORD_POINTER  /*0x83C1 */
 
636
#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER         CHANNEL0CURRENT_DESCRIPTOR_POINTER  /*0x8701 */
 
637
#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER         CHANNEL1CURRENT_DESCRIPTOR_POINTER  /*0x8741 */
 
638
#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER         CHANNEL2CURRENT_DESCRIPTOR_POINTER  /*0x8781 */
 
639
#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER         CHANNEL3CURRENT_DESCRIPTOR_POINTER  /*0x87C1 */
 
640
 
 
641
#define CHANNEL3CURRENT_DESCRIPTOR_POINTER              0x87C
 
642
#define CHANNEL2CURRENT_DESCRIPTOR_POINTER              0x878
 
643
#define CHANNEL1CURRENT_DESCRIPTOR_POINTER              0x874
 
644
#define CHANNEL0CURRENT_DESCRIPTOR_POINTER              0x870
 
645
#define CHANNEL0NEXT_RECORD_POINTER                     0x830
 
646
#define CHANNEL1NEXT_RECORD_POINTER                     0x834
 
647
#define CHANNEL2NEXT_RECORD_POINTER                     0x838
 
648
#define CHANNEL3NEXT_RECORD_POINTER                     0x83C
 
649
#define CHANNEL0_DMA_DESTINATION_ADDRESS                0x820
 
650
#define CHANNEL1_DMA_DESTINATION_ADDRESS                0x824
 
651
#define CHANNEL2_DMA_DESTINATION_ADDRESS                0x828
 
652
#define CHANNEL3_DMA_DESTINATION_ADDRESS                0x82C
 
653
#define CHANNEL0_DMA_SOURCE_ADDRESS                     0x810
 
654
#define CHANNEL1_DMA_SOURCE_ADDRESS                     0x814
 
655
#define CHANNEL2_DMA_SOURCE_ADDRESS                     0x818
 
656
#define CHANNEL3_DMA_SOURCE_ADDRESS                     0x81C
 
657
#define CHANNEL0_DMA_BYTE_COUNT                 0x800
 
658
#define CHANNEL1_DMA_BYTE_COUNT                 0x804
 
659
#define CHANNEL2_DMA_BYTE_COUNT                 0x808
 
660
#define CHANNEL3_DMA_BYTE_COUNT                 0x80C
 
661
 
 
662
 /*  IDMA Address Decoding Base Address Registers  */
 
663
 
 
664
#define DMA_BASE_ADDR_REG0                                              0xa00
 
665
#define DMA_BASE_ADDR_REG1                                              0xa08
 
666
#define DMA_BASE_ADDR_REG2                                              0xa10
 
667
#define DMA_BASE_ADDR_REG3                                              0xa18
 
668
#define DMA_BASE_ADDR_REG4                                              0xa20
 
669
#define DMA_BASE_ADDR_REG5                                              0xa28
 
670
#define DMA_BASE_ADDR_REG6                                              0xa30
 
671
#define DMA_BASE_ADDR_REG7                                              0xa38
 
672
 
 
673
 /*  IDMA Address Decoding Size Address Register   */
 
674
 
 
675
#define DMA_SIZE_REG0                                                   0xa04
 
676
#define DMA_SIZE_REG1                                                   0xa0c
 
677
#define DMA_SIZE_REG2                                                   0xa14
 
678
#define DMA_SIZE_REG3                                                   0xa1c
 
679
#define DMA_SIZE_REG4                                                   0xa24
 
680
#define DMA_SIZE_REG5                                                   0xa2c
 
681
#define DMA_SIZE_REG6                                                   0xa34
 
682
#define DMA_SIZE_REG7                                                   0xa3C
 
683
 
 
684
    /* IDMA Address Decoding High Address Remap and Access
 
685
                  Protection Registers                    */
 
686
 
 
687
#define DMA_HIGH_ADDR_REMAP_REG0                                0xa60
 
688
#define DMA_HIGH_ADDR_REMAP_REG1                                0xa64
 
689
#define DMA_HIGH_ADDR_REMAP_REG2                                0xa68
 
690
#define DMA_HIGH_ADDR_REMAP_REG3                                0xa6C
 
691
#define DMA_BASE_ADDR_ENABLE_REG                                0xa80
 
692
#define DMA_CHANNEL0_ACCESS_PROTECTION_REG              0xa70
 
693
#define DMA_CHANNEL1_ACCESS_PROTECTION_REG                 0xa74
 
694
#define DMA_CHANNEL2_ACCESS_PROTECTION_REG                 0xa78
 
695
#define DMA_CHANNEL3_ACCESS_PROTECTION_REG                 0xa7c
 
696
#define DMA_ARBITER_CONTROL                                             0x860
 
697
#define DMA_CROSS_BAR_TIMEOUT                                   0x8d0
 
698
 
 
699
 /*  IDMA Headers Retarget Registers   */
 
700
 
 
701
 /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL                    0x3e01 */
 
702
 /*#define CPU_IDMA_HEADERS_RETARGET_BASE                        0x3e81 */
 
703
 
 
704
#define DMA_HEADERS_RETARGET_CONTROL                    0xa84
 
705
#define DMA_HEADERS_RETARGET_BASE                       0xa88
 
706
 
 
707
/****************************************/
 
708
/* DMA Interrupt                                                */
 
709
/****************************************/
 
710
 
 
711
#define CHANELS0_3_INTERRUPT_CAUSE                      0x8c0
 
712
#define CHANELS0_3_INTERRUPT_MASK                       0x8c4
 
713
#define CHANELS0_3_ERROR_ADDRESS                        0x8c8
 
714
#define CHANELS0_3_ERROR_SELECT                         0x8cc
 
715
 /*#define CHANELS4_7_INTERRUPT_CAUSE                   0x9c01 */
 
716
 /*#define CHANELS4_7_INTERRUPT_MASK                    0x9c41 */
 
717
 /*#define CHANELS4_7_ERROR_ADDRESS                     0x9c81 */
 
718
 /*#define CHANELS4_7_ERROR_SELECT                      0x9cc1 */
 
719
 
 
720
#define DMA_INTERRUPT_CAUSE_REG                         CHANELS0_3_INTERRUPT_CAUSE  /*0x8c01 */
 
721
#define DMA_INTERRUPT_CAUSE_MASK                        CHANELS0_3_INTERRUPT_MASK  /*0x8c41 */
 
722
#define DMA_ERROR_ADDR                                          CHANELS0_3_ERROR_ADDRESS  /*0x8c81 */
 
723
#define DMA_ERROR_SELECT                                        CHANELS0_3_ERROR_SELECT  /*0x8cc1 */
 
724
 
 
725
 
 
726
/****************************************/
 
727
/* DMA Debug (for internal use)         */
 
728
/****************************************/
 
729
 
 
730
#define DMA_X0_ADDRESS                                          0x8e0
 
731
#define DMA_X0_COMMAND_AND_ID                           0x8e4
 
732
 /*#define DMA_X0_WRITE_DATA_LOW                                0x8e81 */
 
733
 /*#define DMA_X0_WRITE_DATA_HIGH                               0x8ec1 */
 
734
 /*#define DMA_X0_WRITE_BYTE_ENABLE                             0x8f81 */
 
735
 /*#define DMA_X0_READ_DATA_LOW                                 0x8f01 */
 
736
 /*#define DMA_X0_READ_DATA_HIGH                                0x8f41 */
 
737
 /*#define DMA_X0_READ_ID                                       0x8fc1 */
 
738
 /*#define DMA_X1_ADDRESS                                       0x9e01 */
 
739
 /*#define DMA_X1_COMMAND_AND_ID                        0x9e41 */
 
740
 /*#define DMA_X1_WRITE_DATA_LOW                                0x9e81 */
 
741
 /*#define DMA_X1_WRITE_DATA_HIGH                               0x9ec1 */
 
742
 /*#define DMA_X1_WRITE_BYTE_ENABLE                             0x9f81 */
 
743
 /*#define DMA_X1_READ_DATA_LOW                                 0x9f01 */
 
744
 /*#define DMA_X1_READ_DATA_HIGH                                0x9f41 */
 
745
 /*#define DMA_X1_READ_ID                                       0x9fc1 */
 
746
 
 
747
 /*  IDMA Debug Register ( for internal use )    */
 
748
 
 
749
#define DMA_DEBUG_LOW                                           DMA_X0_ADDRESS  /* 0x8e01 */
 
750
#define DMA_DEBUG_HIGH                                          DMA_X0_COMMAND_AND_ID  /*0x8e41 */
 
751
#define DMA_SPARE                                               0xA8C
 
752
 
 
753
 
 
754
/****************************************/
 
755
/* Timer_Counter                                                */
 
756
/****************************************/
 
757
 
 
758
#define TIMER_COUNTER0                                  0x850
 
759
#define TIMER_COUNTER1                                  0x854
 
760
#define TIMER_COUNTER2                                  0x858
 
761
#define TIMER_COUNTER3                                  0x85C
 
762
#define TIMER_COUNTER_0_3_CONTROL                       0x864
 
763
#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE               0x868
 
764
#define TIMER_COUNTER_0_3_INTERRUPT_MASK                0x86c
 
765
 /*#define TIMER_COUNTER4                                       0x9501 */
 
766
 /*#define TIMER_COUNTER5                                       0x9541 */
 
767
 /*#define TIMER_COUNTER6                                       0x9581 */
 
768
 /*#define TIMER_COUNTER7                                       0x95C1 */
 
769
 /*#define TIMER_COUNTER_4_7_CONTROL                    0x9641 */
 
770
 /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE            0x9681 */
 
771
 /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK                     0x96c1 */
 
772
 
 
773
/****************************************/
 
774
/* PCI Slave Address Decoding           */
 
775
/****************************************/
 
776
/****************************************/
 
777
/* PCI Slave Address Decoding registers */
 
778
/****************************************/
 
779
#define PCI_0_CS_0_BANK_SIZE                                    PCI_0SCS_0_BANK_SIZE  /*0xc081 */
 
780
#define PCI_1_CS_0_BANK_SIZE                                    PCI_1SCS_0_BANK_SIZE  /* 0xc881 */
 
781
#define PCI_0_CS_1_BANK_SIZE                                    PCI_0SCS_1_BANK_SIZE  /*0xd081 */
 
782
#define PCI_1_CS_1_BANK_SIZE                                    PCI_1SCS_1_BANK_SIZE  /* 0xd881 */
 
783
#define PCI_0_CS_2_BANK_SIZE                                    PCI_0SCS_2_BANK_SIZE  /*0xc0c1 */
 
784
#define PCI_1_CS_2_BANK_SIZE                                    PCI_1SCS_2_BANK_SIZE  /*0xc8c1 */
 
785
#define PCI_0_CS_3_BANK_SIZE                                    PCI_0SCS_3_BANK_SIZE  /*0xd0c1 */
 
786
#define PCI_1_CS_3_BANK_SIZE                                    PCI_1SCS_3_BANK_SIZE  /*0xd8c1 */
 
787
#define PCI_0_DEVCS_0_BANK_SIZE                                 PCI_0CS_0_BANK_SIZE  /*0xc101 */
 
788
#define PCI_1_DEVCS_0_BANK_SIZE                             PCI_1CS_0_BANK_SIZE  /*0xc901 */
 
789
#define PCI_0_DEVCS_1_BANK_SIZE                             PCI_0CS_1_BANK_SIZE  /*0xd101 */
 
790
#define PCI_1_DEVCS_1_BANK_SIZE                             PCI_1CS_1_BANK_SIZE  /* 0xd901 */
 
791
#define PCI_0_DEVCS_2_BANK_SIZE                             PCI_0CS_2_BANK_SIZE  /* 0xd181 */
 
792
#define PCI_1_DEVCS_2_BANK_SIZE                             PCI_1CS_2_BANK_SIZE  /*0xd981 */
 
793
#define PCI_0_DEVCS_3_BANK_SIZE                             PCI_0CS_3_BANK_SIZE  /* 0xc141 */
 
794
#define PCI_1_DEVCS_3_BANK_SIZE                             PCI_1CS_3_BANK_SIZE  /*0xc941 */
 
795
#define PCI_0_DEVCS_BOOT_BANK_SIZE                      PCI_0CS_BOOT_BANK_SIZE  /*0xd141 */
 
796
#define PCI_1_DEVCS_BOOT_BANK_SIZE                      PCI_1CS_BOOT_BANK_SIZE  /* 0xd941 */
 
797
#define PCI_0_P2P_MEM0_BAR_SIZE                             PCI_0P2P_MEM0_BAR_SIZE  /*0xd1c1 */
 
798
#define PCI_1_P2P_MEM0_BAR_SIZE                             PCI_1P2P_MEM0_BAR_SIZE  /*0xd9c1 */
 
799
#define PCI_0_P2P_MEM1_BAR_SIZE                             PCI_0P2P_MEM1_BAR_SIZE  /*0xd201 */
 
800
#define PCI_1_P2P_MEM1_BAR_SIZE                             PCI_1P2P_MEM1_BAR_SIZE  /*0xda01 */
 
801
#define PCI_0_P2P_I_O_BAR_SIZE                                  PCI_0P2P_I_O_BAR_SIZE  /*0xd241 */
 
802
#define PCI_1_P2P_I_O_BAR_SIZE                                  PCI_1P2P_I_O_BAR_SIZE  /*0xda41 */
 
803
#define PCI_0_CPU_BAR_SIZE                                      PCI_0CPU_BAR_SIZE  /*0xd281 */
 
804
#define PCI_1_CPU_BAR_SIZE                                      PCI_1CPU_BAR_SIZE  /*0xda81 */
 
805
#define PCI_0_INTERNAL_SRAM_BAR_SIZE                    PCI_0DAC_SCS_0_BANK_SIZE  /*0xe001 */
 
806
#define PCI_1_INTERNAL_SRAM_BAR_SIZE                    PCI_1DAC_SCS_0_BANK_SIZE  /*0xe801 */
 
807
#define PCI_0_EXPANSION_ROM_BAR_SIZE                    PCI_0EXPANSION_ROM_BAR_SIZE  /*0xd2c1 */
 
808
#define PCI_1_EXPANSION_ROM_BAR_SIZE                   PCI_1EXPANSION_ROM_BAR_SIZE  /*0xd9c1 */
 
809
#define PCI_0_BASE_ADDR_REG_ENABLE                      PCI_0BASE_ADDRESS_REGISTERS_ENABLE  /*0xc3c1 */
 
810
#define PCI_1_BASE_ADDR_REG_ENABLE                      PCI_1BASE_ADDRESS_REGISTERS_ENABLE  /*0xcbc1 */
 
811
#define PCI_0_CS_0_BASE_ADDR_REMAP              PCI_0SCS_0_BASE_ADDRESS_REMAP  /*0xc481 */
 
812
#define PCI_1_CS_0_BASE_ADDR_REMAP              PCI_1SCS_0_BASE_ADDRESS_REMAP  /*0xcc81 */
 
813
#define PCI_0_CS_1_BASE_ADDR_REMAP              PCI_0SCS_1_BASE_ADDRESS_REMAP  /*0xd481 */
 
814
#define PCI_1_CS_1_BASE_ADDR_REMAP              PCI_1SCS_1_BASE_ADDRESS_REMAP  /*0xdc81 */
 
815
#define PCI_0_CS_2_BASE_ADDR_REMAP              PCI_0SCS_2_BASE_ADDRESS_REMAP  /*0xc4c1 */
 
816
#define PCI_1_CS_2_BASE_ADDR_REMAP              PCI_1SCS_2_BASE_ADDRESS_REMAP  /*0xccc1 */
 
817
#define PCI_0_CS_3_BASE_ADDR_REMAP              PCI_0SCS_3_BASE_ADDRESS_REMAP  /*0xd4c1 */
 
818
#define PCI_1_CS_3_BASE_ADDR_REMAP              PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */
 
819
#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP
 
820
#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP
 
821
#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP
 
822
#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP
 
823
#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP
 
824
#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP
 
825
#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP
 
826
#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP
 
827
#define PCI_0_DEVCS_0_BASE_ADDR_REMAP           PCI_0CS_0_BASE_ADDRESS_REMAP  /*0xc501 */
 
828
#define PCI_1_DEVCS_0_BASE_ADDR_REMAP           PCI_1CS_0_BASE_ADDRESS_REMAP  /*0xcd01 */
 
829
#define PCI_0_DEVCS_1_BASE_ADDR_REMAP           PCI_0CS_1_BASE_ADDRESS_REMAP  /*0xd501 */
 
830
#define PCI_1_DEVCS_1_BASE_ADDR_REMAP           PCI_1CS_1_BASE_ADDRESS_REMAP  /*0xdd01 */
 
831
#define PCI_0_DEVCS_2_BASE_ADDR_REMAP           PCI_0CS_2_BASE_ADDRESS_REMAP  /*0xd581 */
 
832
#define PCI_1_DEVCS_2_BASE_ADDR_REMAP           PCI_1CS_2_BASE_ADDRESS_REMAP  /*0xdd81 */
 
833
#define PCI_0_DEVCS_3_BASE_ADDR_REMAP                   PCI_0CS_3_BASE_ADDRESS_REMAP  /*0xc541 */
 
834
#define PCI_1_DEVCS_3_BASE_ADDR_REMAP                   PCI_1CS_3_BASE_ADDRESS_REMAP  /*0xcd41 */
 
835
#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP  /*0xd541 */
 
836
#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP  /*0xdd41 */
 
837
#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xd5c1 */
 
838
#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xddc1 */
 
839
#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xd601 */
 
840
#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xde01 */
 
841
#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW      PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xd641 */
 
842
#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW      PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xde41 */
 
843
#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH     PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xd681 */
 
844
#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH     PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xde81 */
 
845
#define PCI_0_P2P_I_O_BASE_ADDR_REMAP                   PCI_0P2P_I_O_BASE_ADDRESS_REMAP  /*0xd6c1 */
 
846
#define PCI_1_P2P_I_O_BASE_ADDR_REMAP                   PCI_1P2P_I_O_BASE_ADDRESS_REMAP  /*0xdec 1 */
 
847
#define PCI_0_CPU_BASE_ADDR_REMAP_LOW                   PCI_0CPU_BASE_ADDRESS_REMAP  /*0xd701 */
 
848
#define PCI_1_CPU_BASE_ADDR_REMAP_LOW                   PCI_1CPU_BASE_ADDRESS_REMAP  /*0xdf01 */
 
849
#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH                  0xd74
 
850
#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH                  0xdf4
 
851
#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP             PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP  /*0xf001 */
 
852
#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP             0xf80
 
853
#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP                PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xf381 */
 
854
#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP                PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xfb81 */
 
855
#define PCI_0_ADDR_DECODE_CONTROL                               PCI_0ADDRESS_DECODE_CONTROL  /*0xd3c1 */
 
856
#define PCI_1_ADDR_DECODE_CONTROL                               PCI_1ADDRESS_DECODE_CONTROL  /*0xdbc1 */
 
857
#define PCI_0_HEADERS_RETARGET_CONTROL                  0xF40
 
858
#define PCI_1_HEADERS_RETARGET_CONTROL                          0xFc0
 
859
#define PCI_0_HEADERS_RETARGET_BASE                             0xF44
 
860
#define PCI_1_HEADERS_RETARGET_BASE                             0xFc4
 
861
#define PCI_0_HEADERS_RETARGET_HIGH                             0xF48
 
862
#define PCI_1_HEADERS_RETARGET_HIGH                             0xFc8
 
863
 
 
864
#define PCI_0SCS_0_BANK_SIZE                            0xc08
 
865
#define PCI_1SCS_0_BANK_SIZE                            0xc88
 
866
#define PCI_0SCS_1_BANK_SIZE                            0xd08
 
867
#define PCI_1SCS_1_BANK_SIZE                            0xd88
 
868
#define PCI_0SCS_2_BANK_SIZE                            0xc0c
 
869
#define PCI_1SCS_2_BANK_SIZE                            0xc8c
 
870
#define PCI_0SCS_3_BANK_SIZE                            0xd0c
 
871
#define PCI_1SCS_3_BANK_SIZE                            0xd8c
 
872
#define PCI_0CS_0_BANK_SIZE                             0xc10
 
873
#define PCI_1CS_0_BANK_SIZE                             0xc90
 
874
#define PCI_0CS_1_BANK_SIZE                             0xd10
 
875
#define PCI_1CS_1_BANK_SIZE                             0xd90
 
876
#define PCI_0CS_2_BANK_SIZE                             0xd18
 
877
#define PCI_1CS_2_BANK_SIZE                             0xd98
 
878
#define PCI_0CS_3_BANK_SIZE                             0xc14
 
879
#define PCI_1CS_3_BANK_SIZE                             0xc94
 
880
#define PCI_0CS_BOOT_BANK_SIZE                          0xd14
 
881
#define PCI_1CS_BOOT_BANK_SIZE                          0xd94
 
882
#define PCI_0P2P_MEM0_BAR_SIZE                                          0xd1c
 
883
#define PCI_1P2P_MEM0_BAR_SIZE                                          0xd9c
 
884
#define PCI_0P2P_MEM1_BAR_SIZE                                          0xd20
 
885
#define PCI_1P2P_MEM1_BAR_SIZE                                          0xda0
 
886
#define PCI_0P2P_I_O_BAR_SIZE                                           0xd24
 
887
#define PCI_1P2P_I_O_BAR_SIZE                                           0xda4
 
888
#define PCI_0CPU_BAR_SIZE                                               0xd28
 
889
#define PCI_1CPU_BAR_SIZE                                               0xda8
 
890
#define PCI_0DAC_SCS_0_BANK_SIZE                                0xe00
 
891
#define PCI_1DAC_SCS_0_BANK_SIZE                                0xe80
 
892
#define PCI_0DAC_SCS_1_BANK_SIZE                                0xe04
 
893
#define PCI_1DAC_SCS_1_BANK_SIZE                                0xe84
 
894
#define PCI_0DAC_SCS_2_BANK_SIZE                                0xe08
 
895
#define PCI_1DAC_SCS_2_BANK_SIZE                                0xe88
 
896
#define PCI_0DAC_SCS_3_BANK_SIZE                                0xe0c
 
897
#define PCI_1DAC_SCS_3_BANK_SIZE                                0xe8c
 
898
#define PCI_0DAC_CS_0_BANK_SIZE                                 0xe10
 
899
#define PCI_1DAC_CS_0_BANK_SIZE                                 0xe90
 
900
#define PCI_0DAC_CS_1_BANK_SIZE                                 0xe14
 
901
#define PCI_1DAC_CS_1_BANK_SIZE                                 0xe94
 
902
#define PCI_0DAC_CS_2_BANK_SIZE                                 0xe18
 
903
#define PCI_1DAC_CS_2_BANK_SIZE                                 0xe98
 
904
#define PCI_0DAC_CS_3_BANK_SIZE                                 0xe1c
 
905
#define PCI_1DAC_CS_3_BANK_SIZE                                 0xe9c
 
906
#define PCI_0DAC_BOOTCS_BANK_SIZE                               0xe20
 
907
#define PCI_1DAC_BOOTCS_BANK_SIZE                               0xea0
 
908
 
 
909
#define PCI_0DAC_P2P_MEM0_BAR_SIZE                              0xe24
 
910
#define PCI_1DAC_P2P_MEM0_BAR_SIZE                              0xea4
 
911
#define PCI_0DAC_P2P_MEM1_BAR_SIZE                              0xe28
 
912
#define PCI_1DAC_P2P_MEM1_BAR_SIZE                              0xea8
 
913
#define PCI_0DAC_CPU_BAR_SIZE                                           0xe2c
 
914
#define PCI_1DAC_CPU_BAR_SIZE                                           0xeac
 
915
#define PCI_0EXPANSION_ROM_BAR_SIZE                             0xd2c
 
916
#define PCI_1EXPANSION_ROM_BAR_SIZE                             0xdac
 
917
#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE              0xc3c
 
918
#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE              0xcbc
 
919
#define PCI_0SCS_0_BASE_ADDRESS_REMAP                   0xc48
 
920
#define PCI_1SCS_0_BASE_ADDRESS_REMAP                   0xcc8
 
921
#define PCI_0SCS_1_BASE_ADDRESS_REMAP                   0xd48
 
922
#define PCI_1SCS_1_BASE_ADDRESS_REMAP                   0xdc8
 
923
#define PCI_0SCS_2_BASE_ADDRESS_REMAP                   0xc4c
 
924
#define PCI_1SCS_2_BASE_ADDRESS_REMAP                   0xccc
 
925
#define PCI_0SCS_3_BASE_ADDRESS_REMAP                   0xd4c
 
926
#define PCI_1SCS_3_BASE_ADDRESS_REMAP                   0xdcc
 
927
#define PCI_0CS_0_BASE_ADDRESS_REMAP                    0xc50
 
928
#define PCI_1CS_0_BASE_ADDRESS_REMAP                    0xcd0
 
929
#define PCI_0CS_1_BASE_ADDRESS_REMAP                    0xd50
 
930
#define PCI_1CS_1_BASE_ADDRESS_REMAP                    0xdd0
 
931
#define PCI_0CS_2_BASE_ADDRESS_REMAP                    0xd58
 
932
#define PCI_1CS_2_BASE_ADDRESS_REMAP                    0xdd8
 
933
#define PCI_0CS_3_BASE_ADDRESS_REMAP                    0xc54
 
934
#define PCI_1CS_3_BASE_ADDRESS_REMAP                    0xcd4
 
935
#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP       0xd54
 
936
#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP       0xdd4
 
937
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW                    0xd5c
 
938
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW              0xddc
 
939
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH             0xd60
 
940
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH             0xde0
 
941
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW             0xd64
 
942
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW             0xde4
 
943
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH            0xd68
 
944
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH            0xde8
 
945
#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP                         0xd6c
 
946
#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP                         0xdec
 
947
#define PCI_0CPU_BASE_ADDRESS_REMAP                             0xd70
 
948
#define PCI_1CPU_BASE_ADDRESS_REMAP                             0xdf0
 
949
#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP                       0xf00
 
950
#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP                       0xff0
 
951
#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP                       0xf04
 
952
#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP                       0xf84
 
953
#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP                       0xf08
 
954
#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP                       0xf88
 
955
#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP                       0xf0c
 
956
#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP                       0xf8c
 
957
#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP                        0xf10
 
958
#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP                        0xf90
 
959
#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP                        0xf14
 
960
#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP                        0xf94
 
961
#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP                        0xf18
 
962
#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP                        0xf98
 
963
#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP                        0xf1c
 
964
#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP                        0xf9c
 
965
#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP                      0xf20
 
966
#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP                  0xfa0
 
967
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xf24
 
968
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xfa4
 
969
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xf28
 
970
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xfa8
 
971
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW        0xf2c
 
972
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW     0xfac
 
973
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xf30
 
974
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xfb0
 
975
#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP                         0xf34
 
976
#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP                         0xfb4
 
977
#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP                   0xf38
 
978
#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP                   0xfb8
 
979
#define PCI_0ADDRESS_DECODE_CONTROL                             0xd3c
 
980
#define PCI_1ADDRESS_DECODE_CONTROL                             0xdbc
 
981
 
 
982
/****************************************/
 
983
/* PCI Control                          */
 
984
/****************************************/
 
985
 
 
986
#define PCI_0COMMAND                                                                            0xc00
 
987
#define PCI_1COMMAND                                                                            0xc80
 
988
#define PCI_0MODE                                           0xd00
 
989
#define PCI_1MODE                                           0xd80
 
990
#define PCI_0TIMEOUT_RETRY                                                                      0xc04
 
991
#define PCI_1TIMEOUT_RETRY                                                                      0xc84
 
992
#define PCI_0READ_BUFFER_DISCARD_TIMER                      0xd04
 
993
#define PCI_1READ_BUFFER_DISCARD_TIMER                      0xd84
 
994
#define MSI_0TRIGGER_TIMER                                  0xc38
 
995
#define MSI_1TRIGGER_TIMER                                  0xcb8
 
996
#define PCI_0ARBITER_CONTROL                                0x1d00
 
997
#define PCI_1ARBITER_CONTROL                                0x1d80
 
998
/* changing untill here */
 
999
#define PCI_0CROSS_BAR_CONTROL_LOW                           0x1d08
 
1000
#define PCI_0CROSS_BAR_CONTROL_HIGH                          0x1d0c
 
1001
#define PCI_0CROSS_BAR_TIMEOUT                               0x1d04
 
1002
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d18
 
1003
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d1c
 
1004
#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d10
 
1005
#define PCI_0P2P_CONFIGURATION                               0x1d14
 
1006
#define PCI_0ACCESS_CONTROL_BASE_0_LOW                       0x1e00
 
1007
#define PCI_0ACCESS_CONTROL_BASE_0_HIGH                      0x1e04
 
1008
#define PCI_0ACCESS_CONTROL_TOP_0                            0x1e08
 
1009
#define PCI_0ACCESS_CONTROL_BASE_1_LOW                       0x1e10
 
1010
#define PCI_0ACCESS_CONTROL_BASE_1_HIGH                      0x1e14
 
1011
#define PCI_0ACCESS_CONTROL_TOP_1                            0x1e18
 
1012
#define PCI_0ACCESS_CONTROL_BASE_2_LOW                       0x1e20
 
1013
#define PCI_0ACCESS_CONTROL_BASE_2_HIGH                      0x1e24
 
1014
#define PCI_0ACCESS_CONTROL_TOP_2                            0x1e28
 
1015
#define PCI_0ACCESS_CONTROL_BASE_3_LOW                       0x1e30
 
1016
#define PCI_0ACCESS_CONTROL_BASE_3_HIGH                      0x1e34
 
1017
#define PCI_0ACCESS_CONTROL_TOP_3                            0x1e38
 
1018
#define PCI_0ACCESS_CONTROL_BASE_4_LOW                       0x1e40
 
1019
#define PCI_0ACCESS_CONTROL_BASE_4_HIGH                      0x1e44
 
1020
#define PCI_0ACCESS_CONTROL_TOP_4                            0x1e48
 
1021
#define PCI_0ACCESS_CONTROL_BASE_5_LOW                       0x1e50
 
1022
#define PCI_0ACCESS_CONTROL_BASE_5_HIGH                      0x1e54
 
1023
#define PCI_0ACCESS_CONTROL_TOP_5                            0x1e58
 
1024
#define PCI_0ACCESS_CONTROL_BASE_6_LOW                       0x1e60
 
1025
#define PCI_0ACCESS_CONTROL_BASE_6_HIGH                      0x1e64
 
1026
#define PCI_0ACCESS_CONTROL_TOP_6                            0x1e68
 
1027
#define PCI_0ACCESS_CONTROL_BASE_7_LOW                       0x1e70
 
1028
#define PCI_0ACCESS_CONTROL_BASE_7_HIGH                      0x1e74
 
1029
#define PCI_0ACCESS_CONTROL_TOP_7                            0x1e78
 
1030
#define PCI_1CROSS_BAR_CONTROL_LOW                           0x1d88
 
1031
#define PCI_1CROSS_BAR_CONTROL_HIGH                          0x1d8c
 
1032
#define PCI_1CROSS_BAR_TIMEOUT                               0x1d84
 
1033
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d98
 
1034
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d9c
 
1035
#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d90
 
1036
#define PCI_1P2P_CONFIGURATION                               0x1d94
 
1037
#define PCI_1ACCESS_CONTROL_BASE_0_LOW                       0x1e80
 
1038
#define PCI_1ACCESS_CONTROL_BASE_0_HIGH                      0x1e84
 
1039
#define PCI_1ACCESS_CONTROL_TOP_0                            0x1e88
 
1040
#define PCI_1ACCESS_CONTROL_BASE_1_LOW                       0x1e90
 
1041
#define PCI_1ACCESS_CONTROL_BASE_1_HIGH                      0x1e94
 
1042
#define PCI_1ACCESS_CONTROL_TOP_1                            0x1e98
 
1043
#define PCI_1ACCESS_CONTROL_BASE_2_LOW                       0x1ea0
 
1044
#define PCI_1ACCESS_CONTROL_BASE_2_HIGH                      0x1ea4
 
1045
#define PCI_1ACCESS_CONTROL_TOP_2                            0x1ea8
 
1046
#define PCI_1ACCESS_CONTROL_BASE_3_LOW                       0x1eb0
 
1047
#define PCI_1ACCESS_CONTROL_BASE_3_HIGH                      0x1eb4
 
1048
#define PCI_1ACCESS_CONTROL_TOP_3                            0x1eb8
 
1049
#define PCI_1ACCESS_CONTROL_BASE_4_LOW                       0x1ec0
 
1050
#define PCI_1ACCESS_CONTROL_BASE_4_HIGH                      0x1ec4
 
1051
#define PCI_1ACCESS_CONTROL_TOP_4                            0x1ec8
 
1052
#define PCI_1ACCESS_CONTROL_BASE_5_LOW                       0x1ed0
 
1053
#define PCI_1ACCESS_CONTROL_BASE_5_HIGH                      0x1ed4
 
1054
#define PCI_1ACCESS_CONTROL_TOP_5                            0x1ed8
 
1055
#define PCI_1ACCESS_CONTROL_BASE_6_LOW                       0x1ee0
 
1056
#define PCI_1ACCESS_CONTROL_BASE_6_HIGH                      0x1ee4
 
1057
#define PCI_1ACCESS_CONTROL_TOP_6                            0x1ee8
 
1058
#define PCI_1ACCESS_CONTROL_BASE_7_LOW                       0x1ef0
 
1059
#define PCI_1ACCESS_CONTROL_BASE_7_HIGH                      0x1ef4
 
1060
#define PCI_1ACCESS_CONTROL_TOP_7                            0x1ef8
 
1061
 
 
1062
/****************************************/
 
1063
/* PCI Snoop Control                    */
 
1064
/****************************************/
 
1065
 
 
1066
#define PCI_0SNOOP_CONTROL_BASE_0_LOW                        0x1f00
 
1067
#define PCI_0SNOOP_CONTROL_BASE_0_HIGH                       0x1f04
 
1068
#define PCI_0SNOOP_CONTROL_TOP_0                             0x1f08
 
1069
#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW                      0x1f10
 
1070
#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f14
 
1071
#define PCI_0SNOOP_CONTROL_TOP_1                             0x1f18
 
1072
#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW                      0x1f20
 
1073
#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH                     0x1f24
 
1074
#define PCI_0SNOOP_CONTROL_TOP_2                             0x1f28
 
1075
#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW                      0x1f30
 
1076
#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH                     0x1f34
 
1077
#define PCI_0SNOOP_CONTROL_TOP_3                             0x1f38
 
1078
#define PCI_1SNOOP_CONTROL_BASE_0_LOW                        0x1f80
 
1079
#define PCI_1SNOOP_CONTROL_BASE_0_HIGH                       0x1f84
 
1080
#define PCI_1SNOOP_CONTROL_TOP_0                             0x1f88
 
1081
#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW                      0x1f90
 
1082
#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f94
 
1083
#define PCI_1SNOOP_CONTROL_TOP_1                             0x1f98
 
1084
#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW                      0x1fa0
 
1085
#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH                     0x1fa4
 
1086
#define PCI_1SNOOP_CONTROL_TOP_2                             0x1fa8
 
1087
#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW                      0x1fb0
 
1088
#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH                     0x1fb4
 
1089
#define PCI_1SNOOP_CONTROL_TOP_3                             0x1fb8
 
1090
 
 
1091
/****************************************/
 
1092
/* PCI Configuration Address            */
 
1093
/****************************************/
 
1094
 
 
1095
#define PCI_0CONFIGURATION_ADDRESS                                                      0xcf8
 
1096
#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER                0xcfc
 
1097
#define PCI_1CONFIGURATION_ADDRESS                                                      0xc78
 
1098
#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER                0xc7c
 
1099
#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER                     0xc34
 
1100
#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER                     0xcb4
 
1101
 
 
1102
/****************************************/
 
1103
/* PCI Error Report                     */
 
1104
/****************************************/
 
1105
 
 
1106
#define PCI_0SERR_MASK                                                                           0xc28
 
1107
#define PCI_0ERROR_ADDRESS_LOW                               0x1d40
 
1108
#define PCI_0ERROR_ADDRESS_HIGH                              0x1d44
 
1109
#define PCI_0ERROR_DATA_LOW                                  0x1d48
 
1110
#define PCI_0ERROR_DATA_HIGH                                 0x1d4c
 
1111
#define PCI_0ERROR_COMMAND                                   0x1d50
 
1112
#define PCI_0ERROR_CAUSE                                     0x1d58
 
1113
#define PCI_0ERROR_MASK                                      0x1d5c
 
1114
#define PCI_1SERR_MASK                                                                           0xca8
 
1115
#define PCI_1ERROR_ADDRESS_LOW                               0x1dc0
 
1116
#define PCI_1ERROR_ADDRESS_HIGH                              0x1dc4
 
1117
#define PCI_1ERROR_DATA_LOW                                  0x1dc8
 
1118
#define PCI_1ERROR_DATA_HIGH                                 0x1dcc
 
1119
#define PCI_1ERROR_COMMAND                                   0x1dd0
 
1120
#define PCI_1ERROR_CAUSE                                     0x1dd8
 
1121
#define PCI_1ERROR_MASK                                      0x1ddc
 
1122
 
 
1123
 
 
1124
/****************************************/
 
1125
/* Lslave Debug  (for internal use)     */
 
1126
/****************************************/
 
1127
 
 
1128
#define L_SLAVE_X0_ADDRESS                                  0x1d20
 
1129
#define L_SLAVE_X0_COMMAND_AND_ID                           0x1d24
 
1130
#define L_SLAVE_X1_ADDRESS                                  0x1d28
 
1131
#define L_SLAVE_X1_COMMAND_AND_ID                           0x1d2c
 
1132
#define L_SLAVE_WRITE_DATA_LOW                              0x1d30
 
1133
#define L_SLAVE_WRITE_DATA_HIGH                             0x1d34
 
1134
#define L_SLAVE_WRITE_BYTE_ENABLE                           0x1d60
 
1135
#define L_SLAVE_READ_DATA_LOW                               0x1d38
 
1136
#define L_SLAVE_READ_DATA_HIGH                              0x1d3c
 
1137
#define L_SLAVE_READ_ID                                     0x1d64
 
1138
 
 
1139
/****************************************/
 
1140
/* PCI Configuration Function 0         */
 
1141
/****************************************/
 
1142
 
 
1143
#define PCI_DEVICE_AND_VENDOR_ID                                                        0x000
 
1144
#define PCI_STATUS_AND_COMMAND                                                          0x004
 
1145
#define PCI_CLASS_CODE_AND_REVISION_ID                                  0x008
 
1146
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE           0x00C
 
1147
#define PCI_SCS_0_BASE_ADDRESS                                                  0x010
 
1148
#define PCI_SCS_1_BASE_ADDRESS                                                      0x014
 
1149
#define PCI_SCS_2_BASE_ADDRESS                                                      0x018
 
1150
#define PCI_SCS_3_BASE_ADDRESS                                                  0x01C
 
1151
#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS       0x020
 
1152
#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS           0x024
 
1153
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID                        0x02C
 
1154
#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER                         0x030
 
1155
#define PCI_CAPABILTY_LIST_POINTER                          0x034
 
1156
#define PCI_INTERRUPT_PIN_AND_LINE                                                  0x03C
 
1157
#define PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
 
1158
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
 
1159
#define PCI_VPD_ADDRESS                                     0x048
 
1160
#define PCI_VPD_DATA                                        0x04c
 
1161
#define PCI_MSI_MESSAGE_CONTROL                             0x050
 
1162
#define PCI_MSI_MESSAGE_ADDRESS                             0x054
 
1163
#define PCI_MSI_MESSAGE_UPPER_ADDRESS                       0x058
 
1164
#define PCI_MSI_MESSAGE_DATA                                0x05c
 
1165
#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY                 0x058
 
1166
 
 
1167
/****************************************/
 
1168
/* PCI Configuration Function 1         */
 
1169
/****************************************/
 
1170
 
 
1171
#define PCI_CS_0_BASE_ADDRESS                                                   0x110
 
1172
#define PCI_CS_1_BASE_ADDRESS                                                       0x114
 
1173
#define PCI_CS_2_BASE_ADDRESS                                                       0x118
 
1174
#define PCI_CS_3_BASE_ADDRESS                                                   0x11c
 
1175
#define PCI_BOOTCS_BASE_ADDRESS                             0x120
 
1176
 
 
1177
/****************************************/
 
1178
/* PCI Configuration Function 2         */
 
1179
/****************************************/
 
1180
 
 
1181
#define PCI_P2P_MEM0_BASE_ADDRESS                                               0x210
 
1182
 /*#define PCI_P2P_MEM1_BASE_ADDRESS                                                    0x2141 */
 
1183
#define PCI_P2P_I_O_BASE_ADDRESS                                                        0x218
 
1184
 /*#define PCI_CPU_BASE_ADDRESS                                                     0x21c1 */
 
1185
 
 
1186
/****************************************/
 
1187
/* PCI Configuration Function 4         */
 
1188
/****************************************/
 
1189
 
 
1190
#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW                                          0x410
 
1191
#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH                                     0x414
 
1192
#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW                                      0x418
 
1193
#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH                                     0x41c
 
1194
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW                   0x420
 
1195
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH                  0x424
 
1196
 
 
1197
 
 
1198
/****************************************/
 
1199
/* PCI Configuration Function 5         */
 
1200
/****************************************/
 
1201
 
 
1202
#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW                                          0x510
 
1203
#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH                                     0x514
 
1204
#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW                                      0x518
 
1205
#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH                                     0x51c
 
1206
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW                   0x520
 
1207
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH                  0x524
 
1208
 
 
1209
 
 
1210
/****************************************/
 
1211
/* PCI Configuration Function 6         */
 
1212
/****************************************/
 
1213
 
 
1214
#define PCI_DAC_CS_0_BASE_ADDRESS_LOW                                           0x610
 
1215
#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH                                      0x614
 
1216
#define PCI_DAC_CS_1_BASE_ADDRESS_LOW                                       0x618
 
1217
#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH                                      0x61c
 
1218
#define PCI_DAC_CS_2_BASE_ADDRESS_LOW                           0x620
 
1219
#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH                          0x624
 
1220
 
 
1221
/****************************************/
 
1222
/* PCI Configuration Function 7         */
 
1223
/****************************************/
 
1224
 
 
1225
#define PCI_DAC_CS_3_BASE_ADDRESS_LOW                                           0x710
 
1226
#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH                                      0x714
 
1227
#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW                                     0x718
 
1228
#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH                                    0x71c
 
1229
#define PCI_DAC_CPU_BASE_ADDRESS_LOW                            0x720
 
1230
#define PCI_DAC_CPU_BASE_ADDRESS_HIGH                           0x724
 
1231
 
 
1232
/****************************** MV64360 and MV64460 PCI ***************************/
 
1233
/***********************************/
 
1234
/*   PCI Control Register Map      */
 
1235
/***********************************/
 
1236
 
 
1237
#define PCI_0_DLL_STATUS_AND_COMMAND                            0x1d20
 
1238
#define PCI_1_DLL_STATUS_AND_COMMAND                            0x1da0
 
1239
#define PCI_0_MPP_PADS_DRIVE_CONTROL                            0x1d1C
 
1240
#define PCI_1_MPP_PADS_DRIVE_CONTROL                            0x1d9C
 
1241
#define PCI_0_COMMAND                                   0xc00
 
1242
#define PCI_1_COMMAND                                   0xc80
 
1243
#define PCI_0_MODE                                                      0xd00
 
1244
#define PCI_1_MODE                                                      0xd80
 
1245
#define PCI_0_RETRY                                             0xc04
 
1246
#define PCI_1_RETRY                                             0xc84
 
1247
#define PCI_0_READ_BUFFER_DISCARD_TIMER                         0xd04
 
1248
#define PCI_1_READ_BUFFER_DISCARD_TIMER                         0xd84
 
1249
#define PCI_0_MSI_TRIGGER_TIMER                                         0xc38
 
1250
#define PCI_1_MSI_TRIGGER_TIMER                                         0xcb8
 
1251
#define PCI_0_ARBITER_CONTROL                                           0x1d00
 
1252
#define PCI_1_ARBITER_CONTROL                                           0x1d80
 
1253
#define PCI_0_CROSS_BAR_CONTROL_LOW                             0x1d08
 
1254
#define PCI_1_CROSS_BAR_CONTROL_LOW                             0x1d88
 
1255
#define PCI_0_CROSS_BAR_CONTROL_HIGH                            0x1d0c
 
1256
#define PCI_1_CROSS_BAR_CONTROL_HIGH                            0x1d8c
 
1257
#define PCI_0_CROSS_BAR_TIMEOUT                                 0x1d04
 
1258
#define PCI_1_CROSS_BAR_TIMEOUT                                 0x1d84
 
1259
#define PCI_0_SYNC_BARRIER_TRIGGER_REG                          0x1D18
 
1260
#define PCI_1_SYNC_BARRIER_TRIGGER_REG                          0x1D98
 
1261
#define PCI_0_SYNC_BARRIER_VIRTUAL_REG                          0x1d10
 
1262
#define PCI_1_SYNC_BARRIER_VIRTUAL_REG                          0x1d90
 
1263
#define PCI_0_P2P_CONFIG                                                0x1d14
 
1264
#define PCI_1_P2P_CONFIG                                                0x1d94
 
1265
 
 
1266
#define PCI_0_ACCESS_CONTROL_BASE_0_LOW                         0x1e00
 
1267
#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH                        0x1e04
 
1268
#define PCI_0_ACCESS_CONTROL_SIZE_0                             0x1e08
 
1269
#define PCI_0_ACCESS_CONTROL_BASE_1_LOW                         0x1e10
 
1270
#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH                        0x1e14
 
1271
#define PCI_0_ACCESS_CONTROL_SIZE_1                             0x1e18
 
1272
#define PCI_0_ACCESS_CONTROL_BASE_2_LOW                         0x1e20
 
1273
#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH                        0x1e24
 
1274
#define PCI_0_ACCESS_CONTROL_SIZE_2                             0x1e28
 
1275
#define PCI_0_ACCESS_CONTROL_BASE_3_LOW                         0x1e30
 
1276
#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH                        0x1e34
 
1277
#define PCI_0_ACCESS_CONTROL_SIZE_3                             0x1e38
 
1278
#define PCI_0_ACCESS_CONTROL_BASE_4_LOW                         0x1e40
 
1279
#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH                        0x1e44
 
1280
#define PCI_0_ACCESS_CONTROL_SIZE_4                             0x1e48
 
1281
#define PCI_0_ACCESS_CONTROL_BASE_5_LOW                         0x1e50
 
1282
#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH                        0x1e54
 
1283
#define PCI_0_ACCESS_CONTROL_SIZE_5                             0x1e58
 
1284
 
 
1285
#define PCI_1_ACCESS_CONTROL_BASE_0_LOW                         0x1e80
 
1286
#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH                        0x1e84
 
1287
#define PCI_1_ACCESS_CONTROL_SIZE_0                             0x1e88
 
1288
#define PCI_1_ACCESS_CONTROL_BASE_1_LOW                         0x1e90
 
1289
#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH                        0x1e94
 
1290
#define PCI_1_ACCESS_CONTROL_SIZE_1                             0x1e98
 
1291
#define PCI_1_ACCESS_CONTROL_BASE_2_LOW                         0x1ea0
 
1292
#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH                        0x1ea4
 
1293
#define PCI_1_ACCESS_CONTROL_SIZE_2                             0x1ea8
 
1294
#define PCI_1_ACCESS_CONTROL_BASE_3_LOW                         0x1eb0
 
1295
#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH                        0x1eb4
 
1296
#define PCI_1_ACCESS_CONTROL_SIZE_3                             0x1eb8
 
1297
#define PCI_1_ACCESS_CONTROL_BASE_4_LOW                         0x1ec0
 
1298
#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH                        0x1ec4
 
1299
#define PCI_1_ACCESS_CONTROL_SIZE_4                             0x1ec8
 
1300
#define PCI_1_ACCESS_CONTROL_BASE_5_LOW                         0x1ed0
 
1301
#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH                        0x1ed4
 
1302
#define PCI_1_ACCESS_CONTROL_SIZE_5                             0x1ed8
 
1303
 
 
1304
/****************************************/
 
1305
/*   PCI Configuration Access Registers */
 
1306
/****************************************/
 
1307
 
 
1308
#define PCI_0_CONFIG_ADDR                               0xcf8
 
1309
#define PCI_0_CONFIG_DATA_VIRTUAL_REG                           0xcfc
 
1310
#define PCI_1_CONFIG_ADDR                               0xc78
 
1311
#define PCI_1_CONFIG_DATA_VIRTUAL_REG                           0xc7c
 
1312
#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
 
1313
#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
 
1314
 
 
1315
/****************************************/
 
1316
/*   PCI Error Report Registers         */
 
1317
/****************************************/
 
1318
 
 
1319
#define PCI_0_SERR_MASK                                 0xc28
 
1320
#define PCI_1_SERR_MASK                                 0xca8
 
1321
#define PCI_0_ERROR_ADDR_LOW                                            0x1d40
 
1322
#define PCI_1_ERROR_ADDR_LOW                                            0x1dc0
 
1323
#define PCI_0_ERROR_ADDR_HIGH                                           0x1d44
 
1324
#define PCI_1_ERROR_ADDR_HIGH                                           0x1dc4
 
1325
#define PCI_0_ERROR_ATTRIBUTE                                           0x1d48
 
1326
#define PCI_1_ERROR_ATTRIBUTE                                           0x1dc8
 
1327
#define PCI_0_ERROR_COMMAND                                             0x1d50
 
1328
#define PCI_1_ERROR_COMMAND                                             0x1dd0
 
1329
#define PCI_0_ERROR_CAUSE                                               0x1d58
 
1330
#define PCI_1_ERROR_CAUSE                                               0x1dd8
 
1331
#define PCI_0_ERROR_MASK                                                0x1d5c
 
1332
#define PCI_1_ERROR_MASK                                                0x1ddc
 
1333
 
 
1334
/****************************************/
 
1335
/*   PCI Debug Registers                */
 
1336
/****************************************/
 
1337
 
 
1338
#define PCI_0_MMASK                                                     0X1D24
 
1339
#define PCI_1_MMASK                                                     0X1DA4
 
1340
 
 
1341
/*********************************************/
 
1342
/* PCI Configuration, Function 0, Registers  */
 
1343
/*********************************************/
 
1344
 
 
1345
#define PCI_DEVICE_AND_VENDOR_ID                        0x000
 
1346
#define PCI_STATUS_AND_COMMAND                  0x004
 
1347
#define PCI_CLASS_CODE_AND_REVISION_ID                  0x008
 
1348
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE           0x00C
 
1349
 
 
1350
#define PCI_SCS_0_BASE_ADDR_LOW                         0x010
 
1351
#define PCI_SCS_0_BASE_ADDR_HIGH                        0x014
 
1352
#define PCI_SCS_1_BASE_ADDR_LOW                         0x018
 
1353
#define PCI_SCS_1_BASE_ADDR_HIGH                        0x01C
 
1354
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW    0x020
 
1355
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH   0x024
 
1356
 /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID     0x02c1 */
 
1357
#define PCI_EXPANSION_ROM_BASE_ADDR_REG         0x030
 
1358
#define PCI_CAPABILTY_LIST_POINTER                              0x034
 
1359
#define PCI_INTERRUPT_PIN_AND_LINE                      0x03C
 
1360
       /* capability list */
 
1361
#define PCI_POWER_MANAGEMENT_CAPABILITY                         0x040
 
1362
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL      0x044
 
1363
#define PCI_VPD_ADDR                                                    0x048
 
1364
#define PCI_VPD_DATA                                                    0x04c
 
1365
#define PCI_MSI_MESSAGE_CONTROL                                 0x050
 
1366
#define PCI_MSI_MESSAGE_ADDR                                            0x054
 
1367
#define PCI_MSI_MESSAGE_UPPER_ADDR                              0x058
 
1368
#define PCI_MSI_MESSAGE_DATA                                            0x05c
 
1369
#define PCI_X_COMMAND                                                   0x060
 
1370
#define PCI_X_STATUS                                                    0x064
 
1371
#define PCI_COMPACT_PCI_HOT_SWAP                                0x068
 
1372
 
 
1373
/***********************************************/
 
1374
/*   PCI Configuration, Function 1, Registers  */
 
1375
/***********************************************/
 
1376
 
 
1377
#define PCI_SCS_2_BASE_ADDR_LOW                         0x110
 
1378
#define PCI_SCS_2_BASE_ADDR_HIGH                        0x114
 
1379
#define PCI_SCS_3_BASE_ADDR_LOW                         0x118
 
1380
#define PCI_SCS_3_BASE_ADDR_HIGH                        0x11c
 
1381
#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW                                 0x120
 
1382
#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH                                0x124
 
1383
 
 
1384
/***********************************************/
 
1385
/*  PCI Configuration, Function 2, Registers   */
 
1386
/***********************************************/
 
1387
 
 
1388
#define PCI_DEVCS_0_BASE_ADDR_LOW                       0x210
 
1389
#define PCI_DEVCS_0_BASE_ADDR_HIGH                      0x214
 
1390
#define PCI_DEVCS_1_BASE_ADDR_LOW                       0x218
 
1391
#define PCI_DEVCS_1_BASE_ADDR_HIGH                              0x21c
 
1392
#define PCI_DEVCS_2_BASE_ADDR_LOW                       0x220
 
1393
#define PCI_DEVCS_2_BASE_ADDR_HIGH                              0x224
 
1394
 
 
1395
/***********************************************/
 
1396
/*  PCI Configuration, Function 3, Registers   */
 
1397
/***********************************************/
 
1398
 
 
1399
#define PCI_DEVCS_3_BASE_ADDR_LOW                       0x310
 
1400
#define PCI_DEVCS_3_BASE_ADDR_HIGH                      0x314
 
1401
#define PCI_BOOT_CS_BASE_ADDR_LOW                       0x318
 
1402
#define PCI_BOOT_CS_BASE_ADDR_HIGH                              0x31c
 
1403
#define PCI_CPU_BASE_ADDR_LOW                           0x220
 
1404
#define PCI_CPU_BASE_ADDR_HIGH                          0x224
 
1405
 
 
1406
/***********************************************/
 
1407
/*  PCI Configuration, Function 4, Registers   */
 
1408
/***********************************************/
 
1409
 
 
1410
#define PCI_P2P_MEM0_BASE_ADDR_LOW                      0x410
 
1411
#define PCI_P2P_MEM0_BASE_ADDR_HIGH                     0x414
 
1412
#define PCI_P2P_MEM1_BASE_ADDR_LOW                      0x418
 
1413
#define PCI_P2P_MEM1_BASE_ADDR_HIGH                     0x41c
 
1414
#define PCI_P2P_I_O_BASE_ADDR                                           0x420
 
1415
#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR            0x424
 
1416
 
 
1417
/****************************** MV64360 and MV64460 PCI End ***************************/
 
1418
/****************************************/
 
1419
/* I20 Support registers                                */
 
1420
/****************************************/
 
1421
 
 
1422
#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE              0x010
 
1423
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE              0x014
 
1424
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE             0x018
 
1425
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE             0x01C
 
1426
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE              0x020
 
1427
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE       0x024
 
1428
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE        0x028
 
1429
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE             0x02C
 
1430
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE      0x030
 
1431
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE       0x034
 
1432
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE    0x040
 
1433
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   0x044
 
1434
#define QUEUE_CONTROL_REGISTER_PCI_SIDE                 0x050
 
1435
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE            0x054
 
1436
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE     0x060
 
1437
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE     0x064
 
1438
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE     0x068
 
1439
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE     0x06C
 
1440
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE    0x070
 
1441
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE    0x074
 
1442
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE    0x078
 
1443
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE    0x07C
 
1444
 
 
1445
#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE              0x1C10
 
1446
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE              0x1C14
 
1447
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE             0x1C18
 
1448
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE             0x1C1C
 
1449
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE              0x1C20
 
1450
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE       0x1C24
 
1451
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE        0x1C28
 
1452
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE             0x1C2C
 
1453
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE      0x1C30
 
1454
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE       0x1C34
 
1455
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE            0x1C40
 
1456
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE           0x1C44
 
1457
#define QUEUE_CONTROL_REGISTER_CPU_SIDE                         0x1C50
 
1458
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE                    0x1C54
 
1459
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE             0x1C60
 
1460
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE             0x1C64
 
1461
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE             0x1C68
 
1462
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE             0x1C6C
 
1463
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE            0x1C70
 
1464
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE            0x1C74
 
1465
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE            0x1C78
 
1466
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE            0x1C7C
 
1467
 
 
1468
 
 
1469
/****************************************/
 
1470
/* Messaging Unit Registers (I20)       */
 
1471
/****************************************/
 
1472
 
 
1473
#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE                     0x010
 
1474
#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE                             0x014
 
1475
#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE                            0x018
 
1476
#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE                            0x01C
 
1477
#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE                             0x020
 
1478
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE              0x024
 
1479
#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE                       0x028
 
1480
#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE                            0x02C
 
1481
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE             0x030
 
1482
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE              0x034
 
1483
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE           0x040
 
1484
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE          0x044
 
1485
#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE                        0x050
 
1486
#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE                      0x054
 
1487
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE            0x060
 
1488
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE            0x064
 
1489
#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE            0x068
 
1490
#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE            0x06C
 
1491
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE           0x070
 
1492
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE           0x074
 
1493
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE           0x0F8
 
1494
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE           0x0FC
 
1495
 
 
1496
#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE                     0x090
 
1497
#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE                             0x094
 
1498
#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE                            0x098
 
1499
#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE                            0x09C
 
1500
#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE                             0x0A0
 
1501
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE              0x0A4
 
1502
#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE                       0x0A8
 
1503
#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE                            0x0AC
 
1504
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE             0x0B0
 
1505
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE              0x0B4
 
1506
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE           0x0C0
 
1507
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE          0x0C4
 
1508
#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE                        0x0D0
 
1509
#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE                      0x0D4
 
1510
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE            0x0E0
 
1511
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE            0x0E4
 
1512
#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE            0x0E8
 
1513
#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE            0x0EC
 
1514
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE           0x0F0
 
1515
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE           0x0F4
 
1516
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE           0x078
 
1517
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE           0x07C
 
1518
 
 
1519
#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE                      0x1C10
 
1520
#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE                              0x1C14
 
1521
#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE                             0x1C18
 
1522
#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE                             0x1C1C
 
1523
#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE                              0x1C20
 
1524
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE                       0x1C24
 
1525
#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE                        0x1C28
 
1526
#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE                             0x1C2C
 
1527
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE              0x1C30
 
1528
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE               0x1C34
 
1529
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE            0x1C40
 
1530
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE           0x1C44
 
1531
#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE                         0x1C50
 
1532
#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE                               0x1C54
 
1533
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE             0x1C60
 
1534
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE             0x1C64
 
1535
#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE             0x1C68
 
1536
#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE             0x1C6C
 
1537
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE            0x1C70
 
1538
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE            0x1C74
 
1539
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE            0x1CF8
 
1540
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE            0x1CFC
 
1541
#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE                      0x1C90
 
1542
#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE                              0x1C94
 
1543
#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE                             0x1C98
 
1544
#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE                             0x1C9C
 
1545
#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE                              0x1CA0
 
1546
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE                       0x1CA4
 
1547
#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE                        0x1CA8
 
1548
#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE                             0x1CAC
 
1549
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE              0x1CB0
 
1550
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE               0x1CB4
 
1551
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE            0x1CC0
 
1552
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE           0x1CC4
 
1553
#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE                         0x1CD0
 
1554
#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE                               0x1CD4
 
1555
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE             0x1CE0
 
1556
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE             0x1CE4
 
1557
#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE             0x1CE8
 
1558
#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE             0x1CEC
 
1559
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE            0x1CF0
 
1560
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE            0x1CF4
 
1561
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE            0x1C78
 
1562
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE            0x1C7C
 
1563
 
 
1564
 
 
1565
/****************************************/
 
1566
/* Communication Unit Registers         */
 
1567
/****************************************/
 
1568
/*
 
1569
#define ETHERNET_0_ADDRESS_CONTROL_LOW                                          0xf200
 
1570
#define ETHERNET_0_ADDRESS_CONTROL_HIGH                     0xf204
 
1571
#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf208
 
1572
#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf20c
 
1573
#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf210
 
1574
#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf214
 
1575
#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS              0xf218
 
1576
#define ETHERNET_1_ADDRESS_CONTROL_LOW                      0xf220
 
1577
#define ETHERNET_1_ADDRESS_CONTROL_HIGH                     0xf224
 
1578
#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf228
 
1579
#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf22c
 
1580
#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf230
 
1581
#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf234
 
1582
#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS              0xf238
 
1583
#define ETHERNET_2_ADDRESS_CONTROL_LOW                      0xf240
 
1584
#define ETHERNET_2_ADDRESS_CONTROL_HIGH                     0xf244
 
1585
#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf248
 
1586
#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf24c
 
1587
#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf250
 
1588
#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf254
 
1589
#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS              0xf258
 
1590
 */
 
1591
#define MPSC_0_ADDRESS_CONTROL_LOW                          0xf280
 
1592
#define MPSC_0_ADDRESS_CONTROL_HIGH                         0xf284
 
1593
#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf288
 
1594
#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf28c
 
1595
#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf290
 
1596
#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf294
 
1597
#define MPSC_1_ADDRESS_CONTROL_LOW                          0xf2c0
 
1598
#define MPSC_1_ADDRESS_CONTROL_HIGH                         0xf2c4
 
1599
#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf2c8
 
1600
#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf2cc
 
1601
#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf2d0
 
1602
#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf2d4
 
1603
 /*#define SERIAL_INIT_PCI_HIGH_ADDRESS                        0xf3201 */
 
1604
#define COMM_UNIT_ARBITER_CONTROL                           0xf300
 
1605
#define COMM_UNIT_CROSS_BAR_TIMEOUT                         0xf304
 
1606
#define COMM_UNIT_INTERRUPT_CAUSE                           0xf310
 
1607
#define COMM_UNIT_INTERRUPT_MASK                            0xf314
 
1608
#define COMM_UNIT_ERROR_ADDRESS                             0xf314
 
1609
/****************************************/
 
1610
/*    Serial Initialization registers   */
 
1611
/****************************************/
 
1612
 
 
1613
 /*#define SERIAL_INIT_LAST_DATA                                        0xf3241 */
 
1614
 /*#define SERIAL_INIT_STATUS_AND_CONTROL                       0xf3281 */
 
1615
#define SERIAL_INIT_LAST_DATA                                           0xf324
 
1616
#define SERIAL_INIT_CONTROL                                             0xf328
 
1617
#define SERIAL_INIT_STATUS                                              0xf32c
 
1618
 
 
1619
 
 
1620
/****************************************/
 
1621
/*        Ethernet Unit Registers               */
 
1622
/****************************************/
 
1623
 
 
1624
#define ETH_PHY_ADDR_REG                        0x2000
 
1625
#define ETH_SMI_REG                                     0x2004
 
1626
#define ETH_UNIT_DEFAULT_ADDR_REG               0x2008
 
1627
#define ETH_UNIT_DEFAULTID_REG                  0x200c
 
1628
#define ETH_UNIT_INTERRUPT_CAUSE_REG    0x2080
 
1629
#define ETH_UNIT_INTERRUPT_MASK_REG     0x2084
 
1630
#define ETH_UNIT_INTERNAL_USE_REG               0x24fc
 
1631
#define ETH_UNIT_ERROR_ADDR_REG                 0x2094
 
1632
#define ETH_BAR_0                                       0x2200
 
1633
#define ETH_BAR_1                                       0x2208
 
1634
#define ETH_BAR_2                                       0x2210
 
1635
#define ETH_BAR_3                                       0x2218
 
1636
#define ETH_BAR_4                                       0x2220
 
1637
#define ETH_BAR_5                                       0x2228
 
1638
#define ETH_SIZE_REG_0                          0x2204
 
1639
#define ETH_SIZE_REG_1                          0x220c
 
1640
#define ETH_SIZE_REG_2                          0x2214
 
1641
#define ETH_SIZE_REG_3                          0x221c
 
1642
#define ETH_SIZE_REG_4                          0x2224
 
1643
#define ETH_SIZE_REG_5                                  0x222c
 
1644
#define ETH_HEADERS_RETARGET_BASE_REG                   0x2230
 
1645
#define ETH_HEADERS_RETARGET_CONTROL_REG        0x2234
 
1646
#define ETH_HIGH_ADDR_REMAP_REG_0               0x2280
 
1647
#define ETH_HIGH_ADDR_REMAP_REG_1               0x2284
 
1648
#define ETH_HIGH_ADDR_REMAP_REG_2               0x2288
 
1649
#define ETH_HIGH_ADDR_REMAP_REG_3                       0x228c
 
1650
#define ETH_BASE_ADDR_ENABLE_REG                        0x2290
 
1651
#define ETH_ACCESS_PROTECTION_REG(port)                 (0x2294 + (port<<2))
 
1652
#define ETH_MIB_COUNTERS_BASE(port)                     (0x3000 + (port<<7))
 
1653
#define ETH_PORT_CONFIG_REG(port)                               (0x2400 + (port<<10))
 
1654
#define ETH_PORT_CONFIG_EXTEND_REG(port)                (0x2404 + (port<<10))
 
1655
#define ETH_MII_SERIAL_PARAMETRS_REG(port)              (0x2408 + (port<<10))
 
1656
#define ETH_GMII_SERIAL_PARAMETRS_REG(port)             (0x240c + (port<<10))
 
1657
#define ETH_VLAN_ETHERTYPE_REG(port)                    (0x2410 + (port<<10))
 
1658
#define ETH_MAC_ADDR_LOW(port)                                  (0x2414 + (port<<10))
 
1659
#define ETH_MAC_ADDR_HIGH(port)                                 (0x2418 + (port<<10))
 
1660
#define ETH_SDMA_CONFIG_REG(port)                               (0x241c + (port<<10))
 
1661
#define ETH_DSCP_0(port)                                        (0x2420 + (port<<10))
 
1662
#define ETH_DSCP_1(port)                                        (0x2424 + (port<<10))
 
1663
#define ETH_DSCP_2(port)                                        (0x2428 + (port<<10))
 
1664
#define ETH_DSCP_3(port)                                        (0x242c + (port<<10))
 
1665
#define ETH_DSCP_4(port)                                        (0x2430 + (port<<10))
 
1666
#define ETH_DSCP_5(port)                                        (0x2434 + (port<<10))
 
1667
#define ETH_DSCP_6(port)                                        (0x2438 + (port<<10))
 
1668
#define ETH_PORT_SERIAL_CONTROL_REG(port)               (0x243c + (port<<10))
 
1669
#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)         (0x2440 + (port<<10))
 
1670
#define ETH_PORT_STATUS_REG(port)                               (0x2444 + (port<<10))
 
1671
#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)    (0x2448 + (port<<10))
 
1672
#define ETH_TX_QUEUE_FIXED_PRIORITY(port)               (0x244c + (port<<10))
 
1673
#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)              (0x2450 + (port<<10))
 
1674
#define ETH_MAXIMUM_TRANSMIT_UNIT(port)                         (0x2458 + (port<<10))
 
1675
#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)                (0x245c + (port<<10))
 
1676
#define ETH_INTERRUPT_CAUSE_REG(port)                           (0x2460 + (port<<10))
 
1677
#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)                    (0x2464 + (port<<10))
 
1678
#define ETH_INTERRUPT_MASK_REG(port)                            (0x2468 + (port<<10))
 
1679
#define ETH_INTERRUPT_EXTEND_MASK_REG(port)                     (0x246c + (port<<10))
 
1680
#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)                  (0x2470 + (port<<10))
 
1681
#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)                  (0x2474 + (port<<10))
 
1682
#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)                     (0x247c + (port<<10))
 
1683
#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)                   (0x2484 + (port<<10)
 
1684
#define ETH_PORT_DEBUG_0_REG(port)                                      (0x248c + (port<<10))
 
1685
#define ETH_PORT_DEBUG_1_REG(port)                                      (0x2490 + (port<<10))
 
1686
#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)                  (0x2494 + (port<<10))
 
1687
#define ETH_INTERNAL_USE_REG(port)                                      (0x24fc + (port<<10))
 
1688
#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)                     (0x2680 + (port<<10))
 
1689
#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)                    (0x2684 + (port<<10))
 
1690
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)                   (0x260c + (port<<10))
 
1691
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)                   (0x261c + (port<<10))
 
1692
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)                   (0x262c + (port<<10))
 
1693
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)                   (0x263c + (port<<10))
 
1694
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)                   (0x264c + (port<<10))
 
1695
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)                   (0x265c + (port<<10))
 
1696
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)                   (0x266c + (port<<10))
 
1697
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)                   (0x267c + (port<<10))
 
1698
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)                   (0x26c0 + (port<<10))
 
1699
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)                   (0x26c4 + (port<<10))
 
1700
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)                   (0x26c8 + (port<<10))
 
1701
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)                   (0x26cc + (port<<10))
 
1702
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)                   (0x26d0 + (port<<10))
 
1703
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)                   (0x26d4 + (port<<10))
 
1704
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)                   (0x26d8 + (port<<10))
 
1705
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)                   (0x26dc + (port<<10))
 
1706
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)                 (0x2700 + (port<<10))
 
1707
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)                 (0x2710 + (port<<10))
 
1708
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)                 (0x2720 + (port<<10))
 
1709
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)                 (0x2730 + (port<<10))
 
1710
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)                 (0x2740 + (port<<10))
 
1711
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)                 (0x2750 + (port<<10))
 
1712
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)                 (0x2760 + (port<<10))
 
1713
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)                 (0x2770 + (port<<10))
 
1714
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)                (0x2704 + (port<<10))
 
1715
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)                (0x2714 + (port<<10))
 
1716
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)                (0x2724 + (port<<10))
 
1717
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)                (0x2734 + (port<<10))
 
1718
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)                (0x2744 + (port<<10))
 
1719
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)                (0x2754 + (port<<10))
 
1720
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)                (0x2764 + (port<<10))
 
1721
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)                (0x2774 + (port<<10))
 
1722
#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)                     (0x2708 + (port<<10))
 
1723
#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)                     (0x2718 + (port<<10))
 
1724
#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)                     (0x2728 + (port<<10))
 
1725
#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)                     (0x2738 + (port<<10))
 
1726
#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)                     (0x2748 + (port<<10))
 
1727
#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)                     (0x2758 + (port<<10))
 
1728
#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)                     (0x2768 + (port<<10))
 
1729
#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)                     (0x2778 + (port<<10))
 
1730
#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)                    (0x2780 + (port<<10))
 
1731
#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)        (0x3400 + (port<<10))
 
1732
#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)          (0x3500 + (port<<10))
 
1733
#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)                  (0x3600 + (port<<10))
 
1734
 
 
1735
/****************************************/
 
1736
/* Cunit Debug  (for internal use)     */
 
1737
/****************************************/
 
1738
 
 
1739
#define CUNIT_ADDRESS                                       0xf340
 
1740
#define CUNIT_COMMAND_AND_ID                                0xf344
 
1741
#define CUNIT_WRITE_DATA_LOW                                0xf348
 
1742
#define CUNIT_WRITE_DATA_HIGH                               0xf34c
 
1743
#define CUNIT_WRITE_BYTE_ENABLE                             0xf358
 
1744
#define CUNIT_READ_DATA_LOW                                 0xf350
 
1745
#define CUNIT_READ_DATA_HIGH                                0xf354
 
1746
#define CUNIT_READ_ID                                       0xf35c
 
1747
 
 
1748
/****************************************/
 
1749
/* Fast Ethernet Unit Registers         */
 
1750
/****************************************/
 
1751
 
 
1752
/****************************************/
 
1753
/*        Ethernet Unit Registers               */
 
1754
/****************************************/
 
1755
 
 
1756
#define ETH_PHY_ADDR_REG                                0x2000
 
1757
#define ETH_SMI_REG                                             0x2004
 
1758
#define ETH_UNIT_DEFAULT_ADDR_REG                       0x2008
 
1759
#define ETH_UNIT_DEFAULTID_REG                          0x200c
 
1760
#define ETH_UNIT_INTERRUPT_CAUSE_REG                    0x2080
 
1761
#define ETH_UNIT_INTERRUPT_MASK_REG             0x2084
 
1762
#define ETH_UNIT_INTERNAL_USE_REG                       0x24fc
 
1763
#define ETH_UNIT_ERROR_ADDR_REG                         0x2094
 
1764
#define ETH_BAR_0                                               0x2200
 
1765
#define ETH_BAR_1                                               0x2208
 
1766
#define ETH_BAR_2                                               0x2210
 
1767
#define ETH_BAR_3                                               0x2218
 
1768
#define ETH_BAR_4                                               0x2220
 
1769
#define ETH_BAR_5                                               0x2228
 
1770
#define ETH_SIZE_REG_0                                          0x2204
 
1771
#define ETH_SIZE_REG_1                                          0x220c
 
1772
#define ETH_SIZE_REG_2                                          0x2214
 
1773
#define ETH_SIZE_REG_3                                          0x221c
 
1774
#define ETH_SIZE_REG_4                                          0x2224
 
1775
#define ETH_SIZE_REG_5                                          0x222c
 
1776
#define ETH_HEADERS_RETARGET_BASE_REG                   0x2230
 
1777
#define ETH_HEADERS_RETARGET_CONTROL_REG        0x2234
 
1778
#define ETH_HIGH_ADDR_REMAP_REG_0                       0x2280
 
1779
#define ETH_HIGH_ADDR_REMAP_REG_1               0x2284
 
1780
#define ETH_HIGH_ADDR_REMAP_REG_2               0x2288
 
1781
#define ETH_HIGH_ADDR_REMAP_REG_3                       0x228c
 
1782
#define ETH_BASE_ADDR_ENABLE_REG                        0x2290
 
1783
#define ETH_ACCESS_PROTECTION_REG(port)                 (0x2294 + (port<<2))
 
1784
#define ETH_MIB_COUNTERS_BASE(port)                     (0x3000 + (port<<7))
 
1785
#define ETH_PORT_CONFIG_REG(port)                       (0x2400 + (port<<10))
 
1786
#define ETH_PORT_CONFIG_EXTEND_REG(port)                (0x2404 + (port<<10))
 
1787
#define ETH_MII_SERIAL_PARAMETRS_REG(port)              (0x2408 + (port<<10))
 
1788
#define ETH_GMII_SERIAL_PARAMETRS_REG(port)             (0x240c + (port<<10))
 
1789
#define ETH_VLAN_ETHERTYPE_REG(port)                    (0x2410 + (port<<10))
 
1790
#define ETH_MAC_ADDR_LOW(port)                                  (0x2414 + (port<<10))
 
1791
#define ETH_MAC_ADDR_HIGH(port)                                 (0x2418 + (port<<10))
 
1792
#define ETH_SDMA_CONFIG_REG(port)                       (0x241c + (port<<10))
 
1793
#define ETH_DSCP_0(port)                                        (0x2420 + (port<<10))
 
1794
#define ETH_DSCP_1(port)                                        (0x2424 + (port<<10))
 
1795
#define ETH_DSCP_2(port)                                        (0x2428 + (port<<10))
 
1796
#define ETH_DSCP_3(port)                                        (0x242c + (port<<10))
 
1797
#define ETH_DSCP_4(port)                                        (0x2430 + (port<<10))
 
1798
#define ETH_DSCP_5(port)                                        (0x2434 + (port<<10))
 
1799
#define ETH_DSCP_6(port)                                        (0x2438 + (port<<10))
 
1800
#define ETH_PORT_SERIAL_CONTROL_REG(port)       (0x243c + (port<<10))
 
1801
#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)         (0x2440 + (port<<10))
 
1802
#define ETH_PORT_STATUS_REG(port)                               (0x2444 + (port<<10))
 
1803
#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)    (0x2448 + (port<<10))
 
1804
#define ETH_TX_QUEUE_FIXED_PRIORITY(port)               (0x244c + (port<<10))
 
1805
#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)         (0x2450 + (port<<10))
 
1806
#define ETH_MAXIMUM_TRANSMIT_UNIT(port)                 (0x2458 + (port<<10))
 
1807
#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)           (0x245c + (port<<10))
 
1808
#define ETH_INTERRUPT_CAUSE_REG(port)                   (0x2460 + (port<<10))
 
1809
#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)            (0x2464 + (port<<10))
 
1810
#define ETH_INTERRUPT_MASK_REG(port)                    (0x2468 + (port<<10))
 
1811
#define ETH_INTERRUPT_EXTEND_MASK_REG(port)             (0x246c + (port<<10))
 
1812
#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)  (0x2470 + (port<<10))
 
1813
#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)  (0x2474 + (port<<10))
 
1814
#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)             (0x247c + (port<<10))
 
1815
#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)   (0x2484 + (port<<10)
 
1816
#define ETH_PORT_DEBUG_0_REG(port)                              (0x248c + (port<<10))
 
1817
#define ETH_PORT_DEBUG_1_REG(port)                              (0x2490 + (port<<10))
 
1818
#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)  (0x2494 + (port<<10))
 
1819
#define ETH_INTERNAL_USE_REG(port)                              (0x24fc + (port<<10))
 
1820
#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)     (0x2680 + (port<<10))
 
1821
#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)            (0x2684 + (port<<10))
 
1822
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)           (0x260c + (port<<10))
 
1823
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)   (0x261c + (port<<10))
 
1824
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)           (0x262c + (port<<10))
 
1825
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)           (0x263c + (port<<10))
 
1826
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)           (0x264c + (port<<10))
 
1827
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)           (0x265c + (port<<10))
 
1828
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)           (0x266c + (port<<10))
 
1829
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)           (0x267c + (port<<10))
 
1830
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)   (0x26c0 + (port<<10))
 
1831
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)   (0x26c4 + (port<<10))
 
1832
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)   (0x26c8 + (port<<10))
 
1833
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)           (0x26cc + (port<<10))
 
1834
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)           (0x26d0 + (port<<10))
 
1835
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)           (0x26d4 + (port<<10))
 
1836
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)           (0x26d8 + (port<<10))
 
1837
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)           (0x26dc + (port<<10))
 
1838
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)            (0x2700 + (port<<10))
 
1839
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)            (0x2710 + (port<<10))
 
1840
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)            (0x2720 + (port<<10))
 
1841
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)            (0x2730 + (port<<10))
 
1842
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)            (0x2740 + (port<<10))
 
1843
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)            (0x2750 + (port<<10))
 
1844
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)            (0x2760 + (port<<10))
 
1845
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)            (0x2770 + (port<<10))
 
1846
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)           (0x2704 + (port<<10))
 
1847
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)           (0x2714 + (port<<10))
 
1848
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)           (0x2724 + (port<<10))
 
1849
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)           (0x2734 + (port<<10))
 
1850
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)           (0x2744 + (port<<10))
 
1851
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)           (0x2754 + (port<<10))
 
1852
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)           (0x2764 + (port<<10))
 
1853
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)           (0x2774 + (port<<10))
 
1854
#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)             (0x2708 + (port<<10))
 
1855
#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)             (0x2718 + (port<<10))
 
1856
#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)             (0x2728 + (port<<10))
 
1857
#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)             (0x2738 + (port<<10))
 
1858
#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)             (0x2748 + (port<<10))
 
1859
#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)             (0x2758 + (port<<10))
 
1860
#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)             (0x2768 + (port<<10))
 
1861
#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)             (0x2778 + (port<<10))
 
1862
#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)            (0x2780 + (port<<10))
 
1863
#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
 
1864
#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)     (0x3500 + (port<<10))
 
1865
#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)          (0x3600 + (port<<10))
 
1866
 
 
1867
 
 
1868
/* Ethernet GT64260 */
 
1869
/*
 
1870
#define ETHERNET_PHY_ADDRESS_REGISTER                                   0x2000
 
1871
#define ETHERNET_SMI_REGISTER                                                   0x2010
 
1872
*/
 
1873
/* Ethernet 0 */
 
1874
/*
 
1875
#define ETHERNET0_PORT_CONFIGURATION_REGISTER                           0x2400
 
1876
#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER            0x2408
 
1877
#define ETHERNET0_PORT_COMMAND_REGISTER                                 0x2410
 
1878
#define ETHERNET0_PORT_STATUS_REGISTER                                  0x2418
 
1879
#define ETHERNET0_SERIAL_PARAMETRS_REGISTER                             0x2420
 
1880
#define ETHERNET0_HASH_TABLE_POINTER_REGISTER                           0x2428
 
1881
#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW               0x2430
 
1882
#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH              0x2438
 
1883
#define ETHERNET0_SDMA_CONFIGURATION_REGISTER                   0x2440
 
1884
#define ETHERNET0_SDMA_COMMAND_REGISTER                                 0x2448
 
1885
#define ETHERNET0_INTERRUPT_CAUSE_REGISTER                              0x2450
 
1886
#define ETHERNET0_INTERRUPT_MASK_REGISTER                               0x2458
 
1887
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0                          0x2480
 
1888
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1                          0x2484
 
1889
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2                          0x2488
 
1890
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3                          0x248c
 
1891
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0                0x24a0
 
1892
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1                0x24a4
 
1893
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2                0x24a8
 
1894
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3                0x24ac
 
1895
#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0                0x24e0
 
1896
#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1                0x24e4
 
1897
#define ETHERNET0_MIB_COUNTER_BASE                                      0x2500
 
1898
*/
 
1899
/* Ethernet 1 */
 
1900
/*
 
1901
#define ETHERNET1_PORT_CONFIGURATION_REGISTER                           0x2800
 
1902
#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER            0x2808
 
1903
#define ETHERNET1_PORT_COMMAND_REGISTER                                 0x2810
 
1904
#define ETHERNET1_PORT_STATUS_REGISTER                                  0x2818
 
1905
#define ETHERNET1_SERIAL_PARAMETRS_REGISTER                             0x2820
 
1906
#define ETHERNET1_HASH_TABLE_POINTER_REGISTER                           0x2828
 
1907
#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW               0x2830
 
1908
#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH              0x2838
 
1909
#define ETHERNET1_SDMA_CONFIGURATION_REGISTER                   0x2840
 
1910
#define ETHERNET1_SDMA_COMMAND_REGISTER                                 0x2848
 
1911
#define ETHERNET1_INTERRUPT_CAUSE_REGISTER                              0x2850
 
1912
#define ETHERNET1_INTERRUPT_MASK_REGISTER                               0x2858
 
1913
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0                          0x2880
 
1914
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1                          0x2884
 
1915
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2                          0x2888
 
1916
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3                          0x288c
 
1917
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0                0x28a0
 
1918
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1                0x28a4
 
1919
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2                0x28a8
 
1920
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3                0x28ac
 
1921
#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0                0x28e0
 
1922
#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1                0x28e4
 
1923
#define ETHERNET1_MIB_COUNTER_BASE                                      0x2900
 
1924
*/
 
1925
/* Ethernet 2 */
 
1926
/*
 
1927
#define ETHERNET2_PORT_CONFIGURATION_REGISTER                           0x2c00
 
1928
#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER            0x2c08
 
1929
#define ETHERNET2_PORT_COMMAND_REGISTER                                 0x2c10
 
1930
#define ETHERNET2_PORT_STATUS_REGISTER                                  0x2c18
 
1931
#define ETHERNET2_SERIAL_PARAMETRS_REGISTER                             0x2c20
 
1932
#define ETHERNET2_HASH_TABLE_POINTER_REGISTER                           0x2c28
 
1933
#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW               0x2c30
 
1934
#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH              0x2c38
 
1935
#define ETHERNET2_SDMA_CONFIGURATION_REGISTER                   0x2c40
 
1936
#define ETHERNET2_SDMA_COMMAND_REGISTER                                 0x2c48
 
1937
#define ETHERNET2_INTERRUPT_CAUSE_REGISTER                              0x2c50
 
1938
#define ETHERNET2_INTERRUPT_MASK_REGISTER                               0x2c58
 
1939
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0                          0x2c80
 
1940
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1                          0x2c84
 
1941
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2                          0x2c88
 
1942
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3                          0x2c8c
 
1943
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0                0x2ca0
 
1944
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1                0x2ca4
 
1945
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2                0x2ca8
 
1946
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3                0x2cac
 
1947
#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0                0x2ce0
 
1948
#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1                0x2ce4
 
1949
#define ETHERNET2_MIB_COUNTER_BASE                                      0x2d00
 
1950
*/
 
1951
 
 
1952
/****************************************/
 
1953
/* SDMA Registers                       */
 
1954
/****************************************/
 
1955
 
 
1956
#define SDMA_GROUP_CONFIGURATION_REGISTER                       0xb1f0
 
1957
#define CHANNEL0_CONFIGURATION_REGISTER                         0x4000
 
1958
#define CHANNEL0_COMMAND_REGISTER                               0x4008
 
1959
#define CHANNEL0_RX_CMD_STATUS                                  0x4800
 
1960
#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES                 0x4804
 
1961
#define CHANNEL0_RX_BUFFER_POINTER                              0x4808
 
1962
#define CHANNEL0_RX_NEXT_POINTER                                0x480c
 
1963
#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER          0x4810
 
1964
#define CHANNEL0_TX_CMD_STATUS                                  0x4C00
 
1965
#define CHANNEL0_TX_PACKET_SIZE                                 0x4C04
 
1966
#define CHANNEL0_TX_BUFFER_POINTER                              0x4C08
 
1967
#define CHANNEL0_TX_NEXT_POINTER                                0x4C0c
 
1968
#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER          0x4c10
 
1969
#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER                    0x4c14
 
1970
/*
 
1971
#define CHANNEL1_CONFIGURATION_REGISTER                         0x5000
 
1972
#define CHANNEL1_COMMAND_REGISTER                               0x5008
 
1973
#define CHANNEL1_RX_CMD_STATUS                                  0x5800
 
1974
#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES                 0x5804
 
1975
#define CHANNEL1_RX_BUFFER_POINTER                              0x5808
 
1976
#define CHANNEL1_RX_NEXT_POINTER                                0x580c
 
1977
#define CHANNEL1_TX_CMD_STATUS                                  0x5C00
 
1978
#define CHANNEL1_TX_PACKET_SIZE                                 0x5C04
 
1979
#define CHANNEL1_TX_BUFFER_POINTER                              0x5C08
 
1980
#define CHANNEL1_TX_NEXT_POINTER                                0x5C0c
 
1981
#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER          0x5810
 
1982
#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER          0x5c10
 
1983
#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER                    0x5c14
 
1984
#define CHANNEL2_CONFIGURATION_REGISTER                         0x6000
 
1985
#define CHANNEL2_COMMAND_REGISTER                               0x6008
 
1986
#define CHANNEL2_RX_CMD_STATUS                                  0x6800
 
1987
#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES                 0x6804
 
1988
#define CHANNEL2_RX_BUFFER_POINTER                              0x6808
 
1989
#define CHANNEL2_RX_NEXT_POINTER                                0x680c
 
1990
#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER          0x6810
 
1991
#define CHANNEL2_TX_CMD_STATUS                                  0x6C00
 
1992
#define CHANNEL2_TX_PACKET_SIZE                                 0x6C04
 
1993
#define CHANNEL2_TX_BUFFER_POINTER                              0x6C08
 
1994
#define CHANNEL2_TX_NEXT_POINTER                                0x6C0c
 
1995
#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER          0x6810
 
1996
#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER                  0x6c10
 
1997
#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER                    0x6c14
 
1998
*/
 
1999
/* SDMA Interrupt */
 
2000
/*
 
2001
#define SDMA_CAUSE                                                      0xb820
 
2002
#define SDMA_MASK                                                       0xb8a0
 
2003
*/
 
2004
/***************************************/
 
2005
/*          SDMA Registers             */
 
2006
/***************************************/
 
2007
 
 
2008
#define SDMA_CONFIG_REG(channel)                                        (0x4000 + (channel<<13))
 
2009
#define SDMA_COMMAND_REG(channel)                                       (0x4008 + (channel<<13))
 
2010
#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)             (0x4810 + (channel<<13))
 
2011
#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)     (0x4c10 + (channel<<13))
 
2012
#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)       (0x4c14 + (channel<<13))
 
2013
 
 
2014
#define SDMA_CAUSE_REG                                                  0xb800
 
2015
#define SDMA_MASK_REG                                                   0xb880
 
2016
 
 
2017
/****************************************/
 
2018
/* Baude Rate Generators Registers      */
 
2019
/****************************************/
 
2020
 
 
2021
/* BRG 0 */
 
2022
#define BRG0_CONFIGURATION_REGISTER             0xb200
 
2023
#define BRG0_BAUDE_TUNING_REGISTER                       0xb204
 
2024
 
 
2025
/* BRG 1 */
 
2026
#define BRG1_CONFIGURATION_REGISTER                     0xb208
 
2027
#define BRG1_BAUDE_TUNING_REGISTER                       0xb20c
 
2028
 
 
2029
/* BRG 2 */
 
2030
#define BRG2_CONFIGURATION_REGISTER                     0xb210
 
2031
#define BRG2_BAUDE_TUNING_REGISTER                       0xb214
 
2032
 
 
2033
/* BRG Interrupts */
 
2034
#define BRG_CAUSE_REGISTER                                      0xb834
 
2035
#define BRG_MASK_REGISTER                                       0xb8b4
 
2036
#define BRG_CONFIG_REG(brg)                                     (0xb200 + (brg<<3))
 
2037
#define BRG_BAUDE_TUNING_REG(brg)                               (0xb208 + (brg<<3))
 
2038
#define BRG_CAUSE_REG                                           BRG_CAUSE_REGISTER  /*0xb8341 */
 
2039
#define BRG_MASK_REG                                            BRG_MASK_REGISTER  /*0xb8b41 */
 
2040
 
 
2041
/* MISC */
 
2042
 
 
2043
#define MAIN_ROUTING_REGISTER                                           0xb400
 
2044
#define RECEIVE_CLOCK_ROUTING_REGISTER                          0xb404
 
2045
#define TRANSMIT_CLOCK_ROUTING_REGISTER                         0xb408
 
2046
#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER        0xb40c
 
2047
 
 
2048
/****************************************/
 
2049
/*         Watchdog registers                   */
 
2050
/****************************************/
 
2051
#define WATCHDOG_CONFIGURATION_REGISTER                 0xb410
 
2052
#define WATCHDOG_VALUE_REGISTER                                 0xb414
 
2053
#define WATCHDOG_CONFIG_REG                                     WATCHDOG_CONFIGURATION_REGISTER  /*0xb4101 */
 
2054
#define WATCHDOG_VALUE_REG                                              WATCHDOG_VALUE_REGISTER  /*0xb4141 */
 
2055
 
 
2056
 
 
2057
/****************************************/
 
2058
/* Flex TDM Registers                   */
 
2059
/****************************************/
 
2060
 
 
2061
/* FTDM Port */
 
2062
 
 
2063
#define FLEXTDM_TRANSMIT_READ_POINTER                       0xa800
 
2064
#define FLEXTDM_RECEIVE_READ_POINTER                        0xa804
 
2065
#define FLEXTDM_CONFIGURATION_REGISTER                      0xa808
 
2066
#define FLEXTDM_AUX_CHANNELA_TX_REGISTER                    0xa80c
 
2067
#define FLEXTDM_AUX_CHANNELA_RX_REGISTER                    0xa810
 
2068
#define FLEXTDM_AUX_CHANNELB_TX_REGISTER                    0xa814
 
2069
#define FLEXTDM_AUX_CHANNELB_RX_REGISTER                    0xa818
 
2070
 
 
2071
/* FTDM Interrupts */
 
2072
 
 
2073
#define FTDM_CAUSE_REGISTER                                 0xb830
 
2074
#define FTDM_MASK_REGISTER                                  0xb8b0
 
2075
 
 
2076
 
 
2077
/****************************************/
 
2078
/* GPP Interface Registers              */
 
2079
/****************************************/
 
2080
 
 
2081
#define GPP_IO_CONTROL                                          0xf100
 
2082
#define GPP_LEVEL_CONTROL                                       0xf110
 
2083
#define GPP_VALUE                                               0xf104
 
2084
#define GPP_INTERRUPT_CAUSE                                     0xf108
 
2085
#define GPP_INTERRUPT_MASK                                      0xf10c
 
2086
#define GPP_INTERRUPT_MASK0                                     GPP_INTERRUPT_MASK  /* 0xf10c1 */
 
2087
#define GPP_INTERRUPT_MASK1                                     0xf114
 
2088
#define GPP_VALUE_SET                                           0xf118
 
2089
#define GPP_VALUE_CLEAR                                         0xf11c
 
2090
 
 
2091
/****************************************/
 
2092
/*      MPP Interface Registers         */
 
2093
/****************************************/
 
2094
#define MPP_CONTROL0                                            0xf000
 
2095
#define MPP_CONTROL1                                            0xf004
 
2096
#define MPP_CONTROL2                                            0xf008
 
2097
#define MPP_CONTROL3                                            0xf00c
 
2098
#define DEBUG_PORT_MULTIPLEX                                    0xf014
 
2099
 /*#define SERIAL_PORT_MULTIPLEX                               0xf0101 */
 
2100
 
 
2101
/****************************************/
 
2102
/* Interrupt Controller Registers       */
 
2103
/****************************************/
 
2104
 
 
2105
/****************************************/
 
2106
/* Interrupts                                                   */
 
2107
/****************************************/
 
2108
/****************************************/
 
2109
/* Interrupts (checked I.A. 14.10.02)                           */
 
2110
/****************************************/
 
2111
 
 
2112
#define LOW_INTERRUPT_CAUSE_REGISTER                    0x004  /* gt64260: 0xc181 */
 
2113
#define HIGH_INTERRUPT_CAUSE_REGISTER                   0x00c  /* gt64260: 0xc681 */
 
2114
#define CPU_INTERRUPT_MASK_REGISTER_LOW         0x014  /* gt64260: 0xc1c1 */
 
2115
#define CPU_INTERRUPT_MASK_REGISTER_HIGH                0x01c  /* gt64260: 0xc6c1 */
 
2116
#define CPU_SELECT_CAUSE_REGISTER                       0x024  /* gt64260: 0xc701 */
 
2117
#define CPU_INTERRUPT_1_MASK_REGISTER_LOW               0x034  /* new in the MV64360 and MV64460 */
 
2118
#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH              0x03c  /* new in the MV64360 and MV64460 */
 
2119
#define CPU_SELECT_1_CAUSE_REGISTER                     0x044  /* new in the MV64360 and MV64460 */
 
2120
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW  0x054  /* gt64260: 0xc241 */
 
2121
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c  /* gt64260: 0xc641 */
 
2122
#define PCI_0SELECT_CAUSE                                               0x064  /* gt64260: 0xc741 */
 
2123
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW  0x074  /* gt64260: 0xca41 */
 
2124
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c  /* gt64260: 0xce41 */
 
2125
#define PCI_1SELECT_CAUSE                                               0x084  /* gt64260: 0xcf41 */
 
2126
/*#define CPU_INT_0_MASK                                                0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */
 
2127
/*#define CPU_INT_1_MASK                                                0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */
 
2128
/*#define CPU_INT_2_MASK                                                0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */
 
2129
/*#define CPU_INT_3_MASK                                                0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */
 
2130
 
 
2131
#define MAIN_INTERRUPT_CAUSE_LOW                                LOW_INTERRUPT_CAUSE_REGISTER  /* 0x0041 */
 
2132
#define MAIN_INTERRUPT_CAUSE_HIGH                               HIGH_INTERRUPT_CAUSE_REGISTER  /* 0x00c1 */
 
2133
#define CPU_INTERRUPT0_MASK_LOW                         CPU_INTERRUPT_MASK_REGISTER_LOW  /* 0x0141 */
 
2134
#define CPU_INTERRUPT0_MASK_HIGH                        CPU_INTERRUPT_MASK_REGISTER_HIGH  /*0x01c1 */
 
2135
#define CPU_INTERRUPT0_SELECT_CAUSE                     CPU_SELECT_CAUSE_REGISTER  /* 0x0241 */
 
2136
#define CPU_INTERRUPT1_MASK_LOW                         CPU_INTERRUPT_1_MASK_REGISTER_LOW  /* 0x0341 */
 
2137
#define CPU_INTERRUPT1_MASK_HIGH                        CPU_INTERRUPT_1_MASK_REGISTER_HIGH  /* 0x03c1 */
 
2138
#define CPU_INTERRUPT1_SELECT_CAUSE                     CPU_SELECT_1_CAUSE_REGISTER  /* 0x0441 */
 
2139
#define INTERRUPT0_MASK_0_LOW                           PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */
 
2140
#define INTERRUPT0_MASK_0_HIGH                                  PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH  /* 0x05c1 */
 
2141
#define INTERRUPT0_SELECT_CAUSE                         PCI_0SELECT_CAUSE  /* 0x0641 */
 
2142
#define INTERRUPT1_MASK_0_LOW                                   PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW  /* 0x0741 */
 
2143
#define INTERRUPT1_MASK_0_HIGH                                  PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH  /* 0x07c1 */
 
2144
#define INTERRUPT1_SELECT_CAUSE                         PCI_1SELECT_CAUSE  /* 0x0841 */
 
2145
 
 
2146
/****************************************/
 
2147
/* I2C Registers                        */
 
2148
/****************************************/
 
2149
 
 
2150
#define I2C_SLAVE_ADDRESS                                       0xc000
 
2151
#define I2C_EXTENDED_SLAVE_ADDRESS                      0xc040
 
2152
#define I2C_DATA                                                0xc004
 
2153
#define I2C_CONTROL                                             0xc008
 
2154
#define I2C_STATUS_BAUDE_RATE                                   0xc00C
 
2155
#define I2C_SOFT_RESET                                          0xc01c
 
2156
#define I2C_SLAVE_ADDR                                          I2C_SLAVE_ADDRESS  /* 0xc0001 */
 
2157
#define I2C_EXTENDED_SLAVE_ADDR                                 I2C_EXTENDED_SLAVE_ADDRESS  /*0xc0101 */
 
2158
 
 
2159
/****************************************/
 
2160
/* MPSC Registers                       */
 
2161
/****************************************/
 
2162
 
 
2163
        /*  MPSCs Clocks Routing Registers  */
 
2164
 
 
2165
#define MPSC_ROUTING_REG                                        0xb400
 
2166
#define MPSC_RX_CLOCK_ROUTING_REG                       0xb404
 
2167
#define MPSC_TX_CLOCK_ROUTING_REG                       0xb408
 
2168
 
 
2169
        /*  MPSCs Interrupts Registers    */
 
2170
 
 
2171
#define MPSC_CAUSE_REG(port)                                    (0xb804 + (port<<3))
 
2172
#define MPSC_MASK_REG(port)                                     (0xb884 + (port<<3))
 
2173
 
 
2174
#define MPSC_MAIN_CONFIG_LOW(port)                      (0x8000 + (port<<12))
 
2175
#define MPSC_MAIN_CONFIG_HIGH(port)                     (0x8004 + (port<<12))
 
2176
#define MPSC_PROTOCOL_CONFIG(port)                      (0x8008 + (port<<12))
 
2177
#define MPSC_CHANNEL_REG1(port)                                 (0x800c + (port<<12))
 
2178
#define MPSC_CHANNEL_REG2(port)                                 (0x8010 + (port<<12))
 
2179
#define MPSC_CHANNEL_REG3(port)                                 (0x8014 + (port<<12))
 
2180
#define MPSC_CHANNEL_REG4(port)                                 (0x8018 + (port<<12))
 
2181
#define MPSC_CHANNEL_REG5(port)                                 (0x801c + (port<<12))
 
2182
#define MPSC_CHANNEL_REG6(port)                                 (0x8020 + (port<<12))
 
2183
#define MPSC_CHANNEL_REG7(port)                                 (0x8024 + (port<<12))
 
2184
#define MPSC_CHANNEL_REG8(port)                                 (0x8028 + (port<<12))
 
2185
#define MPSC_CHANNEL_REG9(port)                                 (0x802c + (port<<12))
 
2186
#define MPSC_CHANNEL_REG10(port)                                (0x8030 + (port<<12))
 
2187
 
 
2188
 
 
2189
/* MPSC0  */
 
2190
 
 
2191
#define MPSC0_MAIN_CONFIGURATION_LOW                        0x8000
 
2192
#define MPSC0_MAIN_CONFIGURATION_HIGH                       0x8004
 
2193
#define MPSC0_PROTOCOL_CONFIGURATION                        0x8008
 
2194
#define CHANNEL0_REGISTER1                                  0x800c
 
2195
#define CHANNEL0_REGISTER2                                  0x8010
 
2196
#define CHANNEL0_REGISTER3                                  0x8014
 
2197
#define CHANNEL0_REGISTER4                                  0x8018
 
2198
#define CHANNEL0_REGISTER5                                  0x801c
 
2199
#define CHANNEL0_REGISTER6                                  0x8020
 
2200
#define CHANNEL0_REGISTER7                                  0x8024
 
2201
#define CHANNEL0_REGISTER8                                  0x8028
 
2202
#define CHANNEL0_REGISTER9                                  0x802c
 
2203
#define CHANNEL0_REGISTER10                                 0x8030
 
2204
#define CHANNEL0_REGISTER11                                 0x8034
 
2205
 
 
2206
/* MPSC1  */
 
2207
 
 
2208
#define MPSC1_MAIN_CONFIGURATION_LOW                        0x8840
 
2209
#define MPSC1_MAIN_CONFIGURATION_HIGH                       0x8844
 
2210
#define MPSC1_PROTOCOL_CONFIGURATION                        0x8848
 
2211
#define CHANNEL1_REGISTER1                                  0x884c
 
2212
#define CHANNEL1_REGISTER2                                  0x8850
 
2213
#define CHANNEL1_REGISTER3                                  0x8854
 
2214
#define CHANNEL1_REGISTER4                                  0x8858
 
2215
#define CHANNEL1_REGISTER5                                  0x885c
 
2216
#define CHANNEL1_REGISTER6                                  0x8860
 
2217
#define CHANNEL1_REGISTER7                                  0x8864
 
2218
#define CHANNEL1_REGISTER8                                  0x8868
 
2219
#define CHANNEL1_REGISTER9                                  0x886c
 
2220
#define CHANNEL1_REGISTER10                                 0x8870
 
2221
#define CHANNEL1_REGISTER11                                 0x8874
 
2222
 
 
2223
/* MPSC2  */
 
2224
 
 
2225
#define MPSC2_MAIN_CONFIGURATION_LOW                        0x9040
 
2226
#define MPSC2_MAIN_CONFIGURATION_HIGH                       0x9044
 
2227
#define MPSC2_PROTOCOL_CONFIGURATION                        0x9048
 
2228
#define CHANNEL2_REGISTER1                                  0x904c
 
2229
#define CHANNEL2_REGISTER2                                  0x9050
 
2230
#define CHANNEL2_REGISTER3                                  0x9054
 
2231
#define CHANNEL2_REGISTER4                                  0x9058
 
2232
#define CHANNEL2_REGISTER5                                  0x905c
 
2233
#define CHANNEL2_REGISTER6                                  0x9060
 
2234
#define CHANNEL2_REGISTER7                                  0x9064
 
2235
#define CHANNEL2_REGISTER8                                  0x9068
 
2236
#define CHANNEL2_REGISTER9                                  0x906c
 
2237
#define CHANNEL2_REGISTER10                                 0x9070
 
2238
#define CHANNEL2_REGISTER11                                 0x9074
 
2239
 
 
2240
/* MPSCs Interupts  */
 
2241
 
 
2242
#define MPSC0_CAUSE                                             0xb824
 
2243
#define MPSC0_MASK                                              0xb8a4
 
2244
#define MPSC1_CAUSE                                             0xb828
 
2245
#define MPSC1_MASK                                              0xb8a8
 
2246
#define MPSC2_CAUSE                                             0xb82c
 
2247
#define MPSC2_MASK                                               0xb8ac
 
2248
 
 
2249
/*******************************************/
 
2250
/*          CUNIT  Registers               */
 
2251
/*******************************************/
 
2252
 
 
2253
         /* Address Decoding Register Map */
 
2254
 
 
2255
#define CUNIT_BASE_ADDR_REG0                                    0xf200
 
2256
#define CUNIT_BASE_ADDR_REG1                                    0xf208
 
2257
#define CUNIT_BASE_ADDR_REG2                                    0xf210
 
2258
#define CUNIT_BASE_ADDR_REG3                                    0xf218
 
2259
#define CUNIT_SIZE0                                             0xf204
 
2260
#define CUNIT_SIZE1                                             0xf20c
 
2261
#define CUNIT_SIZE2                                             0xf214
 
2262
#define CUNIT_SIZE3                                             0xf21c
 
2263
#define CUNIT_HIGH_ADDR_REMAP_REG0                      0xf240
 
2264
#define CUNIT_HIGH_ADDR_REMAP_REG1                      0xf244
 
2265
#define CUNIT_BASE_ADDR_ENABLE_REG                      0xf250
 
2266
#define MPSC0_ACCESS_PROTECTION_REG                     0xf254
 
2267
#define MPSC1_ACCESS_PROTECTION_REG                     0xf258
 
2268
#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG      0xf25C
 
2269
 
 
2270
        /*  Error Report Registers  */
 
2271
 
 
2272
#define CUNIT_INTERRUPT_CAUSE_REG                       0xf310
 
2273
#define CUNIT_INTERRUPT_MASK_REG                        0xf314
 
2274
#define CUNIT_ERROR_ADDR                                        0xf318
 
2275
 
 
2276
        /*  Cunit Control Registers */
 
2277
 
 
2278
#define CUNIT_ARBITER_CONTROL_REG                       0xf300
 
2279
#define CUNIT_CONFIG_REG                                        0xb40c
 
2280
#define CUNIT_CRROSBAR_TIMEOUT_REG                      0xf304
 
2281
 
 
2282
        /*  Cunit Debug Registers   */
 
2283
 
 
2284
#define CUNIT_DEBUG_LOW                                         0xf340
 
2285
#define CUNIT_DEBUG_HIGH                                        0xf344
 
2286
#define CUNIT_MMASK                                             0xf380
 
2287
 
 
2288
#endif /* __INCmv_gen_regh */