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Viewing changes to board/freescale/mpc8544ds/ddr.c

  • Committer: Bazaar Package Importer
  • Author(s): Oliver Grawert
  • Date: 2010-03-22 15:06:23 UTC
  • Revision ID: james.westby@ubuntu.com-20100322150623-i21g8rgiyl5dohag
Tags: upstream-2010.3git20100315
Import upstream version 2010.3git20100315

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board/freescale/mpc8544ds/ddr.c
 
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/*
 
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 * Copyright 2008 Freescale Semiconductor, Inc.
 
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 *
 
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 * This program is free software; you can redistribute it and/or
 
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 * modify it under the terms of the GNU General Public License
 
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 * Version 2 as published by the Free Software Foundation.
 
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 */
 
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#include <common.h>
 
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#include <i2c.h>
 
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#include <asm/fsl_ddr_sdram.h>
 
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#include <asm/fsl_ddr_dimm_params.h>
 
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static void
 
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get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
 
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{
 
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        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 
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}
 
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unsigned int fsl_ddr_get_mem_data_rate(void)
 
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{
 
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        return get_ddr_freq(0);
 
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}
 
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void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 
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                      unsigned int ctrl_num)
 
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{
 
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        unsigned int i;
 
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        if (ctrl_num) {
 
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                printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 
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                return;
 
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        }
 
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        for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 
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                get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
 
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        }
 
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}
 
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void fsl_ddr_board_options(memctl_options_t *popts,
 
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                                dimm_params_t *pdimm,
 
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                                unsigned int ctrl_num)
 
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{
 
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        /*
 
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         * Factors to consider for clock adjust:
 
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         *      - number of chips on bus
 
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         *      - position of slot
 
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         *      - DDR1 vs. DDR2?
 
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         *      - ???
 
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         *
 
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         * This needs to be determined on a board-by-board basis.
 
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         *      0110    3/4 cycle late
 
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         *      0111    7/8 cycle late
 
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         */
 
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        popts->clk_adjust = 7;
 
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        /*
 
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         * Factors to consider for CPO:
 
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         *      - frequency
 
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         *      - ddr1 vs. ddr2
 
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         */
 
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        popts->cpo_override = 10;
 
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        /*
 
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         * Factors to consider for write data delay:
 
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         *      - number of DIMMs
 
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         *
 
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         * 1 = 1/4 clock delay
 
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         * 2 = 1/2 clock delay
 
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         * 3 = 3/4 clock delay
 
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         * 4 = 1   clock delay
 
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         * 5 = 5/4 clock delay
 
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         * 6 = 3/2 clock delay
 
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         */
 
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        popts->write_data_delay = 3;
 
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        /* 2T timing enable */
 
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        popts->twoT_en = 1;
 
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        /*
 
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         * Factors to consider for half-strength driver enable:
 
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         *      - number of DIMMs installed
 
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         */
 
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        popts->half_strength_driver_enable = 0;
 
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}