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* Ethernet driver for TI TMS320DM644x (DaVinci) chips.
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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* Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
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* ----------------------------------------------------------------------------
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* TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
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* Copyright (C) 2005 Texas Instruments.
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* ----------------------------------------------------------------------------
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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* ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
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* ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
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#include <asm/arch/emac_defs.h>
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unsigned int emac_dbg = 0;
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#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
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#ifdef DAVINCI_EMAC_GIG_ENABLE
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#define emac_gigabit_enable() davinci_eth_gigabit_enable()
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#define emac_gigabit_enable() /* no gigabit to enable */
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static void davinci_eth_mdio_enable(void);
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static int gen_init_phy(int phy_addr);
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static int gen_is_phy_connected(int phy_addr);
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static int gen_get_link_speed(int phy_addr);
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static int gen_auto_negotiate(int phy_addr);
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void eth_mdio_enable(void)
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davinci_eth_mdio_enable();
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static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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* This function must be called before emac_open() if you want to override
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* the default mac address.
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void davinci_eth_set_mac_addr(const u_int8_t *addr)
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for (i = 0; i < sizeof (davinci_eth_mac_addr); i++) {
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davinci_eth_mac_addr[i] = addr[i];
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static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
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static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
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static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
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/* EMAC descriptors */
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static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
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static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
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static volatile emac_desc *emac_rx_active_head = 0;
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static volatile emac_desc *emac_rx_active_tail = 0;
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static int emac_rx_queue_active = 0;
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/* Receive packet buffers */
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static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
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/* PHY address for a discovered PHY (0xff - not found) */
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static volatile u_int8_t active_phy_addr = 0xff;
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static void davinci_eth_mdio_enable(void)
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clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
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writel((clkdiv & 0xff) |
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MDIO_CONTROL_ENABLE |
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MDIO_CONTROL_FAULT_ENABLE,
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&adap_mdio->CONTROL);
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while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
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* Tries to find an active connected PHY. Returns 1 if address if found.
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* If no active PHY (or more than one PHY) found returns 0.
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* Sets active_phy_addr variable.
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static int davinci_eth_phy_detect(void)
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u_int32_t phy_act_state;
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active_phy_addr = 0xff;
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phy_act_state = readl(&adap_mdio->ALIVE) & EMAC_MDIO_PHY_MASK;
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if (phy_act_state == 0)
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return(0); /* No active PHYs */
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debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
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for (i = 0; i < 32; i++) {
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if (phy_act_state & (1 << i)) {
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if (phy_act_state & ~(1 << i))
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return(0); /* More than one PHY */
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return(0); /* Just to make GCC happy */
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/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
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int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
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while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
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writel(MDIO_USERACCESS0_GO |
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MDIO_USERACCESS0_WRITE_READ |
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((reg_num & 0x1f) << 21) |
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((phy_addr & 0x1f) << 16),
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&adap_mdio->USERACCESS0);
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/* Wait for command to complete */
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while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
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if (tmp & MDIO_USERACCESS0_ACK) {
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*data = tmp & 0xffff;
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/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
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int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
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while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
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writel(MDIO_USERACCESS0_GO |
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MDIO_USERACCESS0_WRITE_WRITE |
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((reg_num & 0x1f) << 21) |
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((phy_addr & 0x1f) << 16) |
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&adap_mdio->USERACCESS0);
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/* Wait for command to complete */
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while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
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/* PHY functions for a generic PHY */
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static int gen_init_phy(int phy_addr)
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if (gen_get_link_speed(phy_addr)) {
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/* Try another time */
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ret = gen_get_link_speed(phy_addr);
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static int gen_is_phy_connected(int phy_addr)
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return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy));
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static int gen_get_link_speed(int phy_addr)
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if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04))
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static int gen_auto_negotiate(int phy_addr)
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if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
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/* Restart Auto_negotiation */
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tmp |= PHY_BMCR_AUTON;
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davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
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/*check AutoNegotiate complete */
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if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
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if (!(tmp & PHY_BMSR_AUTN_COMP))
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return(gen_get_link_speed(phy_addr));
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/* End of generic PHY functions */
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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static int davinci_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
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return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
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static int davinci_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value)
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return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
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static void __attribute__((unused)) davinci_eth_gigabit_enable(void)
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if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) {
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if (data & (1 << 6)) { /* speed selection MSB */
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* Check if link detected is giga-bit
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* If Gigabit mode detected, enable gigbit in MAC
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writel(EMAC_MACCONTROL_GIGFORCE |
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EMAC_MACCONTROL_GIGABIT_ENABLE,
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&adap_emac->MACCONTROL);
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/* Eth device open */
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static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
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u_int32_t clkdiv, cnt;
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volatile emac_desc *rx_desc;
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unsigned long mac_hi;
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unsigned long mac_lo;
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debug_emac("+ emac_open\n");
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/* Reset EMAC module and disable interrupts in wrapper */
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writel(1, &adap_emac->SOFTRESET);
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while (readl(&adap_emac->SOFTRESET) != 0)
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#if defined(DAVINCI_EMAC_VERSION2)
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writel(1, &adap_ewrap->softrst);
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while (readl(&adap_ewrap->softrst) != 0)
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writel(0, &adap_ewrap->EWCTL);
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for (cnt = 0; cnt < 5; cnt++) {
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clkdiv = readl(&adap_ewrap->EWCTL);
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rx_desc = emac_rx_desc;
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writel(1, &adap_emac->TXCONTROL);
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writel(1, &adap_emac->RXCONTROL);
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/* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
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/* Using channel 0 only - other channels are disabled */
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writel(0, &adap_emac->MACINDEX);
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mac_hi = (davinci_eth_mac_addr[3] << 24) |
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(davinci_eth_mac_addr[2] << 16) |
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(davinci_eth_mac_addr[1] << 8) |
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(davinci_eth_mac_addr[0]);
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mac_lo = (davinci_eth_mac_addr[5] << 8) |
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(davinci_eth_mac_addr[4]);
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writel(mac_hi, &adap_emac->MACADDRHI);
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#if defined(DAVINCI_EMAC_VERSION2)
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writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
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&adap_emac->MACADDRLO);
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writel(mac_lo, &adap_emac->MACADDRLO);
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writel(0, &adap_emac->MACHASH1);
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writel(0, &adap_emac->MACHASH2);
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/* Set source MAC address - REQUIRED */
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writel(mac_hi, &adap_emac->MACSRCADDRHI);
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writel(mac_lo, &adap_emac->MACSRCADDRLO);
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/* Set DMA 8 TX / 8 RX Head pointers to 0 */
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addr = &adap_emac->TX0HDP;
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for(cnt = 0; cnt < 16; cnt++)
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addr = &adap_emac->RX0HDP;
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for(cnt = 0; cnt < 16; cnt++)
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/* Clear Statistics (do this before setting MacControl register) */
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addr = &adap_emac->RXGOODFRAMES;
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for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
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/* No multicast addressing */
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writel(0, &adap_emac->MACHASH1);
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writel(0, &adap_emac->MACHASH2);
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/* Create RX queue and set receive process in place */
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emac_rx_active_head = emac_rx_desc;
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for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
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rx_desc->next = (u_int32_t)(rx_desc + 1);
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rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
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rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
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rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
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/* Finalize the rx desc list */
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emac_rx_active_tail = rx_desc;
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emac_rx_queue_active = 1;
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writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
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writel(0, &adap_emac->RXBUFFEROFFSET);
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* No fancy configs - Use this for promiscous debug
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* - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
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writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
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/* Enable ch 0 only */
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writel(1, &adap_emac->RXUNICASTSET);
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/* Enable MII interface and Full duplex mode */
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#ifdef CONFIG_SOC_DA8XX
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writel((EMAC_MACCONTROL_MIIEN_ENABLE |
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EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
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EMAC_MACCONTROL_RMIISPEED_100),
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&adap_emac->MACCONTROL);
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writel((EMAC_MACCONTROL_MIIEN_ENABLE |
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EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
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&adap_emac->MACCONTROL);
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/* Init MDIO & get link state */
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clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
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writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
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&adap_mdio->CONTROL);
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/* We need to wait for MDIO to start */
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if (!phy.get_link_speed(active_phy_addr))
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emac_gigabit_enable();
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/* Start receive process */
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writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP);
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debug_emac("- emac_open\n");
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/* EMAC Channel Teardown */
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static void davinci_eth_ch_teardown(int ch)
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debug_emac("+ emac_ch_teardown\n");
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if (ch == EMAC_CH_TX) {
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/* Init TX channel teardown */
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writel(1, &adap_emac->TXTEARDOWN);
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* Wait here for Tx teardown completion interrupt to
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* occur. Note: A task delay can be called here to pend
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* rather than occupying CPU cycles - anyway it has
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* been found that teardown takes very few cpu cycles
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* and does not affect functionality
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cnt = readl(&adap_emac->TX0CP);
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} while (cnt != 0xfffffffc);
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writel(cnt, &adap_emac->TX0CP);
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writel(0, &adap_emac->TX0HDP);
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/* Init RX channel teardown */
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writel(1, &adap_emac->RXTEARDOWN);
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* Wait here for Rx teardown completion interrupt to
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* occur. Note: A task delay can be called here to pend
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* rather than occupying CPU cycles - anyway it has
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* been found that teardown takes very few cpu cycles
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* and does not affect functionality
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cnt = readl(&adap_emac->RX0CP);
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} while (cnt != 0xfffffffc);
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writel(cnt, &adap_emac->RX0CP);
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writel(0, &adap_emac->RX0HDP);
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debug_emac("- emac_ch_teardown\n");
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/* Eth device close */
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static void davinci_eth_close(struct eth_device *dev)
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debug_emac("+ emac_close\n");
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davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
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davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
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/* Reset EMAC module and disable interrupts in wrapper */
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writel(1, &adap_emac->SOFTRESET);
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#if defined(DAVINCI_EMAC_VERSION2)
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writel(1, &adap_ewrap->softrst);
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writel(0, &adap_ewrap->EWCTL);
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debug_emac("- emac_close\n");
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static int tx_send_loop = 0;
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* This function sends a single packet on the network and returns
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* positive number (number of bytes transmitted) or negative for error
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static int davinci_eth_send_packet (struct eth_device *dev,
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volatile void *packet, int length)
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/* Return error if no link */
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if (!phy.get_link_speed (active_phy_addr)) {
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printf ("WARN: emac_send_packet: No link\n");
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emac_gigabit_enable();
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/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
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if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
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length = EMAC_MIN_ETHERNET_PKT_SIZE;
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/* Populate the TX descriptor */
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emac_tx_desc->next = 0;
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emac_tx_desc->buffer = (u_int8_t *) packet;
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emac_tx_desc->buff_off_len = (length & 0xffff);
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emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
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EMAC_CPPI_OWNERSHIP_BIT |
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/* Send the packet */
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writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP);
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/* Wait for packet to complete or link down */
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if (!phy.get_link_speed (active_phy_addr)) {
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davinci_eth_ch_teardown (EMAC_CH_TX);
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emac_gigabit_enable();
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if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
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* This function handles receipt of a packet from the network
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static int davinci_eth_rcv_packet (struct eth_device *dev)
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volatile emac_desc *rx_curr_desc;
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volatile emac_desc *curr_desc;
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volatile emac_desc *tail_desc;
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int status, ret = -1;
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rx_curr_desc = emac_rx_active_head;
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status = rx_curr_desc->pkt_flag_len;
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if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
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if (status & EMAC_CPPI_RX_ERROR_FRAME) {
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/* Error in packet - discard it and requeue desc */
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printf ("WARN: emac_rcv_pkt: Error in packet\n");
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NetReceive (rx_curr_desc->buffer,
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(rx_curr_desc->buff_off_len & 0xffff));
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ret = rx_curr_desc->buff_off_len & 0xffff;
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/* Ack received packet descriptor */
568
writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP);
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curr_desc = rx_curr_desc;
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emac_rx_active_head =
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(volatile emac_desc *) rx_curr_desc->next;
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if (status & EMAC_CPPI_EOQ_BIT) {
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if (emac_rx_active_head) {
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writel((unsigned long)emac_rx_active_head,
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emac_rx_queue_active = 0;
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printf ("INFO:emac_rcv_packet: RX Queue not active\n");
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/* Recycle RX descriptor */
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rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
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rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
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rx_curr_desc->next = 0;
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if (emac_rx_active_head == 0) {
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printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
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emac_rx_active_head = curr_desc;
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emac_rx_active_tail = curr_desc;
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if (emac_rx_queue_active != 0) {
593
writel((unsigned long)emac_rx_active_head,
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printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
596
emac_rx_queue_active = 1;
599
tail_desc = emac_rx_active_tail;
600
emac_rx_active_tail = curr_desc;
601
tail_desc->next = (unsigned int) curr_desc;
602
status = tail_desc->pkt_flag_len;
603
if (status & EMAC_CPPI_EOQ_BIT) {
604
writel((unsigned long)curr_desc,
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status &= ~EMAC_CPPI_EOQ_BIT;
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tail_desc->pkt_flag_len = status;
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* This function initializes the emac hardware. It does NOT initialize
617
* EMAC modules power or pin multiplexors, that is done by board_init()
618
* much earlier in bootup process. Returns 1 on success, 0 otherwise.
620
int davinci_emac_initialize(void)
625
struct eth_device *dev;
627
dev = malloc(sizeof *dev);
632
memset(dev, 0, sizeof *dev);
635
dev->init = davinci_eth_open;
636
dev->halt = davinci_eth_close;
637
dev->send = davinci_eth_send_packet;
638
dev->recv = davinci_eth_rcv_packet;
642
davinci_eth_mdio_enable();
644
for (i = 0; i < 256; i++) {
645
if (readl(&adap_mdio->ALIVE))
651
printf("No ETH PHY detected!!!\n");
655
/* Find if a PHY is connected and get it's address */
656
if (!davinci_eth_phy_detect())
659
/* Get PHY ID and initialize phy_ops for a detected PHY */
660
if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) {
661
active_phy_addr = 0xff;
665
phy_id = (tmp << 16) & 0xffff0000;
667
if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) {
668
active_phy_addr = 0xff;
672
phy_id |= tmp & 0x0000ffff;
676
sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr);
677
phy.init = lxt972_init_phy;
678
phy.is_phy_connected = lxt972_is_phy_connected;
679
phy.get_link_speed = lxt972_get_link_speed;
680
phy.auto_negotiate = lxt972_auto_negotiate;
683
sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr);
684
phy.init = dp83848_init_phy;
685
phy.is_phy_connected = dp83848_is_phy_connected;
686
phy.get_link_speed = dp83848_get_link_speed;
687
phy.auto_negotiate = dp83848_auto_negotiate;
690
sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
691
phy.init = gen_init_phy;
692
phy.is_phy_connected = gen_is_phy_connected;
693
phy.get_link_speed = gen_get_link_speed;
694
phy.auto_negotiate = gen_auto_negotiate;
697
printf("Ethernet PHY: %s\n", phy.name);
699
miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write);