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* Custom IDEAS, Inc. <www.cideas.com>
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* Jon Diekema <diekema@cideas.com>
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* See file CREDITS for list of people who contributed to this
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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#include <asm/cpm_8260.h>
29
#include <configs/sacsng.h>
33
DECLARE_GLOBAL_DATA_PTR;
35
int Daq64xSampling = 0;
38
void Daq_BRG_Reset(uint brg)
40
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
41
volatile uint *brg_ptr;
43
brg_ptr = (uint *)&immr->im_brgc1;
46
brg_ptr = (uint *)&immr->im_brgc5;
50
*brg_ptr |= CPM_BRG_RST;
51
*brg_ptr &= ~CPM_BRG_RST;
54
void Daq_BRG_Disable(uint brg)
56
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
57
volatile uint *brg_ptr;
59
brg_ptr = (uint *)&immr->im_brgc1;
62
brg_ptr = (uint *)&immr->im_brgc5;
66
*brg_ptr &= ~CPM_BRG_EN;
69
void Daq_BRG_Enable(uint brg)
71
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
72
volatile uint *brg_ptr;
74
brg_ptr = (uint *)&immr->im_brgc1;
76
brg_ptr = (uint *)&immr->im_brgc5;
80
*brg_ptr |= CPM_BRG_EN;
83
uint Daq_BRG_Get_Div16(uint brg)
85
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
88
brg_ptr = (uint *)&immr->im_brgc1;
90
brg_ptr = (uint *)&immr->im_brgc5;
95
if (*brg_ptr & CPM_BRG_DIV16) {
105
void Daq_BRG_Set_Div16(uint brg, uint div16)
107
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
110
brg_ptr = (uint *)&immr->im_brgc1;
112
brg_ptr = (uint *)&immr->im_brgc5;
119
*brg_ptr |= CPM_BRG_DIV16;
123
*brg_ptr &= ~CPM_BRG_DIV16;
127
uint Daq_BRG_Get_Count(uint brg)
129
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
133
brg_ptr = (uint *)&immr->im_brgc1;
135
brg_ptr = (uint *)&immr->im_brgc5;
140
/* Get the clock divider
142
* Note: A clock divider of 0 means divide by 1,
143
* therefore we need to add 1 to the count.
145
brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
147
if (*brg_ptr & CPM_BRG_DIV16) {
154
void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
156
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
159
brg_ptr = (uint *)&immr->im_brgc1;
161
brg_ptr = (uint *)&immr->im_brgc5;
167
* Note: A clock divider of 0 means divide by 1,
168
* therefore we need to subtract 1 from the count.
170
if (brg_cnt > 4096) {
171
/* Prescale = Divide by 16 */
172
*brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
173
(((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
174
*brg_ptr |= CPM_BRG_DIV16;
177
/* Prescale = Divide by 1 */
178
*brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
179
((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
180
*brg_ptr &= ~CPM_BRG_DIV16;
184
uint Daq_BRG_Get_ExtClk(uint brg)
186
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
189
brg_ptr = (uint *)&immr->im_brgc1;
191
brg_ptr = (uint *)&immr->im_brgc5;
196
return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
199
char* Daq_BRG_Get_ExtClk_Description(uint brg)
203
extc = Daq_BRG_Get_ExtClk(brg);
244
void Daq_BRG_Set_ExtClk(uint brg, uint extc)
246
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
249
brg_ptr = (uint *)&immr->im_brgc1;
251
brg_ptr = (uint *)&immr->im_brgc5;
256
*brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
257
((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
260
uint Daq_BRG_Rate(uint brg)
262
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
267
brg_ptr = (uint *)&immr->im_brgc1;
270
brg_ptr = (uint *)&immr->im_brgc5;
271
brg_ptr += (brg - 4);
274
brg_cnt = Daq_BRG_Get_Count(brg);
276
switch (Daq_BRG_Get_ExtClk(brg)) {
277
case CPM_BRG_EXTC_CLK3:
278
case CPM_BRG_EXTC_CLK5: {
283
brg_freq = (uint)BRG_INT_CLK / brg_cnt;
289
uint Daq_Get_SampleRate(void)
292
* Read the BRG's to return the actual sample rate.
294
return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
297
void Daq_Init_Clocks(int sample_rate, int sample_64x)
299
volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
300
uint mclk_divisor; /* MCLK divisor */
301
int flag; /* Interrupt state */
303
/* Save off the clocking data */
304
Daq64xSampling = sample_64x;
307
* Limit the sample rate to some sensible values.
309
if (sample_rate > MAX_64x_SAMPLE_RATE) {
310
sample_rate = MAX_64x_SAMPLE_RATE;
312
if (sample_rate < MIN_SAMPLE_RATE) {
313
sample_rate = MIN_SAMPLE_RATE;
317
* Initialize the MCLK/SCLK/LRCLK baud rate generators.
321
Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
324
# ifdef RUN_SCLK_ON_BRG_INT
325
Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
327
Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
331
# ifdef RUN_LRCLK_ON_BRG_INT
332
Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
334
Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
338
* Dynamically adjust MCLK based on the new sample rate.
341
/* Compute the divisors */
342
mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
345
* Disable interrupt and save the current state
347
flag = disable_interrupts();
350
Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
353
# ifdef RUN_SCLK_ON_BRG_INT
354
Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
356
Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
359
# ifdef RUN_LRCLK_ON_BRG_INT
360
Daq_BRG_Set_Count(LRCLK_BRG,
361
mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
363
Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
367
* Restore the Interrupt state
373
/* Enable the clock drivers */
374
iopa->pdat &= ~SLRCLK_EN_MASK;
377
void Daq_Stop_Clocks(void)
380
#ifdef TIGHTEN_UP_BRG_TIMING
381
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
382
register uint mclk_brg; /* MCLK BRG value */
383
register uint sclk_brg; /* SCLK BRG value */
384
register uint lrclk_brg; /* LRCLK BRG value */
385
unsigned long flag; /* Interrupt flags */
388
# ifdef TIGHTEN_UP_BRG_TIMING
390
* Obtain MCLK BRG reset/disabled value
393
mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
396
mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
399
mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
402
mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
405
mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
408
mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
411
mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
414
mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
418
* Obtain SCLK BRG reset/disabled value
421
sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
424
sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
427
sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
430
sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
433
sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
436
sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
439
sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
442
sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
446
* Obtain LRCLK BRG reset/disabled value
448
# if (LRCLK_BRG == 0)
449
lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
451
# if (LRCLK_BRG == 1)
452
lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
454
# if (LRCLK_BRG == 2)
455
lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
457
# if (LRCLK_BRG == 3)
458
lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
460
# if (LRCLK_BRG == 4)
461
lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
463
# if (LRCLK_BRG == 5)
464
lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
466
# if (LRCLK_BRG == 6)
467
lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
469
# if (LRCLK_BRG == 7)
470
lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
474
* Disable interrupt and save the current state
476
flag = disable_interrupts();
479
* Set reset on MCLK BRG
482
*IM_BRGC1 = mclk_brg;
485
*IM_BRGC2 = mclk_brg;
488
*IM_BRGC3 = mclk_brg;
491
*IM_BRGC4 = mclk_brg;
494
*IM_BRGC5 = mclk_brg;
497
*IM_BRGC6 = mclk_brg;
500
*IM_BRGC7 = mclk_brg;
503
*IM_BRGC8 = mclk_brg;
507
* Set reset on SCLK BRG
510
*IM_BRGC1 = sclk_brg;
513
*IM_BRGC2 = sclk_brg;
516
*IM_BRGC3 = sclk_brg;
519
*IM_BRGC4 = sclk_brg;
522
*IM_BRGC5 = sclk_brg;
525
*IM_BRGC6 = sclk_brg;
528
*IM_BRGC7 = sclk_brg;
531
*IM_BRGC8 = sclk_brg;
535
* Set reset on LRCLK BRG
537
# if (LRCLK_BRG == 0)
538
*IM_BRGC1 = lrclk_brg;
540
# if (LRCLK_BRG == 1)
541
*IM_BRGC2 = lrclk_brg;
543
# if (LRCLK_BRG == 2)
544
*IM_BRGC3 = lrclk_brg;
546
# if (LRCLK_BRG == 3)
547
*IM_BRGC4 = lrclk_brg;
549
# if (LRCLK_BRG == 4)
550
*IM_BRGC5 = lrclk_brg;
552
# if (LRCLK_BRG == 5)
553
*IM_BRGC6 = lrclk_brg;
555
# if (LRCLK_BRG == 6)
556
*IM_BRGC7 = lrclk_brg;
558
# if (LRCLK_BRG == 7)
559
*IM_BRGC8 = lrclk_brg;
563
* Clear reset on MCLK BRG
566
*IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
569
*IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
572
*IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
575
*IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
578
*IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
581
*IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
584
*IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
587
*IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
591
* Clear reset on SCLK BRG
594
*IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
597
*IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
600
*IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
603
*IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
606
*IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
609
*IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
612
*IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
615
*IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
619
* Clear reset on LRCLK BRG
621
# if (LRCLK_BRG == 0)
622
*IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
624
# if (LRCLK_BRG == 1)
625
*IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
627
# if (LRCLK_BRG == 2)
628
*IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
630
# if (LRCLK_BRG == 3)
631
*IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
633
# if (LRCLK_BRG == 4)
634
*IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
636
# if (LRCLK_BRG == 5)
637
*IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
639
# if (LRCLK_BRG == 6)
640
*IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
642
# if (LRCLK_BRG == 7)
643
*IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
647
* Restore the Interrupt state
656
Daq_BRG_Reset(MCLK_BRG);
657
Daq_BRG_Reset(SCLK_BRG);
658
Daq_BRG_Reset(LRCLK_BRG);
662
void Daq_Start_Clocks(int sample_rate)
665
#ifdef TIGHTEN_UP_BRG_TIMING
666
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
668
register uint mclk_brg; /* MCLK BRG value */
669
register uint sclk_brg; /* SCLK BRG value */
670
register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
671
register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
672
uint lrclk_brg; /* LRCLK BRG value */
673
unsigned long flags; /* Interrupt flags */
674
uint sclk_cnt; /* SCLK count */
675
uint delay_cnt; /* Delay count */
678
# ifdef TIGHTEN_UP_BRG_TIMING
680
* Obtain the enabled MCLK BRG value
683
mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
686
mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
689
mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
692
mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
695
mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
698
mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
701
mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
704
mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
708
* Obtain the enabled SCLK BRG value
711
sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
714
sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
717
sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
720
sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
723
sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
726
sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
729
sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
732
sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
736
* Obtain the enabled LRCLK BRG value
738
# if (LRCLK_BRG == 0)
739
lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
741
# if (LRCLK_BRG == 1)
742
lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
744
# if (LRCLK_BRG == 2)
745
lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
747
# if (LRCLK_BRG == 3)
748
lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
750
# if (LRCLK_BRG == 4)
751
lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
753
# if (LRCLK_BRG == 5)
754
lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
756
# if (LRCLK_BRG == 6)
757
lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
759
# if (LRCLK_BRG == 7)
760
lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
763
/* Save off the real LRCLK value */
764
real_lrclk_brg = lrclk_brg;
766
/* Obtain the current SCLK count */
767
sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
769
/* Compute the delay as a function of SCLK count */
770
delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
771
if (DaqSampleRate == 43402) {
775
/* Clear out the count */
776
temp_lrclk_brg = sclk_brg & ~0x00001FFE;
778
/* Insert the count */
779
temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
782
* Disable interrupt and save the current state
784
flag = disable_interrupts();
790
*IM_BRGC1 = mclk_brg;
793
*IM_BRGC2 = mclk_brg;
796
*IM_BRGC3 = mclk_brg;
799
*IM_BRGC4 = mclk_brg;
802
*IM_BRGC5 = mclk_brg;
805
*IM_BRGC6 = mclk_brg;
808
*IM_BRGC7 = mclk_brg;
811
*IM_BRGC8 = mclk_brg;
818
*IM_BRGC1 = sclk_brg;
821
*IM_BRGC2 = sclk_brg;
824
*IM_BRGC3 = sclk_brg;
827
*IM_BRGC4 = sclk_brg;
830
*IM_BRGC5 = sclk_brg;
833
*IM_BRGC6 = sclk_brg;
836
*IM_BRGC7 = sclk_brg;
839
*IM_BRGC8 = sclk_brg;
843
* Enable LRCLK BRG (1st time - temporary)
845
# if (LRCLK_BRG == 0)
846
*IM_BRGC1 = temp_lrclk_brg;
848
# if (LRCLK_BRG == 1)
849
*IM_BRGC2 = temp_lrclk_brg;
851
# if (LRCLK_BRG == 2)
852
*IM_BRGC3 = temp_lrclk_brg;
854
# if (LRCLK_BRG == 3)
855
*IM_BRGC4 = temp_lrclk_brg;
857
# if (LRCLK_BRG == 4)
858
*IM_BRGC5 = temp_lrclk_brg;
860
# if (LRCLK_BRG == 5)
861
*IM_BRGC6 = temp_lrclk_brg;
863
# if (LRCLK_BRG == 6)
864
*IM_BRGC7 = temp_lrclk_brg;
866
# if (LRCLK_BRG == 7)
867
*IM_BRGC8 = temp_lrclk_brg;
871
* Enable LRCLK BRG (2nd time - permanent)
873
# if (LRCLK_BRG == 0)
874
*IM_BRGC1 = real_lrclk_brg;
876
# if (LRCLK_BRG == 1)
877
*IM_BRGC2 = real_lrclk_brg;
879
# if (LRCLK_BRG == 2)
880
*IM_BRGC3 = real_lrclk_brg;
882
# if (LRCLK_BRG == 3)
883
*IM_BRGC4 = real_lrclk_brg;
885
# if (LRCLK_BRG == 4)
886
*IM_BRGC5 = real_lrclk_brg;
888
# if (LRCLK_BRG == 5)
889
*IM_BRGC6 = real_lrclk_brg;
891
# if (LRCLK_BRG == 6)
892
*IM_BRGC7 = real_lrclk_brg;
894
# if (LRCLK_BRG == 7)
895
*IM_BRGC8 = real_lrclk_brg;
899
* Restore the Interrupt state
908
Daq_BRG_Enable(LRCLK_BRG);
909
Daq_BRG_Enable(SCLK_BRG);
910
Daq_BRG_Enable(MCLK_BRG);
914
void Daq_Display_Clocks(void)
917
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
918
uint mclk_divisor; /* Detected MCLK divisor */
919
uint sclk_divisor; /* Detected SCLK divisor */
922
if (immr->im_brgc4 != 0) {
923
printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
925
(uint)&(immr->im_brgc4),
926
Daq_BRG_Get_Count(3),
927
Daq_BRG_Get_ExtClk(3),
928
Daq_BRG_Get_ExtClk_Description(3));
930
if (immr->im_brgc8 != 0) {
931
printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
933
(uint)&(immr->im_brgc8),
934
Daq_BRG_Get_Count(7),
935
Daq_BRG_Get_ExtClk(7),
936
Daq_BRG_Get_ExtClk_Description(7));
938
if (immr->im_brgc6 != 0) {
939
printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
941
(uint)&(immr->im_brgc6),
942
Daq_BRG_Get_Count(5),
943
Daq_BRG_Get_ExtClk(5),
944
Daq_BRG_Get_ExtClk_Description(5));
946
if (immr->im_brgc1 != 0) {
947
printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
949
(uint)&(immr->im_brgc1),
950
Daq_BRG_Get_Count(0),
951
Daq_BRG_Get_ExtClk(0),
952
Daq_BRG_Get_ExtClk_Description(0));
954
if (immr->im_brgc2 != 0) {
955
printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
957
(uint)&(immr->im_brgc2),
958
Daq_BRG_Get_Count(1),
959
Daq_BRG_Get_ExtClk(1),
960
Daq_BRG_Get_ExtClk_Description(1));
962
if (immr->im_brgc3 != 0) {
963
printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
965
(uint)&(immr->im_brgc3),
966
Daq_BRG_Get_Count(2),
967
Daq_BRG_Get_ExtClk(2),
968
Daq_BRG_Get_ExtClk_Description(2));
970
if (immr->im_brgc5 != 0) {
971
printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
973
(uint)&(immr->im_brgc5),
974
Daq_BRG_Get_Count(4),
975
Daq_BRG_Get_ExtClk(4),
976
Daq_BRG_Get_ExtClk_Description(4));
978
if (immr->im_brgc7 != 0) {
979
printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
981
(uint)&(immr->im_brgc7),
982
Daq_BRG_Get_Count(6),
983
Daq_BRG_Get_ExtClk(6),
984
Daq_BRG_Get_ExtClk_Description(6));
987
# ifdef RUN_SCLK_ON_BRG_INT
988
mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
990
mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
992
# ifdef RUN_LRCLK_ON_BRG_INT
993
sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
995
sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
998
printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
999
printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
1000
Daq_BRG_Rate(MCLK_BRG),
1002
mclk_divisor * sclk_divisor);
1003
# ifdef RUN_SCLK_ON_BRG_INT
1004
printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
1005
Daq_BRG_Rate(SCLK_BRG),
1008
printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
1009
Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
1012
# ifdef RUN_LRCLK_ON_BRG_INT
1013
printf("\tLRCLK %8d Hz\n",
1014
Daq_BRG_Rate(LRCLK_BRG));
1016
# ifdef RUN_SCLK_ON_BRG_INT
1017
printf("\tLRCLK %8d Hz\n",
1018
Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
1020
printf("\tLRCLK %8d Hz\n",
1021
Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));