3
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5
* See file CREDITS for list of people who contributed to this
8
* This program is free software; you can redistribute it and/or
9
* modify it under the terms of the GNU General Public License as
10
* published by the Free Software Foundation; either version 2 of
11
* the License, or (at your option) any later version.
13
* This program is distributed in the hope that it will be useful,
14
* but WITHOUT ANY WARRANTY; without even the implied warranty of
15
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
* GNU General Public License for more details.
18
* You should have received a copy of the GNU General Public License
19
* along with this program; if not, write to the Free Software
20
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24
/*************************************************************************
25
* adaption for the Marvell DB64360 Board
26
* Ingo Assmus (ingo.assmus@keymile.com)
28
* adaption for the cpci750 Board
29
* Reinhard Arlt (reinhard.arlt@esd-electronics.com)
30
*************************************************************************/
33
/* sdram_init.c - automatic memory sizing */
37
#include "../../Marvell/include/memory.h"
38
#include "../../Marvell/include/pci.h"
39
#include "../../Marvell/include/mv_gen_reg.h"
44
#include "../../Marvell/common/i2c.h"
48
DECLARE_GLOBAL_DATA_PTR;
54
#endif /* of CONFIG_PCI */
62
int set_dfcdlInit(void); /* setup delay line of Mv64360 */
64
/* ------------------------------------------------------------------------- */
67
memory_map_bank(unsigned int bankNo,
68
unsigned int bankBase,
69
unsigned int bankLength)
78
printf("mapping bank %d at %08x - %08x\n",
79
bankNo, bankBase, bankBase + bankLength - 1);
81
printf("unmapping bank %d\n", bankNo);
85
memoryMapBank(bankNo, bankBase, bankLength);
88
for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
93
READ_LINE_AGGRESSIVE_PREFETCH |
94
READ_MULTI_AGGRESSIVE_PREFETCH |
98
pciMapMemoryBank(host, bankNo, bankBase, bankLength);
100
pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
103
pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
111
/* much of this code is based on (or is) the code in the pip405 port */
112
/* thanks go to the authors of said port - Josh */
114
/* structure to store the relevant information about an sdram bank */
115
typedef struct sdram_info {
117
uchar registered, ecc;
124
/* Typedefs for 'gtAuxilGetDIMMinfo' function */
126
typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
128
typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
129
SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
132
typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
133
typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
136
/* SDRAM/DDR information struct */
137
typedef struct _gtMemoryDimmInfo {
138
MEMORY_TYPE memoryType;
139
unsigned int numOfRowAddresses;
140
unsigned int numOfColAddresses;
141
unsigned int numOfModuleBanks;
142
unsigned int dataWidth;
143
VOLTAGE_INTERFACE voltageInterface;
144
unsigned int errorCheckType; /* ECC , PARITY.. */
145
unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
146
unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
147
unsigned int minClkDelay;
148
unsigned int burstLengthSupported;
149
unsigned int numOfBanksOnEachDevice;
150
unsigned int suportedCasLatencies;
151
unsigned int RefreshInterval;
152
unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
153
unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
154
MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
155
MAX_CL_SUPPORTED_SD maxClSupported_SD;
156
unsigned int moduleBankDensity;
157
/* module attributes (true for yes) */
158
bool bufferedAddrAndControlInputs;
159
bool registeredAddrAndControlInputs;
161
bool bufferedDQMBinputs;
162
bool registeredDQMBinputs;
163
bool differentialClockInput;
164
bool redundantRowAddressing;
166
/* module general attributes */
167
bool suportedAutoPreCharge;
168
bool suportedPreChargeAll;
169
bool suportedEarlyRasPreCharge;
170
bool suportedWrite1ReadBurst;
171
bool suported5PercentLowVCC;
172
bool suported5PercentUpperVCC;
173
/* module timing parameters */
174
unsigned int minRasToCasDelay;
175
unsigned int minRowActiveRowActiveDelay;
176
unsigned int minRasPulseWidth;
177
unsigned int minRowPrechargeTime; /* measured in ns */
179
int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
180
int addrAndCommandSetupTime; /* (measured in ns/100) */
181
int dataInputSetupTime; /* LoP left of point (measured in ns) */
182
int dataInputHoldTime; /* LoP left of point (measured in ns) */
183
/* tAC times for highest 2nd and 3rd highest CAS Latency values */
184
unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
185
unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
186
unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
187
unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
188
unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
189
unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
191
unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
192
unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
194
unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
195
unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
197
unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
198
unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
200
/* Parameters calculated from
201
the extracted DIMM information */
203
unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
204
unsigned int numberOfDevices;
205
uchar drb_size; /* DRAM size in n*64Mbit */
206
uchar slot; /* Slot Number this module is inserted in */
207
uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
209
uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
210
uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
211
uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
212
unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
213
unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
214
unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
215
uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
222
* translate ns.ns/10 coding of SPD timing values
223
* into 10 ps unit values
225
static inline unsigned short
226
NS10to10PS(unsigned char spd_byte)
228
unsigned short ns, ns10;
230
/* isolate upper nibble */
231
ns = (spd_byte >> 4) & 0x0F;
232
/* isolate lower nibble */
233
ns10 = (spd_byte & 0x0F);
235
return(ns*100 + ns10*10);
239
* translate ns coding of SPD timing values
240
* into 10 ps unit values
242
static inline unsigned short
243
NSto10PS(unsigned char spd_byte)
245
return(spd_byte*100);
248
/* This code reads the SPD chip on the sdram and populates
249
* the array which is passed in with the relevant information */
250
/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
251
static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
253
unsigned long spd_checksum;
255
uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
257
unsigned int i, j, density = 1, devicesForErrCheck = 0;
262
unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
263
int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
264
uchar supp_cal, cal_val;
265
ulong memclk, tmemclk;
267
uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
270
memclk = gd->bus_clk;
271
tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
273
memset (data, 0, sizeof (data));
278
DP (puts ("before i2c read\n"));
280
ret = i2c_read (addr, 0, 2, data, 128);
282
DP (puts ("after i2c read\n"));
284
if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
285
|| (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
286
|| (data[70] != 'b') || (data[71] != 'h')) {
290
if ((ret != 0) && (slot == 0)) {
291
memset (data, 0, sizeof (data));
339
/* zero all the values */
340
memset (dimmInfo, 0, sizeof (*dimmInfo));
342
/* copy the SPD content 1:1 into the dimmInfo structure */
343
for (i = 0; i <= 127; i++) {
344
dimmInfo->spd_raw_data[i] = data[i];
348
DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
351
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
353
#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
355
for (i = 0; i <= 127; i++) {
356
printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
362
/* find Manufacturer of Dimm Module */
363
for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
364
dimmInfo->manufactura[i] = data[64 + i];
366
printf ("\nThis RAM-Module is produced by: %s\n",
367
dimmInfo->manufactura);
369
/* find Manul-ID of Dimm Module */
370
for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
371
dimmInfo->modul_id[i] = data[73 + i];
373
printf ("The Module-ID of this RAM-Module is: %s\n",
376
/* find Vendor-Data of Dimm Module */
377
for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
378
dimmInfo->vendor_data[i] = data[99 + i];
380
printf ("Vendor Data of this RAM-Module is: %s\n",
381
dimmInfo->vendor_data);
383
/* find modul_serial_no of Dimm Module */
384
dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
385
printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
386
dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
388
/* find Manufac-Data of Dimm Module */
389
dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
390
printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
392
/* find modul_revision of Dimm Module */
393
dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
394
printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
396
/* find manufac_place of Dimm Module */
397
dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
398
printf ("manufac_place of this RAM-Module is: %d\n",
399
dimmInfo->manufac_place);
402
/*------------------------------------------------------------------------------------------------------------------------------*/
403
/* calculate SPD checksum */
404
/*------------------------------------------------------------------------------------------------------------------------------*/
406
#if 0 /* test-only */
407
for (i = 0; i <= 62; i++) {
408
spd_checksum += data[i];
411
if ((spd_checksum & 0xff) != data[63]) {
412
printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
417
printf ("SPD Checksum ok!\n");
418
#endif /* test-only */
420
/*------------------------------------------------------------------------------------------------------------------------------*/
421
for (i = 2; i <= 35; i++) {
423
case 2: /* Memory type (DDR / SDRAM) */
424
dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
426
if (dimmInfo->memoryType == 0)
428
("Dram_type in slot %d is: SDRAM\n",
430
if (dimmInfo->memoryType == 1)
432
("Dram_type in slot %d is: DDRAM\n",
436
/*------------------------------------------------------------------------------------------------------------------------------*/
438
case 3: /* Number Of Row Addresses */
439
dimmInfo->numOfRowAddresses = data[i];
441
("Module Number of row addresses: %d\n",
442
dimmInfo->numOfRowAddresses));
444
/*------------------------------------------------------------------------------------------------------------------------------*/
446
case 4: /* Number Of Column Addresses */
447
dimmInfo->numOfColAddresses = data[i];
449
("Module Number of col addresses: %d\n",
450
dimmInfo->numOfColAddresses));
452
/*------------------------------------------------------------------------------------------------------------------------------*/
454
case 5: /* Number Of Module Banks */
455
dimmInfo->numOfModuleBanks = data[i];
457
("Number of Banks on Mod. : %d\n",
458
dimmInfo->numOfModuleBanks));
460
/*------------------------------------------------------------------------------------------------------------------------------*/
462
case 6: /* Data Width */
463
dimmInfo->dataWidth = data[i];
465
("Module Data Width: %d\n",
466
dimmInfo->dataWidth));
468
/*------------------------------------------------------------------------------------------------------------------------------*/
470
case 8: /* Voltage Interface */
473
dimmInfo->voltageInterface = TTL_5V_TOLERANT;
475
("Module is TTL_5V_TOLERANT\n"));
478
dimmInfo->voltageInterface = LVTTL;
480
("Module is LVTTL\n"));
483
dimmInfo->voltageInterface = HSTL_1_5V;
485
("Module is TTL_5V_TOLERANT\n"));
488
dimmInfo->voltageInterface = SSTL_3_3V;
490
("Module is HSTL_1_5V\n"));
493
dimmInfo->voltageInterface = SSTL_2_5V;
495
("Module is SSTL_2_5V\n"));
498
dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
500
("Module is VOLTAGE_UNKNOWN\n"));
504
/*------------------------------------------------------------------------------------------------------------------------------*/
506
case 9: /* Minimum Cycle Time At Max CasLatancy */
507
shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
508
mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
510
(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
512
(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
513
leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
514
rightOfPoint = (data[i] & maskRightOfPoint) * mult;
515
dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
517
dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
520
("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
521
leftOfPoint, rightOfPoint));
523
/*------------------------------------------------------------------------------------------------------------------------------*/
525
case 10: /* Clock To Data Out */
526
div = (dimmInfo->memoryType == DDR) ? 100 : 10;
528
(((data[i] & 0xf0) >> 4) * 10) +
530
leftOfPoint = time_tmp / div;
531
rightOfPoint = time_tmp % div;
532
dimmInfo->clockToDataOut_LoP = leftOfPoint;
533
dimmInfo->clockToDataOut_RoP = rightOfPoint;
535
("Clock To Data Out: %d.%2d [ns]\n",
536
leftOfPoint, rightOfPoint));
537
/*dimmInfo->clockToDataOut */
539
/*------------------------------------------------------------------------------------------------------------------------------*/
542
case 11: /* Error Check Type */
543
dimmInfo->errorCheckType = data[i];
545
("Error Check Type (0=NONE): %d\n",
546
dimmInfo->errorCheckType));
549
/*------------------------------------------------------------------------------------------------------------------------------*/
551
case 12: /* Refresh Interval */
552
dimmInfo->RefreshInterval = data[i];
554
("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
555
dimmInfo->RefreshInterval));
557
/*------------------------------------------------------------------------------------------------------------------------------*/
559
case 13: /* Sdram Width */
560
dimmInfo->sdramWidth = data[i];
562
("Sdram Width: %d\n",
563
dimmInfo->sdramWidth));
565
/*------------------------------------------------------------------------------------------------------------------------------*/
567
case 14: /* Error Check Data Width */
568
dimmInfo->errorCheckDataWidth = data[i];
570
("Error Check Data Width: %d\n",
571
dimmInfo->errorCheckDataWidth));
573
/*------------------------------------------------------------------------------------------------------------------------------*/
575
case 15: /* Minimum Clock Delay */
576
dimmInfo->minClkDelay = data[i];
578
("Minimum Clock Delay: %d\n",
579
dimmInfo->minClkDelay));
581
/*------------------------------------------------------------------------------------------------------------------------------*/
583
case 16: /* Burst Length Supported */
584
/******-******-******-*******
585
* bit3 | bit2 | bit1 | bit0 *
586
*******-******-******-*******
587
burst length = * 8 | 4 | 2 | 1 *
588
*****************************
590
If for example bit0 and bit2 are set, the burst
591
length supported are 1 and 4. */
593
dimmInfo->burstLengthSupported = data[i];
596
("Burst Length Supported: "));
597
if (dimmInfo->burstLengthSupported & 0x01)
599
if (dimmInfo->burstLengthSupported & 0x02)
601
if (dimmInfo->burstLengthSupported & 0x04)
603
if (dimmInfo->burstLengthSupported & 0x08)
605
DP (printf (" Bit \n"));
608
/*------------------------------------------------------------------------------------------------------------------------------*/
610
case 17: /* Number Of Banks On Each Device */
611
dimmInfo->numOfBanksOnEachDevice = data[i];
613
("Number Of Banks On Each Chip: %d\n",
614
dimmInfo->numOfBanksOnEachDevice));
616
/*------------------------------------------------------------------------------------------------------------------------------*/
618
case 18: /* Suported Cas Latencies */
621
*******-******-******-******-******-******-******-*******
622
* bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
623
*******-******-******-******-******-******-******-*******
624
CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
625
*********************************************************
627
*******-******-******-******-******-******-******-*******
628
* bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
629
*******-******-******-******-******-******-******-*******
630
CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
631
********************************************************/
632
dimmInfo->suportedCasLatencies = data[i];
635
("Suported Cas Latencies: (CL) "));
636
if (dimmInfo->memoryType == 0) { /* SDRAM */
637
for (k = 0; k <= 7; k++) {
639
suportedCasLatencies & (1 << k))
645
} else { /* DDR-RAM */
647
if (dimmInfo->suportedCasLatencies & 1)
649
if (dimmInfo->suportedCasLatencies & 2)
650
DP (printf ("1.5, "));
651
if (dimmInfo->suportedCasLatencies & 4)
653
if (dimmInfo->suportedCasLatencies & 8)
654
DP (printf ("2.5, "));
655
if (dimmInfo->suportedCasLatencies & 16)
657
if (dimmInfo->suportedCasLatencies & 32)
658
DP (printf ("3.5, "));
663
/* Calculating MAX CAS latency */
664
for (j = 7; j > 0; j--) {
666
suportedCasLatencies >> j) & 0x1) ==
668
switch (dimmInfo->memoryType) {
670
/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
674
("Max. Cas Latencies (DDR): ERROR !!!\n"));
683
("Max. Cas Latencies (DDR): ERROR !!!\n"));
692
("Max. Cas Latencies (DDR): 3.5 clk's\n"));
699
("Max. Cas Latencies (DDR): 3 clk's \n"));
706
("Max. Cas Latencies (DDR): 2.5 clk's \n"));
713
("Max. Cas Latencies (DDR): 2 clk's \n"));
720
("Max. Cas Latencies (DDR): 1.5 clk's \n"));
727
maxCASlatencySupported_LoP
731
if (((5 * j) % 10) != 0)
733
maxCASlatencySupported_RoP
737
maxCASlatencySupported_RoP
740
("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
742
maxCASlatencySupported_LoP,
744
maxCASlatencySupported_RoP));
747
/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
748
dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
750
("Max. Cas Latencies (SD): %d\n",
754
maxCASlatencySupported_LoP
757
maxCASlatencySupported_RoP
760
("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
762
maxCASlatencySupported_LoP,
764
maxCASlatencySupported_RoP));
771
/*------------------------------------------------------------------------------------------------------------------------------*/
773
case 21: /* Buffered Address And Control Inputs */
774
DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
775
dimmInfo->bufferedAddrAndControlInputs =
777
dimmInfo->registeredAddrAndControlInputs =
778
(data[i] & BIT1) >> 1;
779
dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
780
dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
781
dimmInfo->registeredDQMBinputs =
782
(data[i] & BIT4) >> 4;
783
dimmInfo->differentialClockInput =
784
(data[i] & BIT5) >> 5;
785
dimmInfo->redundantRowAddressing =
786
(data[i] & BIT6) >> 6;
788
if (dimmInfo->bufferedAddrAndControlInputs == 1)
790
(" - Buffered Address/Control Input: Yes \n"));
793
(" - Buffered Address/Control Input: No \n"));
795
if (dimmInfo->registeredAddrAndControlInputs == 1)
797
(" - Registered Address/Control Input: Yes \n"));
800
(" - Registered Address/Control Input: No \n"));
802
if (dimmInfo->onCardPLL == 1)
804
(" - On-Card PLL (clock): Yes \n"));
807
(" - On-Card PLL (clock): No \n"));
809
if (dimmInfo->bufferedDQMBinputs == 1)
811
(" - Bufferd DQMB Inputs: Yes \n"));
814
(" - Bufferd DQMB Inputs: No \n"));
816
if (dimmInfo->registeredDQMBinputs == 1)
818
(" - Registered DQMB Inputs: Yes \n"));
821
(" - Registered DQMB Inputs: No \n"));
823
if (dimmInfo->differentialClockInput == 1)
825
(" - Differential Clock Input: Yes \n"));
828
(" - Differential Clock Input: No \n"));
830
if (dimmInfo->redundantRowAddressing == 1)
832
(" - redundant Row Addressing: Yes \n"));
835
(" - redundant Row Addressing: No \n"));
839
/*------------------------------------------------------------------------------------------------------------------------------*/
841
case 22: /* Suported AutoPreCharge */
842
DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
843
dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
844
dimmInfo->suportedAutoPreCharge =
845
(data[i] & BIT1) >> 1;
846
dimmInfo->suportedPreChargeAll =
847
(data[i] & BIT2) >> 2;
848
dimmInfo->suportedWrite1ReadBurst =
849
(data[i] & BIT3) >> 3;
850
dimmInfo->suported5PercentLowVCC =
851
(data[i] & BIT4) >> 4;
852
dimmInfo->suported5PercentUpperVCC =
853
(data[i] & BIT5) >> 5;
855
if (dimmInfo->suportedEarlyRasPreCharge == 1)
857
(" - Early Ras Precharge: Yes \n"));
860
(" - Early Ras Precharge: No \n"));
862
if (dimmInfo->suportedAutoPreCharge == 1)
864
(" - AutoPreCharge: Yes \n"));
867
(" - AutoPreCharge: No \n"));
869
if (dimmInfo->suportedPreChargeAll == 1)
871
(" - Precharge All: Yes \n"));
874
(" - Precharge All: No \n"));
876
if (dimmInfo->suportedWrite1ReadBurst == 1)
878
(" - Write 1/ReadBurst: Yes \n"));
881
(" - Write 1/ReadBurst: No \n"));
883
if (dimmInfo->suported5PercentLowVCC == 1)
885
(" - lower VCC tolerance: 5 Percent \n"));
888
(" - lower VCC tolerance: 10 Percent \n"));
890
if (dimmInfo->suported5PercentUpperVCC == 1)
892
(" - upper VCC tolerance: 5 Percent \n"));
895
(" - upper VCC tolerance: 10 Percent \n"));
899
/*------------------------------------------------------------------------------------------------------------------------------*/
901
case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
902
shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
903
mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
905
(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
907
(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
908
leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
909
rightOfPoint = (data[i] & maskRightOfPoint) * mult;
910
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
912
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
915
("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
916
leftOfPoint, rightOfPoint));
917
/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
919
/*------------------------------------------------------------------------------------------------------------------------------*/
921
case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
922
div = (dimmInfo->memoryType == DDR) ? 100 : 10;
924
(((data[i] & 0xf0) >> 4) * 10) +
926
leftOfPoint = time_tmp / div;
927
rightOfPoint = time_tmp % div;
928
dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
929
dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
931
("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
932
leftOfPoint, rightOfPoint));
934
/*------------------------------------------------------------------------------------------------------------------------------*/
936
case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
937
shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
938
mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
940
(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
942
(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
943
leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
944
rightOfPoint = (data[i] & maskRightOfPoint) * mult;
945
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
947
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
950
("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
951
leftOfPoint, rightOfPoint));
952
/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
954
/*------------------------------------------------------------------------------------------------------------------------------*/
956
case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
957
div = (dimmInfo->memoryType == DDR) ? 100 : 10;
959
(((data[i] & 0xf0) >> 4) * 10) +
961
leftOfPoint = time_tmp / div;
962
rightOfPoint = time_tmp % div;
963
dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
964
dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
966
("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
967
leftOfPoint, rightOfPoint));
969
/*------------------------------------------------------------------------------------------------------------------------------*/
971
case 27: /* Minimum Row Precharge Time */
972
shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
974
(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
976
(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
977
leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
978
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
980
dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
982
(dimmInfo->minRowPrechargeTime +
983
(tmemclk - 1)) / tmemclk;
985
("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
986
tmemclk, tmemclk / 100, tmemclk % 100));
988
("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
989
leftOfPoint, rightOfPoint, trp_clocks));
991
/*------------------------------------------------------------------------------------------------------------------------------*/
993
case 28: /* Minimum Row Active to Row Active Time */
994
shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
996
(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
998
(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
999
leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1000
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1002
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
1004
(dimmInfo->minRowActiveRowActiveDelay +
1005
(tmemclk - 1)) / tmemclk;
1007
("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
1008
leftOfPoint, rightOfPoint, trp_clocks));
1010
/*------------------------------------------------------------------------------------------------------------------------------*/
1012
case 29: /* Minimum Ras-To-Cas Delay */
1013
shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
1015
(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1017
(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1018
leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1019
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1021
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
1023
(dimmInfo->minRowActiveRowActiveDelay +
1024
(tmemclk - 1)) / tmemclk;
1026
("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
1027
leftOfPoint, rightOfPoint, trp_clocks));
1029
/*------------------------------------------------------------------------------------------------------------------------------*/
1031
case 30: /* Minimum Ras Pulse Width */
1032
dimmInfo->minRasPulseWidth = data[i];
1034
(NSto10PS (data[i]) +
1035
(tmemclk - 1)) / tmemclk;
1037
("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
1038
dimmInfo->minRasPulseWidth, tras_clocks));
1041
/*------------------------------------------------------------------------------------------------------------------------------*/
1043
case 31: /* Module Bank Density */
1044
dimmInfo->moduleBankDensity = data[i];
1046
("Module Bank Density: %d\n",
1047
dimmInfo->moduleBankDensity));
1050
("*** Offered Densities (more than 1 = Multisize-Module): "));
1052
if (dimmInfo->moduleBankDensity & 1)
1053
DP (printf ("4MB, "));
1054
if (dimmInfo->moduleBankDensity & 2)
1055
DP (printf ("8MB, "));
1056
if (dimmInfo->moduleBankDensity & 4)
1057
DP (printf ("16MB, "));
1058
if (dimmInfo->moduleBankDensity & 8)
1059
DP (printf ("32MB, "));
1060
if (dimmInfo->moduleBankDensity & 16)
1061
DP (printf ("64MB, "));
1062
if (dimmInfo->moduleBankDensity & 32)
1063
DP (printf ("128MB, "));
1064
if ((dimmInfo->moduleBankDensity & 64)
1065
|| (dimmInfo->moduleBankDensity & 128)) {
1066
DP (printf ("ERROR, "));
1073
/*------------------------------------------------------------------------------------------------------------------------------*/
1075
case 32: /* Address And Command Setup Time (measured in ns/1000) */
1077
switch (dimmInfo->memoryType) {
1080
(((data[i] & 0xf0) >> 4) * 10) +
1082
leftOfPoint = time_tmp / 100;
1083
rightOfPoint = time_tmp % 100;
1086
leftOfPoint = (data[i] & 0xf0) >> 4;
1087
if (leftOfPoint > 7) {
1088
leftOfPoint = data[i] & 0x70 >> 4;
1091
rightOfPoint = (data[i] & 0x0f);
1094
dimmInfo->addrAndCommandSetupTime =
1095
(leftOfPoint * 100 + rightOfPoint) * sign;
1097
("Address And Command Setup Time [ns]: %d.%d\n",
1098
sign * leftOfPoint, rightOfPoint));
1100
/*------------------------------------------------------------------------------------------------------------------------------*/
1102
case 33: /* Address And Command Hold Time */
1104
switch (dimmInfo->memoryType) {
1107
(((data[i] & 0xf0) >> 4) * 10) +
1109
leftOfPoint = time_tmp / 100;
1110
rightOfPoint = time_tmp % 100;
1113
leftOfPoint = (data[i] & 0xf0) >> 4;
1114
if (leftOfPoint > 7) {
1115
leftOfPoint = data[i] & 0x70 >> 4;
1118
rightOfPoint = (data[i] & 0x0f);
1121
dimmInfo->addrAndCommandHoldTime =
1122
(leftOfPoint * 100 + rightOfPoint) * sign;
1124
("Address And Command Hold Time [ns]: %d.%d\n",
1125
sign * leftOfPoint, rightOfPoint));
1127
/*------------------------------------------------------------------------------------------------------------------------------*/
1129
case 34: /* Data Input Setup Time */
1131
switch (dimmInfo->memoryType) {
1134
(((data[i] & 0xf0) >> 4) * 10) +
1136
leftOfPoint = time_tmp / 100;
1137
rightOfPoint = time_tmp % 100;
1140
leftOfPoint = (data[i] & 0xf0) >> 4;
1141
if (leftOfPoint > 7) {
1142
leftOfPoint = data[i] & 0x70 >> 4;
1145
rightOfPoint = (data[i] & 0x0f);
1148
dimmInfo->dataInputSetupTime =
1149
(leftOfPoint * 100 + rightOfPoint) * sign;
1151
("Data Input Setup Time [ns]: %d.%d\n",
1152
sign * leftOfPoint, rightOfPoint));
1154
/*------------------------------------------------------------------------------------------------------------------------------*/
1156
case 35: /* Data Input Hold Time */
1158
switch (dimmInfo->memoryType) {
1161
(((data[i] & 0xf0) >> 4) * 10) +
1163
leftOfPoint = time_tmp / 100;
1164
rightOfPoint = time_tmp % 100;
1167
leftOfPoint = (data[i] & 0xf0) >> 4;
1168
if (leftOfPoint > 7) {
1169
leftOfPoint = data[i] & 0x70 >> 4;
1172
rightOfPoint = (data[i] & 0x0f);
1175
dimmInfo->dataInputHoldTime =
1176
(leftOfPoint * 100 + rightOfPoint) * sign;
1178
("Data Input Hold Time [ns]: %d.%d\n\n",
1179
sign * leftOfPoint, rightOfPoint));
1181
/*------------------------------------------------------------------------------------------------------------------------------*/
1184
/* calculating the sdram density */
1186
i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1188
density = density * 2;
1190
dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1191
dimmInfo->sdramWidth;
1192
dimmInfo->numberOfDevices =
1193
(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1194
dimmInfo->numOfModuleBanks;
1195
devicesForErrCheck =
1196
(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1197
if ((dimmInfo->errorCheckType == 0x1)
1198
|| (dimmInfo->errorCheckType == 0x2)
1199
|| (dimmInfo->errorCheckType == 0x3)) {
1201
(dimmInfo->deviceDensity / 8) *
1202
(dimmInfo->numberOfDevices - devicesForErrCheck);
1205
(dimmInfo->deviceDensity / 8) *
1206
dimmInfo->numberOfDevices;
1209
/* compute the module DRB size */
1211
(dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1212
tmp *= dimmInfo->numOfModuleBanks;
1213
tmp *= dimmInfo->sdramWidth;
1214
tmp = tmp >> 24; /* div by 0x4000000 (64M) */
1215
dimmInfo->drb_size = (uchar) tmp;
1216
DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
1218
/* try a CAS latency of 3 first... */
1220
/* bit 1 is CL2, bit 2 is CL3 */
1221
supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1225
if (NS10to10PS (data[9]) <= tmemclk)
1229
if (NS10to10PS (data[9]) <= tmemclk)
1235
if (NS10to10PS (data[23]) <= tmemclk)
1239
DP (printf ("cal_val = %d\n", cal_val * 5));
1241
/* bummer, did't work... */
1243
DP (printf ("Couldn't find a good CAS latency\n"));
1251
/* sets up the GT properly with information passed in */
1252
int setup_sdram (AUX_MEM_DIMM_INFO * info)
1255
ulong tmp_sdram_mode = 0; /* 0x141c */
1256
ulong tmp_dunit_control_low = 0; /* 0x1404 */
1259
/* sanity checking */
1260
if (!info->numOfModuleBanks) {
1261
printf ("setup_sdram called with 0 banks\n");
1267
/* Program the GT with the discovered data */
1268
if (info->registeredAddrAndControlInputs == true)
1270
("Module is registered, but we do not support registered Modules !!!\n"));
1274
set_dfcdlInit (); /* may be its not needed */
1275
DP (printf ("Delay line set done\n"));
1277
/* set SDRAM mode NOP */ /* To_do check it */
1278
GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1279
while (GTREGREAD (SDRAM_OPERATION) != 0) {
1281
("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
1284
/* SDRAM configuration */
1285
GT_REG_WRITE (SDRAM_CONFIG, 0x58200400);
1286
DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
1288
/* SDRAM open pages controll keep open as much as I can */
1289
GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1291
("sdram_open_pages_controll 0x1414: %08x\n",
1292
GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
1295
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1296
tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1298
DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
1301
("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
1303
/* SDRAM set CAS Lentency according to SPD information */
1304
switch (info->memoryType) {
1306
DP (printf ("### SD-RAM not supported yet !!!\n"));
1308
/* ToDo fill SD-RAM if needed !!!!! */
1312
DP (printf ("### SET-CL for DDR-RAM\n"));
1314
switch (info->maxClSupported_DDR) {
1316
tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */
1317
tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
1319
("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1320
tmp_sdram_mode, tmp_dunit_control_low));
1324
if (tmp == 1) { /* clocks sync */
1325
tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */
1326
tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1328
("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1329
tmp_sdram_mode, tmp_dunit_control_low));
1330
} else { /* clk sync. bypassed */
1332
tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1333
tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1335
("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1336
tmp_sdram_mode, tmp_dunit_control_low));
1341
if (tmp == 1) { /* Sync */
1342
tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1343
tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1345
("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1346
tmp_sdram_mode, tmp_dunit_control_low));
1347
} else { /* Not sync. */
1349
tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */
1350
tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1352
("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1353
tmp_sdram_mode, tmp_dunit_control_low));
1358
if (tmp == 1) { /* Sync */
1359
tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */
1360
tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1362
("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1363
tmp_sdram_mode, tmp_dunit_control_low));
1364
} else { /* not sync */
1366
tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */
1367
tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1369
("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1370
tmp_sdram_mode, tmp_dunit_control_low));
1375
printf ("Max. CL is out of range %d\n",
1376
info->maxClSupported_DDR);
1383
/* Write results of CL detection procedure */
1384
GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1385
/* set SDRAM mode SetCommand 0x1418 */
1386
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1387
while (GTREGREAD (SDRAM_OPERATION) != 0) {
1389
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1393
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1394
tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1395
if (tmp != 1) { /*clocks are not sync */
1397
GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1398
(GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1399
0x18110780 | tmp_dunit_control_low);
1402
GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1403
(GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1404
0x00110000 | tmp_dunit_control_low);
1407
/* set SDRAM mode SetCommand 0x1418 */
1408
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1409
while (GTREGREAD (SDRAM_OPERATION) != 0) {
1411
("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
1414
/*------------------------------------------------------------------------------ */
1417
/* bank parameters */
1418
/* SDRAM address decode register */
1419
/* program this with the default value */
1423
DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
1424
switch (info->drb_size) {
1425
case 1: /* 64 Mbit */
1426
case 2: /* 128 Mbit */
1427
DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
1430
case 4: /* 256 Mbit */
1431
case 8: /* 512 Mbit */
1432
DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
1435
case 16: /* 1 Gbit */
1436
case 32: /* 2 Gbit */
1437
DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
1441
printf ("Error in dram size calculation\n");
1442
DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
1447
/* SDRAM bank parameters */
1448
/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1450
("setting up slot %d config with: %08lx \n", info->slot, tmp));
1451
GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1453
/* ------------------------------------------------------------------------------ */
1456
("setting up sdram_timing_control_low with: %08x \n",
1458
GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1461
/* ------------------------------------------------------------------------------ */
1463
/* SDRAM configuration */
1464
tmp = GTREGREAD (SDRAM_CONFIG);
1466
if (info->registeredAddrAndControlInputs
1467
|| info->registeredDQMBinputs) {
1470
("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1471
info->registeredAddrAndControlInputs,
1472
info->registeredDQMBinputs));
1475
/* Use buffer 1 to return read data to the CPU
1476
* Page 426 MV64360 */
1479
("Before Buffer assignment - sdram_conf: %08x\n",
1480
GTREGREAD (SDRAM_CONFIG)));
1482
("After Buffer assignment - sdram_conf: %08x\n",
1483
GTREGREAD (SDRAM_CONFIG)));
1485
/* SDRAM timing To_do: */
1488
tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1489
DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp));
1491
/* SDRAM address decode register */
1492
/* program this with the default value */
1493
tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1495
("SDRAM address control (before: decode): %08x ",
1496
GTREGREAD (SDRAM_ADDR_CONTROL)));
1497
GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1499
("SDRAM address control (after: decode): %08x\n",
1500
GTREGREAD (SDRAM_ADDR_CONTROL)));
1502
/* set the SDRAM configuration for each bank */
1504
/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1510
("\n*** Running a MRS cycle for bank %d ***\n", i));
1513
memory_map_bank (i, 0, GB / 4);
1514
#if 1 /* test only */
1516
tmp = GTREGREAD (SDRAM_MODE);
1517
GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
1518
GT_REG_WRITE (SDRAM_OPERATION, 0x4);
1519
while (GTREGREAD (SDRAM_OPERATION) != 0) {
1521
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1524
GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
1525
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1526
while (GTREGREAD (SDRAM_OPERATION) != 0) {
1528
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1532
l1 += GTREGREAD (SDRAM_OPERATION);
1534
GT_REG_WRITE (SDRAM_MODE, tmp);
1535
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1536
while (GTREGREAD (SDRAM_OPERATION) != 0) {
1538
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1541
/* switch back to normal operation mode */
1542
GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1543
while (GTREGREAD (SDRAM_OPERATION) != 0) {
1545
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1548
#endif /* test only */
1549
/* unmap the bank */
1550
memory_map_bank (i, 0, 0);
1557
* Check memory range for valid RAM. A simple memory test determines
1558
* the actually available RAM size between addresses `base' and
1559
* `base + maxsize'. Some (not all) hardware errors are detected:
1560
* - short between address lines
1561
* - short between data lines
1564
dram_size(long int *base, long int maxsize)
1566
volatile long int *addr, *b=base;
1567
long int cnt, val, save1, save2;
1569
#define STARTVAL (1<<20) /* start test at 1M */
1570
for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1571
addr = base + cnt; /* pointer arith! */
1573
save1 = *addr; /* save contents of addr */
1574
save2 = *b; /* save contents of base */
1576
*addr=cnt; /* write cnt to addr */
1577
*b=0; /* put null at base */
1579
/* check at base address */
1581
*addr=save1; /* restore *addr */
1582
*b=save2; /* restore *b */
1585
val = *addr; /* read *addr */
1586
val = *addr; /* read *addr */
1592
DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
1593
/* fix boundary condition.. STARTVAL means zero */
1594
if(cnt==STARTVAL/sizeof(long)) cnt=0;
1595
return (cnt * sizeof(long));
1601
/* ------------------------------------------------------------------------- */
1603
/* ppcboot interface function to SDRAM init - this is where all the
1604
* controlling logic happens */
1606
initdram(int board_type)
1609
int checkbank[4] = { [0 ... 3] = 0 };
1610
ulong bank_no, realsize, total, check;
1611
AUX_MEM_DIMM_INFO dimmInfo1;
1612
AUX_MEM_DIMM_INFO dimmInfo2;
1615
/* first, use the SPD to get info about the SDRAM/ DDRRAM */
1617
/* check the NHR bit and skip mem init if it's already done */
1618
nhr = get_hid0() & (1 << 16);
1621
printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1624
s0 = check_dimm(0, &dimmInfo1);
1627
s1 = check_dimm(1, &dimmInfo2);
1629
memory_map_bank(0, 0, 0);
1630
memory_map_bank(1, 0, 0);
1631
memory_map_bank(2, 0, 0);
1632
memory_map_bank(3, 0, 0);
1634
if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1635
printf("Setup for DIMM1 failed.\n");
1638
if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1639
printf("Setup for DIMM2 failed.\n");
1642
/* set the NHR bit */
1643
set_hid0(get_hid0() | (1 << 16));
1645
/* next, size the SDRAM banks */
1647
realsize = total = 0;
1649
if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1650
if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1651
if (dimmInfo1.numOfModuleBanks > 2)
1652
printf("Error, SPD claims DIMM1 has >2 banks\n");
1654
if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1655
if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1656
if (dimmInfo2.numOfModuleBanks > 2)
1657
printf("Error, SPD claims DIMM2 has >2 banks\n");
1659
for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1660
/* skip over banks that are not populated */
1661
if (! checkbank[bank_no])
1664
if ((total + check) > CONFIG_SYS_GT_REGS)
1665
check = CONFIG_SYS_GT_REGS - total;
1667
memory_map_bank(bank_no, total, check);
1668
realsize = dram_size((long int *)total, check);
1669
memory_map_bank(bank_no, total, realsize);
1674
/* Setup Ethernet DMA Adress window to DRAM Area */
1678
/* ***************************************************************************************
1680
! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
1681
! * This procedure fits only the Atlantis *
1683
! *************************************************************************************** */
1686
/* ***************************************************************************************
1687
! * DFCDL initialize MV643xx Design Considerations *
1689
! *************************************************************************************** */
1690
int set_dfcdlInit (void)
1693
unsigned int dfcdl_word = 0x0000014f;
1695
for (i = 0; i < 64; i++) {
1696
GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1698
GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
added
removed
board/esd/cpci750/sdram_init.c
