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* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* See file CREDITS for list of people who contributed to this
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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#include <asm/timer.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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static volatile ulong timestamp = 0;
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#ifndef CONFIG_SYS_WATCHDOG_FREQ
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#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
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#if defined(CONFIG_MCFTMR)
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#ifndef CONFIG_SYS_UDELAY_BASE
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# error "uDelay base not defined!"
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#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
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# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
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extern void dtimer_intr_setup(void);
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void __udelay(unsigned long usec)
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volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
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/* Set up TIMER 3 as timebase clock */
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timerp->tmr = DTIM_DTMR_RST_RST;
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/* set period to 1 us */
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CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
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start = now = timerp->tcn;
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while (now < start + tmp)
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void dtimer_interrupt(void *not_used)
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volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
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/* check for timer interrupt asserted */
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if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
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timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
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#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
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if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
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#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
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volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
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/* Set up TIMER 4 as clock */
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timerp->tmr = DTIM_DTMR_RST_RST;
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/* initialize and enable timer interrupt */
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irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
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timerp->trr = 1000; /* Interrupt every ms */
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
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DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
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void reset_timer(void)
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ulong get_timer(ulong base)
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return (timestamp - base);
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void set_timer(ulong t)
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#endif /* CONFIG_MCFTMR */
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#if defined(CONFIG_MCFPIT)
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#if !defined(CONFIG_SYS_PIT_BASE)
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# error "CONFIG_SYS_PIT_BASE not defined!"
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static unsigned short lastinc;
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void __udelay(unsigned long usec)
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volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
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/* Set up TIMER 3 as timebase clock */
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timerp->pcsr = PIT_PCSR_OVW;
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/* set period to 1 us */
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timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
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while (timerp->pcntr > 0) ;
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void timer_init(void)
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volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
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/* Set up TIMER 4 as poll clock */
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timerp->pcsr = PIT_PCSR_OVW;
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timerp->pmr = lastinc = 0;
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timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
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void set_timer(ulong t)
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volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
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timerp->pmr = lastinc = 0;
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ulong get_timer(ulong base)
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unsigned short now, diff;
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volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
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diff = -(now - lastinc);
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return timestamp - base;
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void wait_ticks(unsigned long ticks)
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while (get_timer(0) < ticks) ;
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#endif /* CONFIG_MCFPIT */
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* This function is derived from PowerPC code (read timebase as long long).
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* On M68K it just returns the timer value.
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unsigned long long get_ticks(void)
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unsigned long usec2ticks(unsigned long usec)
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return get_timer(usec);
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* This function is derived from PowerPC code (timebase clock frequency).
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* On M68K it returns the number of timer ticks per second.
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ulong get_tbclk(void)
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tbclk = CONFIG_SYS_HZ;