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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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#include <asm/macro.h>
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#include <asm/arch/ftsdmc020.h>
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* parameters for the SDRAM controller
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#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
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#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
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#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
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#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
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#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
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#define TP0_D CONFIG_SYS_FTSDMC020_TP0
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#define TP1_D CONFIG_SYS_FTSDMC020_TP1
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#define CR_D1 FTSDMC020_CR_IPREC
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#define CR_D2 FTSDMC020_CR_ISMR
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#define CR_D3 FTSDMC020_CR_IREF
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#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
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FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
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#define ACR_D FTSDMC020_ACR_TOC(0x18)
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* numeric 7 segment display
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write32 CONFIG_DEBUG_LED, \num
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* Waiting for SDRAM to set up
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ldr r0, =CONFIG_FTSDMC020_BASE
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ldr r1, [r0, #FTSDMC020_OFFSET_CR]
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/* everything is fine now */
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* memory initialization
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/* set SDRAM register */
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/* set to precharge */
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/* set mode register */
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write32 B0_BSR_A, B0_BSR_D