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  • Committer: Bazaar Package Importer
  • Author(s): Oliver Grawert
  • Date: 2010-03-22 15:06:23 UTC
  • Revision ID: james.westby@ubuntu.com-20100322150623-i21g8rgiyl5dohag
Tags: upstream-2010.3git20100315
Import upstream version 2010.3git20100315

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board/pm854/tlb.c
 
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/*
 
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 * Copyright 2008 Freescale Semiconductor, Inc.
 
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 *
 
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 * (C) Copyright 2000
 
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 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
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 *
 
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 * See file CREDITS for list of people who contributed to this
 
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 * project.
 
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 *
 
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 * This program is free software; you can redistribute it and/or
 
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 * modify it under the terms of the GNU General Public License as
 
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 * published by the Free Software Foundation; either version 2 of
 
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 * the License, or (at your option) any later version.
 
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 *
 
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 * This program is distributed in the hope that it will be useful,
 
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
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 * GNU General Public License for more details.
 
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 *
 
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 * You should have received a copy of the GNU General Public License
 
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 * along with this program; if not, write to the Free Software
 
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 
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 * MA 02111-1307 USA
 
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 */
 
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#include <common.h>
 
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#include <asm/mmu.h>
 
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struct fsl_e_tlb_entry tlb_table[] = {
 
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        /* TLB 0 - for temp stack in cache */
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        /*
 
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         * TLB 0:       64M     Non-cacheable, guarded
 
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         * 0xfc000000   64M     FLASH (8,16,32 or 64 MB)
 
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         * Out of reset this entry is only 4K.
 
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         */
 
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        SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 0, BOOKE_PAGESZ_16M, 1),
 
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        /*
 
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         * TLB 1:       256M    Non-cacheable, guarded
 
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         * 0x80000000   256M    PCI1 MEM First half
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 1, BOOKE_PAGESZ_256M, 1),
 
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        /*
 
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         * TLB 2:       256M    Non-cacheable, guarded
 
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         * 0x90000000   256M    PCI1 MEM Second half
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 2, BOOKE_PAGESZ_256M, 1),
 
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        /*
 
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         * TLB 3:       256M    Non-cacheable, guarded
 
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         * 0xc0000000   256M    Rapid IO MEM First half
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 3, BOOKE_PAGESZ_256M, 1),
 
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        /*
 
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         * TLB 4:       256M    Non-cacheable, guarded
 
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         * 0xd0000000   256M    Rapid IO MEM Second half
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 4, BOOKE_PAGESZ_256M, 1),
 
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        /*
 
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         * TLB 5:       64M     Non-cacheable, guarded
 
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         * 0xe000_0000  1M      CCSRBAR
 
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         * 0xe200_0000  16M     PCI1 IO
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 5, BOOKE_PAGESZ_64M, 1),
 
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        /*
 
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         * TLB 6:       64M     Cacheable, non-guarded
 
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         * 0xf000_0000  64M     LBC SDRAM
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 6, BOOKE_PAGESZ_64M, 1),
 
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#if !defined(CONFIG_SPD_EEPROM)
 
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        /*
 
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         * TLB 7:       256M    DDR
 
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         * 0x00000000   256M    DDR System memory
 
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         * Without SPD EEPROM configured DDR, this must be setup manually.
 
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         * Make sure the TLB count at the top of this table is correct.
 
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         * Likely it needs to be increased by two for these entries.
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 7, BOOKE_PAGESZ_256M, 1),
 
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#endif
 
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};
 
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int num_tlb_entries = ARRAY_SIZE(tlb_table);