4
* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6
* This library is free software; you can redistribute it and/or
7
* modify it under the terms of the GNU Lesser General Public
8
* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
11
* This library is distributed in the hope that it will be useful,
12
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
17
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
28
#include "translate.h"
29
#include "qemu/host-utils.h"
31
#include "exec/gen-icount.h"
37
static TCGv_i64 cpu_X[32];
38
static TCGv_i64 cpu_pc;
39
static TCGv_i32 pstate;
41
static const char *regnames[] = {
42
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
44
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
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"x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
48
/* initialize TCG globals. */
49
void a64_translate_init(void)
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cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
54
offsetof(CPUARMState, pc),
56
for (i = 0; i < 32; i++) {
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cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, xregs[i]),
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pstate = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUARMState, pstate),
67
void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
68
fprintf_function cpu_fprintf, int flags)
70
ARMCPU *cpu = ARM_CPU(cs);
71
CPUARMState *env = &cpu->env;
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uint32_t psr = pstate_read(env);
75
cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
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env->pc, env->xregs[31]);
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
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cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
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psr & PSTATE_N ? 'N' : '-',
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psr & PSTATE_Z ? 'Z' : '-',
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psr & PSTATE_C ? 'C' : '-',
90
psr & PSTATE_V ? 'V' : '-');
94
void gen_a64_set_pc_im(uint64_t val)
96
tcg_gen_movi_i64(cpu_pc, val);
99
static void gen_exception(int excp)
101
TCGv_i32 tmp = tcg_temp_new_i32();
102
tcg_gen_movi_i32(tmp, excp);
103
gen_helper_exception(cpu_env, tmp);
104
tcg_temp_free_i32(tmp);
107
static void gen_exception_insn(DisasContext *s, int offset, int excp)
109
gen_a64_set_pc_im(s->pc - offset);
111
s->is_jmp = DISAS_EXC;
114
static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
116
/* No direct tb linking with singlestep or deterministic io */
117
if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
121
/* Only link tbs from inside the same guest page */
122
if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
129
static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
131
TranslationBlock *tb;
134
if (use_goto_tb(s, n, dest)) {
136
gen_a64_set_pc_im(dest);
137
tcg_gen_exit_tb((tcg_target_long)tb + n);
138
s->is_jmp = DISAS_TB_JUMP;
140
gen_a64_set_pc_im(dest);
141
if (s->singlestep_enabled) {
142
gen_exception(EXCP_DEBUG);
145
s->is_jmp = DISAS_JUMP;
149
static void unallocated_encoding(DisasContext *s)
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gen_exception_insn(s, 4, EXCP_UDEF);
154
#define unsupported_encoding(s, insn) \
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qemu_log_mask(LOG_UNIMP, \
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"%s:%d: unsupported instruction encoding 0x%08x " \
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"at pc=%016" PRIx64 "\n", \
159
__FILE__, __LINE__, insn, s->pc - 4); \
160
unallocated_encoding(s); \
164
* the instruction disassembly implemented here matches
165
* the instruction encoding classifications in chapter 3 (C3)
166
* of the ARM Architecture Reference Manual (DDI0487A_a)
169
/* Unconditional branch (immediate) */
170
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
172
unsupported_encoding(s, insn);
175
/* Compare & branch (immediate) */
176
static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
178
unsupported_encoding(s, insn);
181
/* Test & branch (immediate) */
182
static void disas_test_b_imm(DisasContext *s, uint32_t insn)
184
unsupported_encoding(s, insn);
187
/* Conditional branch (immediate) */
188
static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
190
unsupported_encoding(s, insn);
194
static void disas_system(DisasContext *s, uint32_t insn)
196
unsupported_encoding(s, insn);
199
/* Exception generation */
200
static void disas_exc(DisasContext *s, uint32_t insn)
202
unsupported_encoding(s, insn);
205
/* Unconditional branch (register) */
206
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
208
unsupported_encoding(s, insn);
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/* C3.2 Branches, exception generating and system instructions */
212
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
214
switch (extract32(insn, 25, 7)) {
215
case 0x0a: case 0x0b:
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case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
217
disas_uncond_b_imm(s, insn);
219
case 0x1a: case 0x5a: /* Compare & branch (immediate) */
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disas_comp_b_imm(s, insn);
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case 0x1b: case 0x5b: /* Test & branch (immediate) */
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disas_test_b_imm(s, insn);
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case 0x2a: /* Conditional branch (immediate) */
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disas_cond_b_imm(s, insn);
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case 0x6a: /* Exception generation / System */
229
if (insn & (1 << 24)) {
230
disas_system(s, insn);
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case 0x6b: /* Unconditional branch (register) */
236
disas_uncond_b_reg(s, insn);
239
unallocated_encoding(s);
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/* Load/store exclusive */
245
static void disas_ldst_excl(DisasContext *s, uint32_t insn)
247
unsupported_encoding(s, insn);
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/* Load register (literal) */
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static void disas_ld_lit(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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/* Load/store pair (all forms) */
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static void disas_ldst_pair(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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/* Load/store register (all forms) */
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static void disas_ldst_reg(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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/* AdvSIMD load/store multiple structures */
269
static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
271
unsupported_encoding(s, insn);
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/* AdvSIMD load/store single structure */
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static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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/* C3.3 Loads and stores */
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static void disas_ldst(DisasContext *s, uint32_t insn)
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switch (extract32(insn, 24, 6)) {
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case 0x08: /* Load/store exclusive */
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disas_ldst_excl(s, insn);
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case 0x18: case 0x1c: /* Load register (literal) */
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disas_ld_lit(s, insn);
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case 0x28: case 0x29:
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case 0x2c: case 0x2d: /* Load/store pair (all forms) */
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disas_ldst_pair(s, insn);
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case 0x38: case 0x39:
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case 0x3c: case 0x3d: /* Load/store register (all forms) */
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disas_ldst_reg(s, insn);
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case 0x0c: /* AdvSIMD load/store multiple structures */
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disas_ldst_multiple_struct(s, insn);
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case 0x0d: /* AdvSIMD load/store single structure */
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disas_ldst_single_struct(s, insn);
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unallocated_encoding(s);
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/* PC-rel. addressing */
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static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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/* Add/subtract (immediate) */
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static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
319
unsupported_encoding(s, insn);
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/* Logical (immediate) */
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static void disas_logic_imm(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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/* Move wide (immediate) */
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static void disas_movw_imm(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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static void disas_bitfield(DisasContext *s, uint32_t insn)
337
unsupported_encoding(s, insn);
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static void disas_extract(DisasContext *s, uint32_t insn)
343
unsupported_encoding(s, insn);
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/* C3.4 Data processing - immediate */
347
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
349
switch (extract32(insn, 23, 6)) {
350
case 0x20: case 0x21: /* PC-rel. addressing */
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disas_pc_rel_adr(s, insn);
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case 0x22: case 0x23: /* Add/subtract (immediate) */
354
disas_add_sub_imm(s, insn);
356
case 0x24: /* Logical (immediate) */
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disas_logic_imm(s, insn);
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case 0x25: /* Move wide (immediate) */
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disas_movw_imm(s, insn);
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case 0x26: /* Bitfield */
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disas_bitfield(s, insn);
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case 0x27: /* Extract */
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disas_extract(s, insn);
369
unallocated_encoding(s);
374
/* Logical (shifted register) */
375
static void disas_logic_reg(DisasContext *s, uint32_t insn)
377
unsupported_encoding(s, insn);
380
/* Add/subtract (extended register) */
381
static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
383
unsupported_encoding(s, insn);
386
/* Add/subtract (shifted register) */
387
static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
389
unsupported_encoding(s, insn);
392
/* Data-processing (3 source) */
393
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
395
unsupported_encoding(s, insn);
398
/* Add/subtract (with carry) */
399
static void disas_adc_sbc(DisasContext *s, uint32_t insn)
401
unsupported_encoding(s, insn);
404
/* Conditional compare (immediate) */
405
static void disas_cc_imm(DisasContext *s, uint32_t insn)
407
unsupported_encoding(s, insn);
410
/* Conditional compare (register) */
411
static void disas_cc_reg(DisasContext *s, uint32_t insn)
413
unsupported_encoding(s, insn);
416
/* Conditional select */
417
static void disas_cond_select(DisasContext *s, uint32_t insn)
419
unsupported_encoding(s, insn);
422
/* Data-processing (1 source) */
423
static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
425
unsupported_encoding(s, insn);
428
/* Data-processing (2 source) */
429
static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
431
unsupported_encoding(s, insn);
434
/* C3.5 Data processing - register */
435
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
437
switch (extract32(insn, 24, 5)) {
438
case 0x0a: /* Logical (shifted register) */
439
disas_logic_reg(s, insn);
441
case 0x0b: /* Add/subtract */
442
if (insn & (1 << 21)) { /* (extended register) */
443
disas_add_sub_ext_reg(s, insn);
445
disas_add_sub_reg(s, insn);
448
case 0x1b: /* Data-processing (3 source) */
449
disas_data_proc_3src(s, insn);
452
switch (extract32(insn, 21, 3)) {
453
case 0x0: /* Add/subtract (with carry) */
454
disas_adc_sbc(s, insn);
456
case 0x2: /* Conditional compare */
457
if (insn & (1 << 11)) { /* (immediate) */
458
disas_cc_imm(s, insn);
459
} else { /* (register) */
460
disas_cc_reg(s, insn);
463
case 0x4: /* Conditional select */
464
disas_cond_select(s, insn);
466
case 0x6: /* Data-processing */
467
if (insn & (1 << 30)) { /* (1 source) */
468
disas_data_proc_1src(s, insn);
469
} else { /* (2 source) */
470
disas_data_proc_2src(s, insn);
474
unallocated_encoding(s);
479
unallocated_encoding(s);
484
/* C3.6 Data processing - SIMD and floating point */
485
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
487
unsupported_encoding(s, insn);
490
/* C3.1 A64 instruction index by encoding */
491
static void disas_a64_insn(CPUARMState *env, DisasContext *s)
495
insn = arm_ldl_code(env, s->pc, s->bswap_code);
499
switch (extract32(insn, 25, 4)) {
500
case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
501
unallocated_encoding(s);
503
case 0x8: case 0x9: /* Data processing - immediate */
504
disas_data_proc_imm(s, insn);
506
case 0xa: case 0xb: /* Branch, exception generation and system insns */
507
disas_b_exc_sys(s, insn);
512
case 0xe: /* Loads and stores */
516
case 0xd: /* Data processing - register */
517
disas_data_proc_reg(s, insn);
520
case 0xf: /* Data processing - SIMD and floating point */
521
disas_data_proc_simd_fp(s, insn);
524
assert(FALSE); /* all 15 cases should be handled above */
529
void gen_intermediate_code_internal_a64(ARMCPU *cpu,
530
TranslationBlock *tb,
533
CPUState *cs = CPU(cpu);
534
CPUARMState *env = &cpu->env;
535
DisasContext dc1, *dc = &dc1;
537
uint16_t *gen_opc_end;
539
target_ulong pc_start;
540
target_ulong next_page_start;
548
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
550
dc->is_jmp = DISAS_NEXT;
552
dc->singlestep_enabled = cs->singlestep_enabled;
558
dc->condexec_mask = 0;
559
dc->condexec_cond = 0;
560
#if !defined(CONFIG_USER_ONLY)
567
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
570
max_insns = tb->cflags & CF_COUNT_MASK;
571
if (max_insns == 0) {
572
max_insns = CF_COUNT_MASK;
577
tcg_clear_temp_count();
580
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
581
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
582
if (bp->pc == dc->pc) {
583
gen_exception_insn(dc, 0, EXCP_DEBUG);
584
/* Advance PC so that clearing the breakpoint will
585
invalidate this TB. */
587
goto done_generating;
593
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
597
tcg_ctx.gen_opc_instr_start[lj++] = 0;
600
tcg_ctx.gen_opc_pc[lj] = dc->pc;
601
tcg_ctx.gen_opc_instr_start[lj] = 1;
602
tcg_ctx.gen_opc_icount[lj] = num_insns;
605
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
609
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
610
tcg_gen_debug_insn_start(dc->pc);
613
disas_a64_insn(env, dc);
615
if (tcg_check_temp_count()) {
616
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
620
/* Translation stops when a conditional branch is encountered.
621
* Otherwise the subsequent code could get translated several times.
622
* Also stop translation when a page boundary is reached. This
623
* ensures prefetch aborts occur at the right place.
626
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
627
!cs->singlestep_enabled &&
629
dc->pc < next_page_start &&
630
num_insns < max_insns);
632
if (tb->cflags & CF_LAST_IO) {
636
if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
637
/* Note that this means single stepping WFI doesn't halt the CPU.
638
* For conditional branch insns this is harmless unreachable code as
639
* gen_goto_tb() has already handled emitting the debug exception
640
* (and thus a tb-jump is not possible when singlestepping).
642
assert(dc->is_jmp != DISAS_TB_JUMP);
643
if (dc->is_jmp != DISAS_JUMP) {
644
gen_a64_set_pc_im(dc->pc);
646
gen_exception(EXCP_DEBUG);
648
switch (dc->is_jmp) {
650
gen_goto_tb(dc, 1, dc->pc);
655
/* indicate that the hash table must be used to find the next TB */
663
/* This is a special case because we don't want to just halt the CPU
664
* if trying to debug across a WFI.
666
gen_helper_wfi(cpu_env);
672
gen_tb_end(tb, num_insns);
673
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
676
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
677
qemu_log("----------------\n");
678
qemu_log("IN: %s\n", lookup_symbol(pc_start));
679
log_target_disas(env, pc_start, dc->pc - pc_start,
680
dc->thumb | (dc->bswap_code << 1));
685
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
688
tcg_ctx.gen_opc_instr_start[lj++] = 0;
691
tb->size = dc->pc - pc_start;
692
tb->icount = num_insns;