4
* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6
* This library is free software; you can redistribute it and/or
7
* modify it under the terms of the GNU Lesser General Public
8
* License as published by the Free Software Foundation; either
9
* version 2 of the License, or (at your option) any later version.
11
* This library is distributed in the hope that it will be useful,
12
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14
* Lesser General Public License for more details.
16
* You should have received a copy of the GNU Lesser General Public
17
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
28
#include "translate.h"
29
#include "qemu/host-utils.h"
31
#include "exec/gen-icount.h"
37
static TCGv_i64 cpu_X[32];
38
static TCGv_i64 cpu_pc;
39
static TCGv_i32 pstate;
41
static const char *regnames[] = {
42
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
43
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
44
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
45
"x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
48
/* initialize TCG globals. */
49
void a64_translate_init(void)
53
cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
54
offsetof(CPUARMState, pc),
56
for (i = 0; i < 32; i++) {
57
cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
58
offsetof(CPUARMState, xregs[i]),
62
pstate = tcg_global_mem_new_i32(TCG_AREG0,
63
offsetof(CPUARMState, pstate),
67
void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
68
fprintf_function cpu_fprintf, int flags)
70
ARMCPU *cpu = ARM_CPU(cs);
71
CPUARMState *env = &cpu->env;
72
uint32_t psr = pstate_read(env);
75
cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
76
env->pc, env->xregs[31]);
77
for (i = 0; i < 31; i++) {
78
cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
85
cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
87
psr & PSTATE_N ? 'N' : '-',
88
psr & PSTATE_Z ? 'Z' : '-',
89
psr & PSTATE_C ? 'C' : '-',
90
psr & PSTATE_V ? 'V' : '-');
94
void gen_a64_set_pc_im(uint64_t val)
96
tcg_gen_movi_i64(cpu_pc, val);
99
static void gen_exception(int excp)
101
TCGv_i32 tmp = tcg_temp_new_i32();
102
tcg_gen_movi_i32(tmp, excp);
103
gen_helper_exception(cpu_env, tmp);
104
tcg_temp_free_i32(tmp);
107
static void gen_exception_insn(DisasContext *s, int offset, int excp)
109
gen_a64_set_pc_im(s->pc - offset);
111
s->is_jmp = DISAS_EXC;
114
static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
116
/* No direct tb linking with singlestep or deterministic io */
117
if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
121
/* Only link tbs from inside the same guest page */
122
if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
129
static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
131
TranslationBlock *tb;
134
if (use_goto_tb(s, n, dest)) {
136
gen_a64_set_pc_im(dest);
137
tcg_gen_exit_tb((tcg_target_long)tb + n);
138
s->is_jmp = DISAS_TB_JUMP;
140
gen_a64_set_pc_im(dest);
141
if (s->singlestep_enabled) {
142
gen_exception(EXCP_DEBUG);
145
s->is_jmp = DISAS_JUMP;
149
static void unallocated_encoding(DisasContext *s)
151
gen_exception_insn(s, 4, EXCP_UDEF);
154
#define unsupported_encoding(s, insn) \
156
qemu_log_mask(LOG_UNIMP, \
157
"%s:%d: unsupported instruction encoding 0x%08x " \
158
"at pc=%016" PRIx64 "\n", \
159
__FILE__, __LINE__, insn, s->pc - 4); \
160
unallocated_encoding(s); \
163
static void init_tmp_a64_array(DisasContext *s)
165
#ifdef CONFIG_DEBUG_TCG
167
for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
168
TCGV_UNUSED_I64(s->tmp_a64[i]);
171
s->tmp_a64_count = 0;
174
static void free_tmp_a64(DisasContext *s)
177
for (i = 0; i < s->tmp_a64_count; i++) {
178
tcg_temp_free_i64(s->tmp_a64[i]);
180
init_tmp_a64_array(s);
183
static TCGv_i64 new_tmp_a64(DisasContext *s)
185
assert(s->tmp_a64_count < TMP_A64_MAX);
186
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
189
static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
191
TCGv_i64 t = new_tmp_a64(s);
192
tcg_gen_movi_i64(t, 0);
196
static TCGv_i64 cpu_reg(DisasContext *s, int reg)
199
return new_tmp_a64_zero(s);
206
* the instruction disassembly implemented here matches
207
* the instruction encoding classifications in chapter 3 (C3)
208
* of the ARM Architecture Reference Manual (DDI0487A_a)
211
/* C3.2.7 Unconditional branch (immediate)
213
* +----+-----------+-------------------------------------+
214
* | op | 0 0 1 0 1 | imm26 |
215
* +----+-----------+-------------------------------------+
217
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
219
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
221
if (insn & (1 << 31)) {
222
/* C5.6.26 BL Branch with link */
223
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
226
/* C5.6.20 B Branch / C5.6.26 BL Branch with link */
227
gen_goto_tb(s, 0, addr);
230
/* Compare & branch (immediate) */
231
static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
233
unsupported_encoding(s, insn);
236
/* Test & branch (immediate) */
237
static void disas_test_b_imm(DisasContext *s, uint32_t insn)
239
unsupported_encoding(s, insn);
242
/* Conditional branch (immediate) */
243
static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
245
unsupported_encoding(s, insn);
249
static void handle_hint(DisasContext *s, uint32_t insn,
250
unsigned int op1, unsigned int op2, unsigned int crm)
252
unsigned int selector = crm << 3 | op2;
255
unallocated_encoding(s);
267
/* we treat all as NOP at least for now */
270
/* default specified as NOP equivalent */
275
/* CLREX, DSB, DMB, ISB */
276
static void handle_sync(DisasContext *s, uint32_t insn,
277
unsigned int op1, unsigned int op2, unsigned int crm)
280
unallocated_encoding(s);
286
unsupported_encoding(s, insn);
291
/* We don't emulate caches so barriers are no-ops */
294
unallocated_encoding(s);
299
/* C5.6.130 MSR (immediate) - move immediate to processor state field */
300
static void handle_msr_i(DisasContext *s, uint32_t insn,
301
unsigned int op1, unsigned int op2, unsigned int crm)
303
unsupported_encoding(s, insn);
307
static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l,
308
unsigned int op1, unsigned int op2,
309
unsigned int crn, unsigned int crm, unsigned int rt)
311
unsupported_encoding(s, insn);
314
/* C5.6.129 MRS - move from system register */
315
static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0,
316
unsigned int op1, unsigned int op2,
317
unsigned int crn, unsigned int crm, unsigned int rt)
319
unsupported_encoding(s, insn);
322
/* C5.6.131 MSR (register) - move to system register */
323
static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0,
324
unsigned int op1, unsigned int op2,
325
unsigned int crn, unsigned int crm, unsigned int rt)
327
unsupported_encoding(s, insn);
331
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
332
* +---------------------+---+-----+-----+-------+-------+-----+------+
333
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
334
* +---------------------+---+-----+-----+-------+-------+-----+------+
336
static void disas_system(DisasContext *s, uint32_t insn)
338
unsigned int l, op0, op1, crn, crm, op2, rt;
339
l = extract32(insn, 21, 1);
340
op0 = extract32(insn, 19, 2);
341
op1 = extract32(insn, 16, 3);
342
crn = extract32(insn, 12, 4);
343
crm = extract32(insn, 8, 4);
344
op2 = extract32(insn, 5, 3);
345
rt = extract32(insn, 0, 5);
349
unallocated_encoding(s);
353
case 2: /* C5.6.68 HINT */
354
handle_hint(s, insn, op1, op2, crm);
356
case 3: /* CLREX, DSB, DMB, ISB */
357
handle_sync(s, insn, op1, op2, crm);
359
case 4: /* C5.6.130 MSR (immediate) */
360
handle_msr_i(s, insn, op1, op2, crm);
363
unallocated_encoding(s);
371
handle_sys(s, insn, l, op1, op2, crn, crm, rt);
372
} else if (l) { /* op0 > 1 */
373
/* C5.6.129 MRS - move from system register */
374
handle_mrs(s, insn, op0, op1, op2, crn, crm, rt);
376
/* C5.6.131 MSR (register) - move to system register */
377
handle_msr(s, insn, op0, op1, op2, crn, crm, rt);
381
/* Exception generation */
382
static void disas_exc(DisasContext *s, uint32_t insn)
384
unsupported_encoding(s, insn);
387
/* Unconditional branch (register) */
388
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
390
unsupported_encoding(s, insn);
393
/* C3.2 Branches, exception generating and system instructions */
394
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
396
switch (extract32(insn, 25, 7)) {
397
case 0x0a: case 0x0b:
398
case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
399
disas_uncond_b_imm(s, insn);
401
case 0x1a: case 0x5a: /* Compare & branch (immediate) */
402
disas_comp_b_imm(s, insn);
404
case 0x1b: case 0x5b: /* Test & branch (immediate) */
405
disas_test_b_imm(s, insn);
407
case 0x2a: /* Conditional branch (immediate) */
408
disas_cond_b_imm(s, insn);
410
case 0x6a: /* Exception generation / System */
411
if (insn & (1 << 24)) {
412
disas_system(s, insn);
417
case 0x6b: /* Unconditional branch (register) */
418
disas_uncond_b_reg(s, insn);
421
unallocated_encoding(s);
426
/* Load/store exclusive */
427
static void disas_ldst_excl(DisasContext *s, uint32_t insn)
429
unsupported_encoding(s, insn);
432
/* Load register (literal) */
433
static void disas_ld_lit(DisasContext *s, uint32_t insn)
435
unsupported_encoding(s, insn);
438
/* Load/store pair (all forms) */
439
static void disas_ldst_pair(DisasContext *s, uint32_t insn)
441
unsupported_encoding(s, insn);
444
/* Load/store register (all forms) */
445
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
447
unsupported_encoding(s, insn);
450
/* AdvSIMD load/store multiple structures */
451
static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
453
unsupported_encoding(s, insn);
456
/* AdvSIMD load/store single structure */
457
static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
459
unsupported_encoding(s, insn);
462
/* C3.3 Loads and stores */
463
static void disas_ldst(DisasContext *s, uint32_t insn)
465
switch (extract32(insn, 24, 6)) {
466
case 0x08: /* Load/store exclusive */
467
disas_ldst_excl(s, insn);
469
case 0x18: case 0x1c: /* Load register (literal) */
470
disas_ld_lit(s, insn);
472
case 0x28: case 0x29:
473
case 0x2c: case 0x2d: /* Load/store pair (all forms) */
474
disas_ldst_pair(s, insn);
476
case 0x38: case 0x39:
477
case 0x3c: case 0x3d: /* Load/store register (all forms) */
478
disas_ldst_reg(s, insn);
480
case 0x0c: /* AdvSIMD load/store multiple structures */
481
disas_ldst_multiple_struct(s, insn);
483
case 0x0d: /* AdvSIMD load/store single structure */
484
disas_ldst_single_struct(s, insn);
487
unallocated_encoding(s);
492
/* PC-rel. addressing */
493
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
495
unsupported_encoding(s, insn);
498
/* Add/subtract (immediate) */
499
static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
501
unsupported_encoding(s, insn);
504
/* Logical (immediate) */
505
static void disas_logic_imm(DisasContext *s, uint32_t insn)
507
unsupported_encoding(s, insn);
510
/* Move wide (immediate) */
511
static void disas_movw_imm(DisasContext *s, uint32_t insn)
513
unsupported_encoding(s, insn);
517
static void disas_bitfield(DisasContext *s, uint32_t insn)
519
unsupported_encoding(s, insn);
523
static void disas_extract(DisasContext *s, uint32_t insn)
525
unsupported_encoding(s, insn);
528
/* C3.4 Data processing - immediate */
529
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
531
switch (extract32(insn, 23, 6)) {
532
case 0x20: case 0x21: /* PC-rel. addressing */
533
disas_pc_rel_adr(s, insn);
535
case 0x22: case 0x23: /* Add/subtract (immediate) */
536
disas_add_sub_imm(s, insn);
538
case 0x24: /* Logical (immediate) */
539
disas_logic_imm(s, insn);
541
case 0x25: /* Move wide (immediate) */
542
disas_movw_imm(s, insn);
544
case 0x26: /* Bitfield */
545
disas_bitfield(s, insn);
547
case 0x27: /* Extract */
548
disas_extract(s, insn);
551
unallocated_encoding(s);
556
/* Logical (shifted register) */
557
static void disas_logic_reg(DisasContext *s, uint32_t insn)
559
unsupported_encoding(s, insn);
562
/* Add/subtract (extended register) */
563
static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
565
unsupported_encoding(s, insn);
568
/* Add/subtract (shifted register) */
569
static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
571
unsupported_encoding(s, insn);
574
/* Data-processing (3 source) */
575
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
577
unsupported_encoding(s, insn);
580
/* Add/subtract (with carry) */
581
static void disas_adc_sbc(DisasContext *s, uint32_t insn)
583
unsupported_encoding(s, insn);
586
/* Conditional compare (immediate) */
587
static void disas_cc_imm(DisasContext *s, uint32_t insn)
589
unsupported_encoding(s, insn);
592
/* Conditional compare (register) */
593
static void disas_cc_reg(DisasContext *s, uint32_t insn)
595
unsupported_encoding(s, insn);
598
/* Conditional select */
599
static void disas_cond_select(DisasContext *s, uint32_t insn)
601
unsupported_encoding(s, insn);
604
/* Data-processing (1 source) */
605
static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
607
unsupported_encoding(s, insn);
610
/* Data-processing (2 source) */
611
static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
613
unsupported_encoding(s, insn);
616
/* C3.5 Data processing - register */
617
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
619
switch (extract32(insn, 24, 5)) {
620
case 0x0a: /* Logical (shifted register) */
621
disas_logic_reg(s, insn);
623
case 0x0b: /* Add/subtract */
624
if (insn & (1 << 21)) { /* (extended register) */
625
disas_add_sub_ext_reg(s, insn);
627
disas_add_sub_reg(s, insn);
630
case 0x1b: /* Data-processing (3 source) */
631
disas_data_proc_3src(s, insn);
634
switch (extract32(insn, 21, 3)) {
635
case 0x0: /* Add/subtract (with carry) */
636
disas_adc_sbc(s, insn);
638
case 0x2: /* Conditional compare */
639
if (insn & (1 << 11)) { /* (immediate) */
640
disas_cc_imm(s, insn);
641
} else { /* (register) */
642
disas_cc_reg(s, insn);
645
case 0x4: /* Conditional select */
646
disas_cond_select(s, insn);
648
case 0x6: /* Data-processing */
649
if (insn & (1 << 30)) { /* (1 source) */
650
disas_data_proc_1src(s, insn);
651
} else { /* (2 source) */
652
disas_data_proc_2src(s, insn);
656
unallocated_encoding(s);
661
unallocated_encoding(s);
666
/* C3.6 Data processing - SIMD and floating point */
667
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
669
unsupported_encoding(s, insn);
672
/* C3.1 A64 instruction index by encoding */
673
static void disas_a64_insn(CPUARMState *env, DisasContext *s)
677
insn = arm_ldl_code(env, s->pc, s->bswap_code);
681
switch (extract32(insn, 25, 4)) {
682
case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
683
unallocated_encoding(s);
685
case 0x8: case 0x9: /* Data processing - immediate */
686
disas_data_proc_imm(s, insn);
688
case 0xa: case 0xb: /* Branch, exception generation and system insns */
689
disas_b_exc_sys(s, insn);
694
case 0xe: /* Loads and stores */
698
case 0xd: /* Data processing - register */
699
disas_data_proc_reg(s, insn);
702
case 0xf: /* Data processing - SIMD and floating point */
703
disas_data_proc_simd_fp(s, insn);
706
assert(FALSE); /* all 15 cases should be handled above */
710
/* if we allocated any temporaries, free them here */
714
void gen_intermediate_code_internal_a64(ARMCPU *cpu,
715
TranslationBlock *tb,
718
CPUState *cs = CPU(cpu);
719
CPUARMState *env = &cpu->env;
720
DisasContext dc1, *dc = &dc1;
722
uint16_t *gen_opc_end;
724
target_ulong pc_start;
725
target_ulong next_page_start;
733
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
735
dc->is_jmp = DISAS_NEXT;
737
dc->singlestep_enabled = cs->singlestep_enabled;
743
dc->condexec_mask = 0;
744
dc->condexec_cond = 0;
745
#if !defined(CONFIG_USER_ONLY)
752
init_tmp_a64_array(dc);
754
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
757
max_insns = tb->cflags & CF_COUNT_MASK;
758
if (max_insns == 0) {
759
max_insns = CF_COUNT_MASK;
764
tcg_clear_temp_count();
767
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
768
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
769
if (bp->pc == dc->pc) {
770
gen_exception_insn(dc, 0, EXCP_DEBUG);
771
/* Advance PC so that clearing the breakpoint will
772
invalidate this TB. */
774
goto done_generating;
780
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
784
tcg_ctx.gen_opc_instr_start[lj++] = 0;
787
tcg_ctx.gen_opc_pc[lj] = dc->pc;
788
tcg_ctx.gen_opc_instr_start[lj] = 1;
789
tcg_ctx.gen_opc_icount[lj] = num_insns;
792
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
796
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
797
tcg_gen_debug_insn_start(dc->pc);
800
disas_a64_insn(env, dc);
802
if (tcg_check_temp_count()) {
803
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
807
/* Translation stops when a conditional branch is encountered.
808
* Otherwise the subsequent code could get translated several times.
809
* Also stop translation when a page boundary is reached. This
810
* ensures prefetch aborts occur at the right place.
813
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
814
!cs->singlestep_enabled &&
816
dc->pc < next_page_start &&
817
num_insns < max_insns);
819
if (tb->cflags & CF_LAST_IO) {
823
if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
824
/* Note that this means single stepping WFI doesn't halt the CPU.
825
* For conditional branch insns this is harmless unreachable code as
826
* gen_goto_tb() has already handled emitting the debug exception
827
* (and thus a tb-jump is not possible when singlestepping).
829
assert(dc->is_jmp != DISAS_TB_JUMP);
830
if (dc->is_jmp != DISAS_JUMP) {
831
gen_a64_set_pc_im(dc->pc);
833
gen_exception(EXCP_DEBUG);
835
switch (dc->is_jmp) {
837
gen_goto_tb(dc, 1, dc->pc);
842
/* indicate that the hash table must be used to find the next TB */
850
/* This is a special case because we don't want to just halt the CPU
851
* if trying to debug across a WFI.
853
gen_helper_wfi(cpu_env);
859
gen_tb_end(tb, num_insns);
860
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
863
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
864
qemu_log("----------------\n");
865
qemu_log("IN: %s\n", lookup_symbol(pc_start));
866
log_target_disas(env, pc_start, dc->pc - pc_start,
867
dc->thumb | (dc->bswap_code << 1));
872
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
875
tcg_ctx.gen_opc_instr_start[lj++] = 0;
878
tb->size = dc->pc - pc_start;
879
tb->icount = num_insns;