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* TI OMAP SDRAM controller emulation.
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* Copyright (C) 2007-2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) any later version of the License.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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#include "hw/arm/omap.h"
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/* SDRAM Controller Subsystem */
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void omap_sdrc_reset(struct omap_sdrc_s *s)
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static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
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struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
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return omap_badwidth_read32(opaque, addr);
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case 0x00: /* SDRC_REVISION */
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case 0x10: /* SDRC_SYSCONFIG */
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case 0x14: /* SDRC_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x40: /* SDRC_CS_CFG */
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case 0x44: /* SDRC_SHARING */
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case 0x48: /* SDRC_ERR_ADDR */
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case 0x4c: /* SDRC_ERR_TYPE */
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case 0x60: /* SDRC_DLLA_SCTRL */
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case 0x64: /* SDRC_DLLA_STATUS */
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case 0x68: /* SDRC_DLLB_CTRL */
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case 0x6c: /* SDRC_DLLB_STATUS */
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case 0x70: /* SDRC_POWER */
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case 0x80: /* SDRC_MCFG_0 */
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case 0x84: /* SDRC_MR_0 */
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case 0x88: /* SDRC_EMR1_0 */
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case 0x8c: /* SDRC_EMR2_0 */
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case 0x90: /* SDRC_EMR3_0 */
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case 0x94: /* SDRC_DCDL1_CTRL */
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case 0x98: /* SDRC_DCDL2_CTRL */
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case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
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case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
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case 0xa4: /* SDRC_RFR_CTRL_0 */
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case 0xa8: /* SDRC_MANUAL_0 */
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case 0xb0: /* SDRC_MCFG_1 */
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case 0xb4: /* SDRC_MR_1 */
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case 0xb8: /* SDRC_EMR1_1 */
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case 0xbc: /* SDRC_EMR2_1 */
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case 0xc0: /* SDRC_EMR3_1 */
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case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
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case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
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case 0xd4: /* SDRC_RFR_CTRL_1 */
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case 0xd8: /* SDRC_MANUAL_1 */
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static void omap_sdrc_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
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return omap_badwidth_write32(opaque, addr, value);
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case 0x00: /* SDRC_REVISION */
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case 0x14: /* SDRC_SYSSTATUS */
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case 0x48: /* SDRC_ERR_ADDR */
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case 0x64: /* SDRC_DLLA_STATUS */
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case 0x6c: /* SDRC_DLLB_STATUS */
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case 0x10: /* SDRC_SYSCONFIG */
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if ((value >> 3) != 0x2)
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fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
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__FUNCTION__, (unsigned)value >> 3);
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s->config = value & 0x18;
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case 0x40: /* SDRC_CS_CFG */
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case 0x44: /* SDRC_SHARING */
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case 0x4c: /* SDRC_ERR_TYPE */
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case 0x60: /* SDRC_DLLA_SCTRL */
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case 0x68: /* SDRC_DLLB_CTRL */
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case 0x70: /* SDRC_POWER */
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case 0x80: /* SDRC_MCFG_0 */
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case 0x84: /* SDRC_MR_0 */
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case 0x88: /* SDRC_EMR1_0 */
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case 0x8c: /* SDRC_EMR2_0 */
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case 0x90: /* SDRC_EMR3_0 */
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case 0x94: /* SDRC_DCDL1_CTRL */
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case 0x98: /* SDRC_DCDL2_CTRL */
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case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
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case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
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case 0xa4: /* SDRC_RFR_CTRL_0 */
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case 0xa8: /* SDRC_MANUAL_0 */
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case 0xb0: /* SDRC_MCFG_1 */
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case 0xb4: /* SDRC_MR_1 */
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case 0xb8: /* SDRC_EMR1_1 */
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case 0xbc: /* SDRC_EMR2_1 */
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case 0xc0: /* SDRC_EMR3_1 */
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case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
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case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
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case 0xd4: /* SDRC_RFR_CTRL_1 */
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case 0xd8: /* SDRC_MANUAL_1 */
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static const MemoryRegionOps omap_sdrc_ops = {
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.read = omap_sdrc_read,
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.write = omap_sdrc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
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struct omap_sdrc_s *s = (struct omap_sdrc_s *)
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g_malloc0(sizeof(struct omap_sdrc_s));
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memory_region_init_io(&s->iomem, NULL, &omap_sdrc_ops, s, "omap.sdrc", 0x1000);
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memory_region_add_subregion(sysmem, base, &s->iomem);