1
From cf438b58cfd4725a14cb1daa7eceabf703f62dbb Mon Sep 17 00:00:00 2001
2
From: Claudio Fontana <claudio.fontana@linaro.org>
3
Date: Tue, 17 Dec 2013 19:42:32 +0000
4
Subject: [PATCH 30/49] target-arm: A64: expand decoding skeleton for system
7
Decode the various kinds of system instructions:
8
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
9
sync instructions, which include CLREX, DSB, DMB, ISB
10
msr_i, which move immediate to processor state field
11
sys, which include all SYS and SYSL instructions
12
msr, which move from a gp register to a system register
13
mrs, which move from a system register to a gp register
15
Provide implementations where they are trivial nops.
17
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <rth@twiddle.net>
21
target-arm/translate-a64.c | 131 ++++++++++++++++++++++++++++++++++++++++++++-
22
1 file changed, 129 insertions(+), 2 deletions(-)
24
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
25
index 8e16cb1..1e2b371 100644
26
--- a/target-arm/translate-a64.c
27
+++ b/target-arm/translate-a64.c
28
@@ -190,12 +190,139 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
29
unsupported_encoding(s, insn);
33
-static void disas_system(DisasContext *s, uint32_t insn)
35
+static void handle_hint(DisasContext *s, uint32_t insn,
36
+ unsigned int op1, unsigned int op2, unsigned int crm)
38
+ unsigned int selector = crm << 3 | op2;
41
+ unallocated_encoding(s);
53
+ /* we treat all as NOP at least for now */
56
+ /* default specified as NOP equivalent */
61
+/* CLREX, DSB, DMB, ISB */
62
+static void handle_sync(DisasContext *s, uint32_t insn,
63
+ unsigned int op1, unsigned int op2, unsigned int crm)
66
+ unallocated_encoding(s);
72
+ unsupported_encoding(s, insn);
77
+ /* We don't emulate caches so barriers are no-ops */
80
+ unallocated_encoding(s);
85
+/* C5.6.130 MSR (immediate) - move immediate to processor state field */
86
+static void handle_msr_i(DisasContext *s, uint32_t insn,
87
+ unsigned int op1, unsigned int op2, unsigned int crm)
89
unsupported_encoding(s, insn);
93
+static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l,
94
+ unsigned int op1, unsigned int op2,
95
+ unsigned int crn, unsigned int crm, unsigned int rt)
97
+ unsupported_encoding(s, insn);
100
+/* C5.6.129 MRS - move from system register */
101
+static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0,
102
+ unsigned int op1, unsigned int op2,
103
+ unsigned int crn, unsigned int crm, unsigned int rt)
105
+ unsupported_encoding(s, insn);
108
+/* C5.6.131 MSR (register) - move to system register */
109
+static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0,
110
+ unsigned int op1, unsigned int op2,
111
+ unsigned int crn, unsigned int crm, unsigned int rt)
113
+ unsupported_encoding(s, insn);
117
+ * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
118
+ * +---------------------+---+-----+-----+-------+-------+-----+------+
119
+ * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
120
+ * +---------------------+---+-----+-----+-------+-------+-----+------+
122
+static void disas_system(DisasContext *s, uint32_t insn)
124
+ unsigned int l, op0, op1, crn, crm, op2, rt;
125
+ l = extract32(insn, 21, 1);
126
+ op0 = extract32(insn, 19, 2);
127
+ op1 = extract32(insn, 16, 3);
128
+ crn = extract32(insn, 12, 4);
129
+ crm = extract32(insn, 8, 4);
130
+ op2 = extract32(insn, 5, 3);
131
+ rt = extract32(insn, 0, 5);
134
+ if (l || rt != 31) {
135
+ unallocated_encoding(s);
139
+ case 2: /* C5.6.68 HINT */
140
+ handle_hint(s, insn, op1, op2, crm);
142
+ case 3: /* CLREX, DSB, DMB, ISB */
143
+ handle_sync(s, insn, op1, op2, crm);
145
+ case 4: /* C5.6.130 MSR (immediate) */
146
+ handle_msr_i(s, insn, op1, op2, crm);
149
+ unallocated_encoding(s);
157
+ handle_sys(s, insn, l, op1, op2, crn, crm, rt);
158
+ } else if (l) { /* op0 > 1 */
159
+ /* C5.6.129 MRS - move from system register */
160
+ handle_mrs(s, insn, op0, op1, op2, crn, crm, rt);
162
+ /* C5.6.131 MSR (register) - move to system register */
163
+ handle_msr(s, insn, op0, op1, op2, crn, crm, rt);
167
/* Exception generation */
168
static void disas_exc(DisasContext *s, uint32_t insn)