2
* ARM implementation of KVM hooks
4
* Copyright Christoffer Dall 2009-2010
6
* This work is licensed under the terms of the GNU GPL, version 2 or later.
7
* See the COPYING file in the top-level directory.
12
#include <sys/types.h>
13
#include <sys/ioctl.h>
16
#include <linux/kvm.h>
18
#include "qemu-common.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "hw/arm/arm.h"
26
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
30
bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
32
struct kvm_vcpu_init *init)
34
int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
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kvmfd = qemu_open("/dev/kvm", O_RDWR);
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vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0);
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cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0);
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ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
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ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
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/* Old kernel which doesn't know about the
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* PREFERRED_TARGET ioctl: we know it will only support
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* creating one kind of guest CPU which is its preferred
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while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
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init->target = *cpus_to_try++;
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memset(init->features, 0, sizeof(init->features));
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ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
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void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
98
for (i = 2; i >= 0; i--) {
103
static inline void set_feature(uint64_t *features, int feature)
105
*features |= 1ULL << feature;
108
bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
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/* Identify the feature bits corresponding to the host CPU, and
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* fill out the ARMHostCPUClass fields accordingly. To do this
112
* we have to create a scratch VM, create a single CPU inside it,
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* and then query that CPU for the relevant ID registers.
115
int i, ret, fdarray[3];
116
uint32_t midr, id_pfr0, id_isar0, mvfr1;
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uint64_t features = 0;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
119
* we know these will only support creating one kind of guest CPU,
120
* which is its preferred CPU type.
122
static const uint32_t cpus_to_try[] = {
123
QEMU_KVM_ARM_TARGET_CORTEX_A15,
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QEMU_KVM_ARM_TARGET_NONE
126
struct kvm_vcpu_init init;
127
struct kvm_one_reg idregs[] = {
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.id = KVM_REG_ARM | KVM_REG_SIZE_U32
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| ENCODE_CP_REG(15, 0, 0, 0, 0, 0),
131
.addr = (uintptr_t)&midr,
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.id = KVM_REG_ARM | KVM_REG_SIZE_U32
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| ENCODE_CP_REG(15, 0, 0, 1, 0, 0),
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.addr = (uintptr_t)&id_pfr0,
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.id = KVM_REG_ARM | KVM_REG_SIZE_U32
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| ENCODE_CP_REG(15, 0, 0, 2, 0, 0),
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.addr = (uintptr_t)&id_isar0,
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.id = KVM_REG_ARM | KVM_REG_SIZE_U32
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| KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
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.addr = (uintptr_t)&mvfr1,
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if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
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ahcc->target = init.target;
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/* This is not strictly blessed by the device tree binding docs yet,
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* but in practice the kernel does not care about this string so
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* there is no point maintaining an KVM_ARM_TARGET_* -> string table.
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ahcc->dtb_compatible = "arm,arm-v7";
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for (i = 0; i < ARRAY_SIZE(idregs); i++) {
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ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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/* Now we've retrieved all the register information we can
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* set the feature bits based on the ID register fields.
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* We can assume any KVM supporting CPU is at least a v7
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* with VFPv3, LPAE and the generic timers; this in turn implies
179
* most of the other feature bits, but a few must be tested.
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set_feature(&features, ARM_FEATURE_V7);
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set_feature(&features, ARM_FEATURE_VFP3);
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set_feature(&features, ARM_FEATURE_LPAE);
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set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
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switch (extract32(id_isar0, 24, 4)) {
188
set_feature(&features, ARM_FEATURE_THUMB_DIV);
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set_feature(&features, ARM_FEATURE_ARM_DIV);
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set_feature(&features, ARM_FEATURE_THUMB_DIV);
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if (extract32(id_pfr0, 12, 4) == 1) {
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set_feature(&features, ARM_FEATURE_THUMB2EE);
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if (extract32(mvfr1, 20, 4) == 1) {
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set_feature(&features, ARM_FEATURE_VFP_FP16);
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if (extract32(mvfr1, 12, 4) == 1) {
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set_feature(&features, ARM_FEATURE_NEON);
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if (extract32(mvfr1, 28, 4) == 1) {
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/* FMAC support implies VFPv4 */
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set_feature(&features, ARM_FEATURE_VFP4);
212
ahcc->features = features;
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static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data)
219
ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc);
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/* All we really need to set up for the 'host' CPU
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* is the feature bits -- we rely on the fact that the
223
* various ID register values in ARMCPU are only used for
226
if (!kvm_arm_get_host_cpu_features(ahcc)) {
227
fprintf(stderr, "Failed to retrieve host CPU features!\n");
232
static void kvm_arm_host_cpu_initfn(Object *obj)
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ARMHostCPUClass *ahcc = ARM_HOST_CPU_GET_CLASS(obj);
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ARMCPU *cpu = ARM_CPU(obj);
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CPUARMState *env = &cpu->env;
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cpu->kvm_target = ahcc->target;
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cpu->dtb_compatible = ahcc->dtb_compatible;
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env->features = ahcc->features;
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static const TypeInfo host_arm_cpu_type_info = {
244
.name = TYPE_ARM_HOST_CPU,
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.parent = TYPE_ARM_CPU,
246
.instance_init = kvm_arm_host_cpu_initfn,
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.class_init = kvm_arm_host_cpu_class_init,
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.class_size = sizeof(ARMHostCPUClass),
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int kvm_arch_init(KVMState *s)
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/* For ARM interrupt delivery is always asynchronous,
254
* whether we are using an in-kernel VGIC or not.
256
kvm_async_interrupts_allowed = true;
258
type_register_static(&host_arm_cpu_type_info);
263
unsigned long kvm_arch_vcpu_id(CPUState *cpu)
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return cpu->cpu_index;
268
static bool reg_syncs_via_tuple_list(uint64_t regidx)
270
/* Return true if the regidx is a register we should synchronize
271
* via the cpreg_tuples array (ie is not a core reg we sync by
272
* hand in kvm_arch_get/put_registers())
274
switch (regidx & KVM_REG_ARM_COPROC_MASK) {
275
case KVM_REG_ARM_CORE:
276
case KVM_REG_ARM_VFP:
283
static int compare_u64(const void *a, const void *b)
285
if (*(uint64_t *)a > *(uint64_t *)b) {
288
if (*(uint64_t *)a < *(uint64_t *)b) {
294
int kvm_arch_init_vcpu(CPUState *cs)
296
struct kvm_vcpu_init init;
297
int i, ret, arraylen;
299
struct kvm_one_reg r;
300
struct kvm_reg_list rl;
301
struct kvm_reg_list *rlp;
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ARMCPU *cpu = ARM_CPU(cs);
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if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
305
fprintf(stderr, "KVM is not supported for this guest CPU type\n");
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init.target = cpu->kvm_target;
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memset(init.features, 0, sizeof(init.features));
311
if (cpu->start_powered_off) {
312
init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF;
314
ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
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/* Query the kernel to make sure it supports 32 VFP
319
* registers: QEMU's "cortex-a15" CPU is always a
320
* VFP-D32 core. The simplest way to do this is just
321
* to attempt to read register d31.
323
r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
324
r.addr = (uintptr_t)(&v);
325
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
326
if (ret == -ENOENT) {
330
/* Populate the cpreg list based on the kernel's idea
331
* of what registers exist (and throw away the TCG-created list).
334
ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
338
rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
340
ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
344
/* Sort the list we get back from the kernel, since cpreg_tuples
345
* must be in strictly ascending order.
347
qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
349
for (i = 0, arraylen = 0; i < rlp->n; i++) {
350
if (!reg_syncs_via_tuple_list(rlp->reg[i])) {
353
switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
354
case KVM_REG_SIZE_U32:
355
case KVM_REG_SIZE_U64:
358
fprintf(stderr, "Can't handle size of register in kernel list\n");
366
cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
367
cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
368
cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
370
cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
372
cpu->cpreg_array_len = arraylen;
373
cpu->cpreg_vmstate_array_len = arraylen;
375
for (i = 0, arraylen = 0; i < rlp->n; i++) {
376
uint64_t regidx = rlp->reg[i];
377
if (!reg_syncs_via_tuple_list(regidx)) {
380
cpu->cpreg_indexes[arraylen] = regidx;
383
assert(cpu->cpreg_array_len == arraylen);
385
if (!write_kvmstate_to_list(cpu)) {
386
/* Shouldn't happen unless kernel is inconsistent about
387
* what registers exist.
389
fprintf(stderr, "Initial read of kernel register state failed\n");
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/* Save a copy of the initial register values so that we can
395
* feed it back to the kernel on VCPU reset.
397
cpu->cpreg_reset_values = g_memdup(cpu->cpreg_values,
398
cpu->cpreg_array_len *
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sizeof(cpu->cpreg_values[0]));
406
/* We track all the KVM devices which need their memory addresses
407
* passing to the kernel in a list of these structures.
408
* When board init is complete we run through the list and
409
* tell the kernel the base addresses of the memory regions.
410
* We use a MemoryListener to track mapping and unmapping of
411
* the regions during board creation, so the board models don't
412
* need to do anything special for the KVM case.
414
typedef struct KVMDevice {
415
struct kvm_arm_device_addr kda;
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QSLIST_ENTRY(KVMDevice) entries;
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static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head;
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static void kvm_arm_devlistener_add(MemoryListener *listener,
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MemoryRegionSection *section)
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QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
428
if (section->mr == kd->mr) {
429
kd->kda.addr = section->offset_within_address_space;
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static void kvm_arm_devlistener_del(MemoryListener *listener,
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MemoryRegionSection *section)
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QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
440
if (section->mr == kd->mr) {
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static MemoryListener devlistener = {
447
.region_add = kvm_arm_devlistener_add,
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.region_del = kvm_arm_devlistener_del,
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static void kvm_arm_machine_init_done(Notifier *notifier, void *data)
455
memory_listener_unregister(&devlistener);
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QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) {
457
if (kd->kda.addr != -1) {
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if (kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR,
460
fprintf(stderr, "KVM_ARM_SET_DEVICE_ADDRESS failed: %s\n",
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memory_region_unref(kd->mr);
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static Notifier notify = {
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.notify = kvm_arm_machine_init_done,
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void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid)
478
if (!kvm_irqchip_in_kernel()) {
482
if (QSLIST_EMPTY(&kvm_devices_head)) {
483
memory_listener_register(&devlistener, NULL);
484
qemu_add_machine_init_done_notifier(¬ify);
486
kd = g_new0(KVMDevice, 1);
490
QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
491
memory_region_ref(kd->mr);
494
bool write_kvmstate_to_list(ARMCPU *cpu)
496
CPUState *cs = CPU(cpu);
500
for (i = 0; i < cpu->cpreg_array_len; i++) {
501
struct kvm_one_reg r;
502
uint64_t regidx = cpu->cpreg_indexes[i];
508
switch (regidx & KVM_REG_SIZE_MASK) {
509
case KVM_REG_SIZE_U32:
510
r.addr = (uintptr_t)&v32;
511
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
513
cpu->cpreg_values[i] = v32;
516
case KVM_REG_SIZE_U64:
517
r.addr = (uintptr_t)(cpu->cpreg_values + i);
518
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
530
bool write_list_to_kvmstate(ARMCPU *cpu)
532
CPUState *cs = CPU(cpu);
536
for (i = 0; i < cpu->cpreg_array_len; i++) {
537
struct kvm_one_reg r;
538
uint64_t regidx = cpu->cpreg_indexes[i];
543
switch (regidx & KVM_REG_SIZE_MASK) {
544
case KVM_REG_SIZE_U32:
545
v32 = cpu->cpreg_values[i];
546
r.addr = (uintptr_t)&v32;
548
case KVM_REG_SIZE_U64:
549
r.addr = (uintptr_t)(cpu->cpreg_values + i);
554
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
556
/* We might fail for "unknown register" and also for
557
* "you tried to set a register which is constant with
558
* a different value from what it actually contains".
571
#define COREREG(KERNELNAME, QEMUFIELD) \
573
KVM_REG_ARM | KVM_REG_SIZE_U32 | \
574
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
575
offsetof(CPUARMState, QEMUFIELD) \
578
#define VFPSYSREG(R) \
580
KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
581
KVM_REG_ARM_VFP_##R, \
582
offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
585
static const Reg regs[] = {
586
/* R0_usr .. R14_usr */
587
COREREG(usr_regs.uregs[0], regs[0]),
588
COREREG(usr_regs.uregs[1], regs[1]),
589
COREREG(usr_regs.uregs[2], regs[2]),
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COREREG(usr_regs.uregs[3], regs[3]),
591
COREREG(usr_regs.uregs[4], regs[4]),
592
COREREG(usr_regs.uregs[5], regs[5]),
593
COREREG(usr_regs.uregs[6], regs[6]),
594
COREREG(usr_regs.uregs[7], regs[7]),
595
COREREG(usr_regs.uregs[8], usr_regs[0]),
596
COREREG(usr_regs.uregs[9], usr_regs[1]),
597
COREREG(usr_regs.uregs[10], usr_regs[2]),
598
COREREG(usr_regs.uregs[11], usr_regs[3]),
599
COREREG(usr_regs.uregs[12], usr_regs[4]),
600
COREREG(usr_regs.uregs[13], banked_r13[0]),
601
COREREG(usr_regs.uregs[14], banked_r14[0]),
602
/* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
603
COREREG(svc_regs[0], banked_r13[1]),
604
COREREG(svc_regs[1], banked_r14[1]),
605
COREREG(svc_regs[2], banked_spsr[1]),
606
COREREG(abt_regs[0], banked_r13[2]),
607
COREREG(abt_regs[1], banked_r14[2]),
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COREREG(abt_regs[2], banked_spsr[2]),
609
COREREG(und_regs[0], banked_r13[3]),
610
COREREG(und_regs[1], banked_r14[3]),
611
COREREG(und_regs[2], banked_spsr[3]),
612
COREREG(irq_regs[0], banked_r13[4]),
613
COREREG(irq_regs[1], banked_r14[4]),
614
COREREG(irq_regs[2], banked_spsr[4]),
615
/* R8_fiq .. R14_fiq and SPSR_fiq */
616
COREREG(fiq_regs[0], fiq_regs[0]),
617
COREREG(fiq_regs[1], fiq_regs[1]),
618
COREREG(fiq_regs[2], fiq_regs[2]),
619
COREREG(fiq_regs[3], fiq_regs[3]),
620
COREREG(fiq_regs[4], fiq_regs[4]),
621
COREREG(fiq_regs[5], banked_r13[5]),
622
COREREG(fiq_regs[6], banked_r14[5]),
623
COREREG(fiq_regs[7], banked_spsr[5]),
625
COREREG(usr_regs.uregs[15], regs[15]),
626
/* VFP system registers */
635
int kvm_arch_put_registers(CPUState *cs, int level)
637
ARMCPU *cpu = ARM_CPU(cs);
638
CPUARMState *env = &cpu->env;
639
struct kvm_one_reg r;
642
uint32_t cpsr, fpscr;
644
/* Make sure the banked regs are properly set */
645
mode = env->uncached_cpsr & CPSR_M;
646
bn = bank_number(mode);
647
if (mode == ARM_CPU_MODE_FIQ) {
648
memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
650
memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
652
env->banked_r13[bn] = env->regs[13];
653
env->banked_r14[bn] = env->regs[14];
654
env->banked_spsr[bn] = env->spsr;
656
/* Now we can safely copy stuff down to the kernel */
657
for (i = 0; i < ARRAY_SIZE(regs); i++) {
659
r.addr = (uintptr_t)(env) + regs[i].offset;
660
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
666
/* Special cases which aren't a single CPUARMState field */
667
cpsr = cpsr_read(env);
668
r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
669
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
670
r.addr = (uintptr_t)(&cpsr);
671
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
677
r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
678
for (i = 0; i < 32; i++) {
679
r.addr = (uintptr_t)(&env->vfp.regs[i]);
680
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
687
r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
688
KVM_REG_ARM_VFP_FPSCR;
689
fpscr = vfp_get_fpscr(env);
690
r.addr = (uintptr_t)&fpscr;
691
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
696
/* Note that we do not call write_cpustate_to_list()
697
* here, so we are only writing the tuple list back to
698
* KVM. This is safe because nothing can change the
699
* CPUARMState cp15 fields (in particular gdb accesses cannot)
700
* and so there are no changes to sync. In fact syncing would
701
* be wrong at this point: for a constant register where TCG and
702
* KVM disagree about its value, the preceding write_list_to_cpustate()
703
* would not have had any effect on the CPUARMState value (since the
704
* register is read-only), and a write_cpustate_to_list() here would
705
* then try to write the TCG value back into KVM -- this would either
706
* fail or incorrectly change the value the guest sees.
708
* If we ever want to allow the user to modify cp15 registers via
709
* the gdb stub, we would need to be more clever here (for instance
710
* tracking the set of registers kvm_arch_get_registers() successfully
711
* managed to update the CPUARMState with, and only allowing those
712
* to be written back up into the kernel).
714
if (!write_list_to_kvmstate(cpu)) {
721
int kvm_arch_get_registers(CPUState *cs)
723
ARMCPU *cpu = ARM_CPU(cs);
724
CPUARMState *env = &cpu->env;
725
struct kvm_one_reg r;
728
uint32_t cpsr, fpscr;
730
for (i = 0; i < ARRAY_SIZE(regs); i++) {
732
r.addr = (uintptr_t)(env) + regs[i].offset;
733
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
739
/* Special cases which aren't a single CPUARMState field */
740
r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
741
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
742
r.addr = (uintptr_t)(&cpsr);
743
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
747
cpsr_write(env, cpsr, 0xffffffff);
749
/* Make sure the current mode regs are properly set */
750
mode = env->uncached_cpsr & CPSR_M;
751
bn = bank_number(mode);
752
if (mode == ARM_CPU_MODE_FIQ) {
753
memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
755
memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
757
env->regs[13] = env->banked_r13[bn];
758
env->regs[14] = env->banked_r14[bn];
759
env->spsr = env->banked_spsr[bn];
762
r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
763
for (i = 0; i < 32; i++) {
764
r.addr = (uintptr_t)(&env->vfp.regs[i]);
765
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
772
r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
773
KVM_REG_ARM_VFP_FPSCR;
774
r.addr = (uintptr_t)&fpscr;
775
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
779
vfp_set_fpscr(env, fpscr);
781
if (!write_kvmstate_to_list(cpu)) {
784
/* Note that it's OK to have registers which aren't in CPUState,
785
* so we can ignore a failure return here.
787
write_list_to_cpustate(cpu);
792
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
796
void kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
800
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
805
void kvm_arch_reset_vcpu(CPUState *cs)
807
/* Feed the kernel back its initial register state */
808
ARMCPU *cpu = ARM_CPU(cs);
810
memmove(cpu->cpreg_values, cpu->cpreg_reset_values,
811
cpu->cpreg_array_len * sizeof(cpu->cpreg_values[0]));
813
if (!write_list_to_kvmstate(cpu)) {
818
bool kvm_arch_stop_on_emulation_error(CPUState *cs)
823
int kvm_arch_process_async_events(CPUState *cs)
828
int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
833
int kvm_arch_on_sigbus(int code, void *addr)
838
void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
840
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
843
int kvm_arch_insert_sw_breakpoint(CPUState *cs,
844
struct kvm_sw_breakpoint *bp)
846
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
850
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
851
target_ulong len, int type)
853
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
857
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
858
target_ulong len, int type)
860
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
864
int kvm_arch_remove_sw_breakpoint(CPUState *cs,
865
struct kvm_sw_breakpoint *bp)
867
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
871
void kvm_arch_remove_all_hw_breakpoints(void)
873
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
876
void kvm_arch_init_irq_routing(KVMState *s)