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From 538aa3819cc2868befb581ac13091b7a6d28c199 Mon Sep 17 00:00:00 2001
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From: Claudio Fontana <claudio.fontana@linaro.org>
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Date: Tue, 17 Dec 2013 19:42:33 +0000
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Subject: [PATCH 36/49] target-arm: A64: add support for conditional select
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This patch adds support for the instruction group "C3.5.6
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Conditional select": CSEL, CSINC, CSINV, CSNEG.
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Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
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[PMM: Improved code generated in the nomatch case as per RTH suggestions]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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target-arm/translate-a64.c | 67 ++++++++++++++++++++++++++++++++++++++++++++--
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1 file changed, 65 insertions(+), 2 deletions(-)
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diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
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index 5ae3a85..13eedf4 100644
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--- a/target-arm/translate-a64.c
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+++ b/target-arm/translate-a64.c
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@@ -724,10 +724,73 @@ static void disas_cc_reg(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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-/* Conditional select */
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+/* C3.5.6 Conditional select
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+ * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
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+ * +----+----+---+-----------------+------+------+-----+------+------+
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+ * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
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+ * +----+----+---+-----------------+------+------+-----+------+------+
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static void disas_cond_select(DisasContext *s, uint32_t insn)
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- unsupported_encoding(s, insn);
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+ unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
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+ TCGv_i64 tcg_rd, tcg_src;
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+ if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
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+ /* S == 1 or op2<1> == 1 */
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+ unallocated_encoding(s);
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+ sf = extract32(insn, 31, 1);
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+ else_inv = extract32(insn, 30, 1);
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+ rm = extract32(insn, 16, 5);
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+ cond = extract32(insn, 12, 4);
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+ else_inc = extract32(insn, 10, 1);
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+ rn = extract32(insn, 5, 5);
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+ rd = extract32(insn, 0, 5);
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+ /* silly no-op write; until we use movcond we must special-case
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+ * this to avoid a dead temporary across basic blocks.
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+ tcg_rd = cpu_reg(s, rd);
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+ if (cond >= 0x0e) { /* condition "always" */
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+ tcg_src = read_cpu_reg(s, rn, sf);
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+ tcg_gen_mov_i64(tcg_rd, tcg_src);
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+ /* OPTME: we could use movcond here, at the cost of duplicating
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+ * a lot of the arm_gen_test_cc() logic.
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+ int label_match = gen_new_label();
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+ int label_continue = gen_new_label();
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+ arm_gen_test_cc(cond, label_match);
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+ tcg_src = cpu_reg(s, rm);
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+ if (else_inv && else_inc) {
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+ tcg_gen_neg_i64(tcg_rd, tcg_src);
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+ } else if (else_inv) {
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+ tcg_gen_not_i64(tcg_rd, tcg_src);
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+ } else if (else_inc) {
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+ tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
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+ tcg_gen_mov_i64(tcg_rd, tcg_src);
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+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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+ tcg_gen_br(label_continue);
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+ gen_set_label(label_match);
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+ tcg_src = read_cpu_reg(s, rn, sf);
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+ tcg_gen_mov_i64(tcg_rd, tcg_src);
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+ gen_set_label(label_continue);
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/* Data-processing (1 source) */