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Viewing changes to debian/patches/ubuntu/arm64/0016-target-arm-Use-new-qemu_ld-st-opcodes.patch

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-04 12:13:08 UTC
  • mfrom: (10.1.45 sid)
  • Revision ID: package-import@ubuntu.com-20140204121308-1xq92lrfs75agw2g
Tags: 1.7.0+dfsg-3ubuntu1~ppa1
* Merge 1.7.0+dfsg-3 from debian.  Remaining changes:
  - debian/patches/ubuntu:
    * expose-vmx_qemu64cpu.patch
    * linaro (omap3) and arm64 patches
    * ubuntu/target-ppc-add-stubs-for-kvm-breakpoints: fix FTBFS
      on ppc
    * ubuntu/CVE-2013-4377.patch: fix denial of service via virtio
  - debian/qemu-system-x86.modprobe: set kvm_intel nested=1 options
  - debian/control:
    * add arm64 to Architectures
    * add qemu-common and qemu-system-aarch64 packages
  - debian/qemu-system-common.install: add debian/tmp/usr/lib
  - debian/qemu-system-common.preinst: add kvm group
  - debian/qemu-system-common.postinst: remove acl placed by udev,
    and add udevadm trigger.
  - qemu-system-x86.links: add eepro100.rom, remove pxe-virtio,
    pxe-e1000 and pxe-rtl8139.
  - add qemu-system-x86.qemu-kvm.upstart and .default
  - qemu-user-static.postinst-in: remove arm64 binfmt
  - debian/rules:
    * allow parallel build
    * add aarch64 to system_targets and sys_systems
    * add qemu-kvm-spice links
    * install qemu-system-x86.modprobe
  - add debian/qemu-system-common.links for OVMF.fd link
* Remove kvm-img, kvm-nbd, kvm-ifup and kvm-ifdown symlinks.

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debian/patches/ubuntu/arm64/0016-target-arm-Use-new-qemu_ld-st-opcodes.patch
 
1
From 1933f99d75040dd2f6f62f066eda42a5979014a4 Mon Sep 17 00:00:00 2001
 
2
From: Richard Henderson <rth@twiddle.net>
 
3
Date: Mon, 9 Dec 2013 14:37:06 -0800
 
4
Subject: [PATCH 16/49] target-arm: Use new qemu_ld/st opcodes
 
5
 
 
6
Retain the existing gen_aa32_* inlines, to aid compilation for A64.
 
7
 
 
8
Cc: Peter Maydell <peter.maydell@linaro.org>
 
9
Signed-off-by: Richard Henderson <rth@twiddle.net>
 
10
Message-id: 1386628626-21627-1-git-send-email-rth@twiddle.net
 
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 
12
---
 
13
 target-arm/translate.c | 56 ++++++++++++++++++++++----------------------------
 
14
 1 file changed, 25 insertions(+), 31 deletions(-)
 
15
 
 
16
Index: qemu.hallyn/target-arm/translate.c
 
17
===================================================================
 
18
--- qemu.hallyn.orig/target-arm/translate.c     2014-01-15 11:01:24.270266109 -0700
 
19
+++ qemu.hallyn/target-arm/translate.c  2014-01-15 11:01:24.270266109 -0700
 
20
@@ -826,63 +826,57 @@
 
21
  * extended if we're a 64 bit core) and  data is also
 
22
  * 32 bits unless specifically doing a 64 bit access.
 
23
  * These functions work like tcg_gen_qemu_{ld,st}* except
 
24
- * that their arguments are TCGv_i32 rather than TCGv.
 
25
+ * that the address argument is TCGv_i32 rather than TCGv.
 
26
  */
 
27
 #if TARGET_LONG_BITS == 32
 
28
 
 
29
-#define DO_GEN_LD(OP)                                                    \
 
30
-static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
 
31
+#define DO_GEN_LD(SUFF, OPC)                                             \
 
32
+static inline void gen_aa32_ld##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
 
33
 {                                                                        \
 
34
-    tcg_gen_qemu_##OP(val, addr, index);                                 \
 
35
+    tcg_gen_qemu_ld_i32(val, addr, index, OPC);                          \
 
36
 }
 
37
 
 
38
-#define DO_GEN_ST(OP)                                                    \
 
39
-static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
 
40
+#define DO_GEN_ST(SUFF, OPC)                                             \
 
41
+static inline void gen_aa32_st##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
 
42
 {                                                                        \
 
43
-    tcg_gen_qemu_##OP(val, addr, index);                                 \
 
44
+    tcg_gen_qemu_st_i32(val, addr, index, OPC);                          \
 
45
 }
 
46
 
 
47
 static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
 
48
 {
 
49
-    tcg_gen_qemu_ld64(val, addr, index);
 
50
+    tcg_gen_qemu_ld_i64(val, addr, index, MO_TEQ);
 
51
 }
 
52
 
 
53
 static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
 
54
 {
 
55
-    tcg_gen_qemu_st64(val, addr, index);
 
56
+    tcg_gen_qemu_st_i64(val, addr, index, MO_TEQ);
 
57
 }
 
58
 
 
59
 #else
 
60
 
 
61
-#define DO_GEN_LD(OP)                                                    \
 
62
-static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
 
63
+#define DO_GEN_LD(SUFF, OPC)                                             \
 
64
+static inline void gen_aa32_ld##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
 
65
 {                                                                        \
 
66
     TCGv addr64 = tcg_temp_new();                                        \
 
67
-    TCGv val64 = tcg_temp_new();                                         \
 
68
     tcg_gen_extu_i32_i64(addr64, addr);                                  \
 
69
-    tcg_gen_qemu_##OP(val64, addr64, index);                             \
 
70
+    tcg_gen_qemu_ld_i32(val, addr64, index, OPC);                        \
 
71
     tcg_temp_free(addr64);                                               \
 
72
-    tcg_gen_trunc_i64_i32(val, val64);                                   \
 
73
-    tcg_temp_free(val64);                                                \
 
74
 }
 
75
 
 
76
-#define DO_GEN_ST(OP)                                                    \
 
77
-static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
 
78
+#define DO_GEN_ST(SUFF, OPC)                                             \
 
79
+static inline void gen_aa32_st##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
 
80
 {                                                                        \
 
81
     TCGv addr64 = tcg_temp_new();                                        \
 
82
-    TCGv val64 = tcg_temp_new();                                         \
 
83
     tcg_gen_extu_i32_i64(addr64, addr);                                  \
 
84
-    tcg_gen_extu_i32_i64(val64, val);                                    \
 
85
-    tcg_gen_qemu_##OP(val64, addr64, index);                             \
 
86
+    tcg_gen_qemu_st_i32(val, addr64, index, OPC);                        \
 
87
     tcg_temp_free(addr64);                                               \
 
88
-    tcg_temp_free(val64);                                                \
 
89
 }
 
90
 
 
91
 static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
 
92
 {
 
93
     TCGv addr64 = tcg_temp_new();
 
94
     tcg_gen_extu_i32_i64(addr64, addr);
 
95
-    tcg_gen_qemu_ld64(val, addr64, index);
 
96
+    tcg_gen_qemu_ld_i64(val, addr64, index, MO_TEQ);
 
97
     tcg_temp_free(addr64);
 
98
 }
 
99
 
 
100
@@ -890,20 +884,20 @@
 
101
 {
 
102
     TCGv addr64 = tcg_temp_new();
 
103
     tcg_gen_extu_i32_i64(addr64, addr);
 
104
-    tcg_gen_qemu_st64(val, addr64, index);
 
105
+    tcg_gen_qemu_st_i64(val, addr64, index, MO_TEQ);
 
106
     tcg_temp_free(addr64);
 
107
 }
 
108
 
 
109
 #endif
 
110
 
 
111
-DO_GEN_LD(ld8s)
 
112
-DO_GEN_LD(ld8u)
 
113
-DO_GEN_LD(ld16s)
 
114
-DO_GEN_LD(ld16u)
 
115
-DO_GEN_LD(ld32u)
 
116
-DO_GEN_ST(st8)
 
117
-DO_GEN_ST(st16)
 
118
-DO_GEN_ST(st32)
 
119
+DO_GEN_LD(8s, MO_SB)
 
120
+DO_GEN_LD(8u, MO_UB)
 
121
+DO_GEN_LD(16s, MO_TESW)
 
122
+DO_GEN_LD(16u, MO_TEUW)
 
123
+DO_GEN_LD(32u, MO_TEUL)
 
124
+DO_GEN_ST(8, MO_UB)
 
125
+DO_GEN_ST(16, MO_TEUW)
 
126
+DO_GEN_ST(32, MO_TEUL)
 
127
 
 
128
 static inline void gen_smc(CPUARMState *env, DisasContext *s)
 
129
 {