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From 1078f8f7da486c83b13a96a978402040c0ad54fa Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Mon, 18 Feb 2013 16:58:29 +0000
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Subject: [PATCH 37/70] hw/omap_uart.c: Forbid extended MCR bit writes unless
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The OMAP UART defines new functions for MCR bits 5 and 6;
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these can only be written if the appropriate bit is set in the
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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hw/char/omap_uart.c | 13 ++++++++++---
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1 file changed, 10 insertions(+), 3 deletions(-)
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diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
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index 5ee352c..55982fa 100644
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--- a/hw/char/omap_uart.c
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+++ b/hw/char/omap_uart.c
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@@ -124,8 +124,10 @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr,
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if (s->access_mode == regs_config_b) {
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return s->xon[(addr & 7) >> 2];
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} else if (addr == 0x10) {
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- return s->serial_ops->read(s->serial, addr, size)
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- | (s->mcr_cache & 0xe0);
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+ /* MCR. Bits 5 and 6 are handled by us, the rest by
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+ * the underlying serial implementation.
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+ return s->serial_ops->read(s->serial, addr, size) | s->mcr_cache;
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return s->serial_ops->read(s->serial, addr, size);
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@@ -213,7 +215,12 @@ static void omap_uart_write(void *opaque, hwaddr addr,
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s->xon[(addr & 7) >> 2] = value;
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- s->mcr_cache = value & 0x7f;
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+ /* Bits 5 and 6 are handled at this level; they can
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+ * only be written if EFR_REG:ENHANCED_EN is set.
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+ if (s->efr & 0x10) {
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+ s->mcr_cache = value & 0x60;
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s->serial_ops->write(s->serial, addr, value, size);