2
* TI OMAP processors GPIO emulation.
4
* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5
* Copyright (C) 2007-2009 Nokia Corporation
7
* This program is free software; you can redistribute it and/or
8
* modify it under the terms of the GNU General Public License as
9
* published by the Free Software Foundation; either version 2 or
10
* (at your option) version 3 of the License.
12
* This program is distributed in the hope that it will be useful,
13
* but WITHOUT ANY WARRANTY; without even the implied warranty of
14
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
* GNU General Public License for more details.
17
* You should have received a copy of the GNU General Public License along
18
* with this program; if not, see <http://www.gnu.org/licenses/>.
22
#include "hw/arm/omap.h"
23
#include "hw/sysbus.h"
38
#define TYPE_OMAP1_GPIO "omap-gpio"
39
#define OMAP1_GPIO(obj) \
40
OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
43
SysBusDevice parent_obj;
48
struct omap_gpio_s omap1;
51
/* General-Purpose I/O of OMAP1 */
52
static void omap_gpio_set(void *opaque, int line, int level)
54
struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
55
uint16_t prev = s->inputs;
58
s->inputs |= 1 << line;
60
s->inputs &= ~(1 << line);
62
if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
63
(1 << line) & s->dir & ~s->mask) {
65
qemu_irq_raise(s->irq);
69
static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
72
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
73
int offset = addr & OMAP_MPUI_REG_MASK;
76
return omap_badwidth_read16(opaque, addr);
80
case 0x00: /* DATA_INPUT */
81
return s->inputs & s->pins;
83
case 0x04: /* DATA_OUTPUT */
86
case 0x08: /* DIRECTION_CONTROL */
89
case 0x0c: /* INTERRUPT_CONTROL */
92
case 0x10: /* INTERRUPT_MASK */
95
case 0x14: /* INTERRUPT_STATUS */
98
case 0x18: /* PIN_CONTROL (not in OMAP310) */
107
static void omap_gpio_write(void *opaque, hwaddr addr,
108
uint64_t value, unsigned size)
110
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
111
int offset = addr & OMAP_MPUI_REG_MASK;
116
return omap_badwidth_write16(opaque, addr, value);
120
case 0x00: /* DATA_INPUT */
124
case 0x04: /* DATA_OUTPUT */
125
diff = (s->outputs ^ value) & ~s->dir;
127
while ((ln = ffs(diff))) {
130
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
135
case 0x08: /* DIRECTION_CONTROL */
136
diff = s->outputs & (s->dir ^ value);
139
value = s->outputs & ~s->dir;
140
while ((ln = ffs(diff))) {
143
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
148
case 0x0c: /* INTERRUPT_CONTROL */
152
case 0x10: /* INTERRUPT_MASK */
156
case 0x14: /* INTERRUPT_STATUS */
159
qemu_irq_lower(s->irq);
162
case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
173
/* *Some* sources say the memory region is 32-bit. */
174
static const MemoryRegionOps omap_gpio_ops = {
175
.read = omap_gpio_read,
176
.write = omap_gpio_write,
177
.endianness = DEVICE_NATIVE_ENDIAN,
180
static void omap_gpio_reset(struct omap_gpio_s *s)
191
struct omap2_gpio_s {
211
#define TYPE_OMAP2_GPIO "omap2-gpio"
212
#define OMAP2_GPIO(obj) \
213
OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
215
struct omap2_gpif_s {
216
SysBusDevice parent_obj;
223
struct omap2_gpio_s *modules;
229
/* General-Purpose Interface of OMAP2/3 */
230
static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
233
qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
236
static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
238
if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
240
if (!(s->config[0] & (3 << 3))) /* Force Idle */
242
if (!(s->wumask & (1 << line)))
245
qemu_irq_raise(s->wkup);
248
static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
255
while ((ln = ffs(diff))) {
257
qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
262
static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
264
s->ints[line] |= s->dir &
265
((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
266
omap2_gpio_module_int_update(s, line);
269
static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
271
s->ints[0] |= 1 << line;
272
omap2_gpio_module_int_update(s, 0);
273
s->ints[1] |= 1 << line;
274
omap2_gpio_module_int_update(s, 1);
275
omap2_gpio_module_wake(s, line);
278
static void omap2_gpio_set(void *opaque, int line, int level)
280
struct omap2_gpif_s *p = opaque;
281
struct omap2_gpio_s *s = &p->modules[line >> 5];
285
if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
286
omap2_gpio_module_int(s, line);
287
s->inputs |= 1 << line;
289
if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
290
omap2_gpio_module_int(s, line);
291
s->inputs &= ~(1 << line);
295
static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
313
static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
315
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
318
case 0x00: /* GPIO_REVISION */
321
case 0x10: /* GPIO_SYSCONFIG */
324
case 0x14: /* GPIO_SYSSTATUS */
327
case 0x18: /* GPIO_IRQSTATUS1 */
330
case 0x1c: /* GPIO_IRQENABLE1 */
331
case 0x60: /* GPIO_CLEARIRQENABLE1 */
332
case 0x64: /* GPIO_SETIRQENABLE1 */
335
case 0x20: /* GPIO_WAKEUPENABLE */
336
case 0x80: /* GPIO_CLEARWKUENA */
337
case 0x84: /* GPIO_SETWKUENA */
340
case 0x28: /* GPIO_IRQSTATUS2 */
343
case 0x2c: /* GPIO_IRQENABLE2 */
344
case 0x70: /* GPIO_CLEARIRQENABLE2 */
345
case 0x74: /* GPIO_SETIREQNEABLE2 */
348
case 0x30: /* GPIO_CTRL */
351
case 0x34: /* GPIO_OE */
354
case 0x38: /* GPIO_DATAIN */
357
case 0x3c: /* GPIO_DATAOUT */
358
case 0x90: /* GPIO_CLEARDATAOUT */
359
case 0x94: /* GPIO_SETDATAOUT */
362
case 0x40: /* GPIO_LEVELDETECT0 */
365
case 0x44: /* GPIO_LEVELDETECT1 */
368
case 0x48: /* GPIO_RISINGDETECT */
371
case 0x4c: /* GPIO_FALLINGDETECT */
374
case 0x50: /* GPIO_DEBOUNCENABLE */
377
case 0x54: /* GPIO_DEBOUNCINGTIME */
385
static void omap2_gpio_module_write(void *opaque, hwaddr addr,
388
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
393
case 0x00: /* GPIO_REVISION */
394
case 0x14: /* GPIO_SYSSTATUS */
395
case 0x38: /* GPIO_DATAIN */
399
case 0x10: /* GPIO_SYSCONFIG */
400
if (((value >> 3) & 3) == 3)
401
fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
403
omap2_gpio_module_reset(s);
404
s->config[0] = value & 0x1d;
407
case 0x18: /* GPIO_IRQSTATUS1 */
408
if (s->ints[0] & value) {
409
s->ints[0] &= ~value;
410
omap2_gpio_module_level_update(s, 0);
414
case 0x1c: /* GPIO_IRQENABLE1 */
416
omap2_gpio_module_int_update(s, 0);
419
case 0x20: /* GPIO_WAKEUPENABLE */
423
case 0x28: /* GPIO_IRQSTATUS2 */
424
if (s->ints[1] & value) {
425
s->ints[1] &= ~value;
426
omap2_gpio_module_level_update(s, 1);
430
case 0x2c: /* GPIO_IRQENABLE2 */
432
omap2_gpio_module_int_update(s, 1);
435
case 0x30: /* GPIO_CTRL */
436
s->config[1] = value & 7;
439
case 0x34: /* GPIO_OE */
440
diff = s->outputs & (s->dir ^ value);
443
value = s->outputs & ~s->dir;
444
while ((ln = ffs(diff))) {
445
diff &= ~(1 <<-- ln);
446
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
449
omap2_gpio_module_level_update(s, 0);
450
omap2_gpio_module_level_update(s, 1);
453
case 0x3c: /* GPIO_DATAOUT */
454
omap2_gpio_module_out_update(s, s->outputs ^ value);
457
case 0x40: /* GPIO_LEVELDETECT0 */
459
omap2_gpio_module_level_update(s, 0);
460
omap2_gpio_module_level_update(s, 1);
463
case 0x44: /* GPIO_LEVELDETECT1 */
465
omap2_gpio_module_level_update(s, 0);
466
omap2_gpio_module_level_update(s, 1);
469
case 0x48: /* GPIO_RISINGDETECT */
473
case 0x4c: /* GPIO_FALLINGDETECT */
477
case 0x50: /* GPIO_DEBOUNCENABLE */
481
case 0x54: /* GPIO_DEBOUNCINGTIME */
485
case 0x60: /* GPIO_CLEARIRQENABLE1 */
486
s->mask[0] &= ~value;
487
omap2_gpio_module_int_update(s, 0);
490
case 0x64: /* GPIO_SETIRQENABLE1 */
492
omap2_gpio_module_int_update(s, 0);
495
case 0x70: /* GPIO_CLEARIRQENABLE2 */
496
s->mask[1] &= ~value;
497
omap2_gpio_module_int_update(s, 1);
500
case 0x74: /* GPIO_SETIREQNEABLE2 */
502
omap2_gpio_module_int_update(s, 1);
505
case 0x80: /* GPIO_CLEARWKUENA */
509
case 0x84: /* GPIO_SETWKUENA */
513
case 0x90: /* GPIO_CLEARDATAOUT */
514
omap2_gpio_module_out_update(s, s->outputs & value);
517
case 0x94: /* GPIO_SETDATAOUT */
518
omap2_gpio_module_out_update(s, ~s->outputs & value);
527
static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
529
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
532
static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
536
uint32_t mask = 0xffff;
539
case 0x00: /* GPIO_REVISION */
540
case 0x14: /* GPIO_SYSSTATUS */
541
case 0x38: /* GPIO_DATAIN */
545
case 0x10: /* GPIO_SYSCONFIG */
546
case 0x1c: /* GPIO_IRQENABLE1 */
547
case 0x20: /* GPIO_WAKEUPENABLE */
548
case 0x2c: /* GPIO_IRQENABLE2 */
549
case 0x30: /* GPIO_CTRL */
550
case 0x34: /* GPIO_OE */
551
case 0x3c: /* GPIO_DATAOUT */
552
case 0x40: /* GPIO_LEVELDETECT0 */
553
case 0x44: /* GPIO_LEVELDETECT1 */
554
case 0x48: /* GPIO_RISINGDETECT */
555
case 0x4c: /* GPIO_FALLINGDETECT */
556
case 0x50: /* GPIO_DEBOUNCENABLE */
557
case 0x54: /* GPIO_DEBOUNCINGTIME */
558
cur = omap2_gpio_module_read(opaque, addr & ~3) &
559
~(mask << ((addr & 3) << 3));
562
case 0x18: /* GPIO_IRQSTATUS1 */
563
case 0x28: /* GPIO_IRQSTATUS2 */
564
case 0x60: /* GPIO_CLEARIRQENABLE1 */
565
case 0x64: /* GPIO_SETIRQENABLE1 */
566
case 0x70: /* GPIO_CLEARIRQENABLE2 */
567
case 0x74: /* GPIO_SETIREQNEABLE2 */
568
case 0x80: /* GPIO_CLEARWKUENA */
569
case 0x84: /* GPIO_SETWKUENA */
570
case 0x90: /* GPIO_CLEARDATAOUT */
571
case 0x94: /* GPIO_SETDATAOUT */
572
value <<= (addr & 3) << 3;
573
omap2_gpio_module_write(opaque, addr, cur | value);
582
static const MemoryRegionOps omap2_gpio_module_ops = {
585
omap2_gpio_module_readp,
586
omap2_gpio_module_readp,
587
omap2_gpio_module_read,
590
omap2_gpio_module_writep,
591
omap2_gpio_module_writep,
592
omap2_gpio_module_write,
595
.endianness = DEVICE_NATIVE_ENDIAN,
598
static void omap_gpif_reset(DeviceState *dev)
600
struct omap_gpif_s *s = OMAP1_GPIO(dev);
602
omap_gpio_reset(&s->omap1);
605
static void omap2_gpif_reset(DeviceState *dev)
607
struct omap2_gpif_s *s = OMAP2_GPIO(dev);
610
for (i = 0; i < s->modulecount; i++) {
611
omap2_gpio_module_reset(&s->modules[i]);
617
static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
620
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
623
case 0x00: /* IPGENERICOCPSPL_REVISION */
626
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
629
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
632
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
635
case 0x40: /* IPGENERICOCPSPL_GPO */
638
case 0x50: /* IPGENERICOCPSPL_GPI */
646
static void omap2_gpif_top_write(void *opaque, hwaddr addr,
647
uint64_t value, unsigned size)
649
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
652
case 0x00: /* IPGENERICOCPSPL_REVISION */
653
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
654
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
655
case 0x50: /* IPGENERICOCPSPL_GPI */
659
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
660
if (value & (1 << 1)) /* SOFTRESET */
661
omap2_gpif_reset(DEVICE(s));
662
s->autoidle = value & 1;
665
case 0x40: /* IPGENERICOCPSPL_GPO */
675
static const MemoryRegionOps omap2_gpif_top_ops = {
676
.read = omap2_gpif_top_read,
677
.write = omap2_gpif_top_write,
678
.endianness = DEVICE_NATIVE_ENDIAN,
681
static int omap_gpio_init(SysBusDevice *sbd)
683
DeviceState *dev = DEVICE(sbd);
684
struct omap_gpif_s *s = OMAP1_GPIO(dev);
687
hw_error("omap-gpio: clk not connected\n");
689
qdev_init_gpio_in(dev, omap_gpio_set, 16);
690
qdev_init_gpio_out(dev, s->omap1.handler, 16);
691
sysbus_init_irq(sbd, &s->omap1.irq);
692
memory_region_init_io(&s->iomem, OBJECT(s), &omap_gpio_ops, &s->omap1,
693
"omap.gpio", 0x1000);
694
sysbus_init_mmio(sbd, &s->iomem);
698
static int omap2_gpio_init(SysBusDevice *sbd)
700
DeviceState *dev = DEVICE(sbd);
701
struct omap2_gpif_s *s = OMAP2_GPIO(dev);
705
hw_error("omap2-gpio: iclk not connected\n");
707
if (s->mpu_model < omap3430) {
708
s->modulecount = (s->mpu_model < omap2430) ? 4 : 5;
709
memory_region_init_io(&s->iomem, OBJECT(s), &omap2_gpif_top_ops, s,
710
"omap2.gpio", 0x1000);
711
sysbus_init_mmio(sbd, &s->iomem);
715
s->modules = g_malloc0(s->modulecount * sizeof(struct omap2_gpio_s));
716
s->handler = g_malloc0(s->modulecount * 32 * sizeof(qemu_irq));
717
qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
718
qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
719
for (i = 0; i < s->modulecount; i++) {
720
struct omap2_gpio_s *m = &s->modules[i];
722
hw_error("omap2-gpio: fclk%d not connected\n", i);
724
m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
725
m->handler = &s->handler[i * 32];
726
sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
727
sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
728
sysbus_init_irq(sbd, &m->wkup);
729
memory_region_init_io(&m->iomem, OBJECT(s), &omap2_gpio_module_ops, m,
730
"omap.gpio-module", 0x1000);
731
sysbus_init_mmio(sbd, &m->iomem);
736
/* Using qdev pointer properties for the clocks is not ideal.
737
* qdev should support a generic means of defining a 'port' with
738
* an arbitrary interface for connecting two devices. Then we
739
* could reframe the omap clock API in terms of clock ports,
740
* and get some type safety. For now the best qdev provides is
741
* passing an arbitrary pointer.
742
* (It's not possible to pass in the string which is the clock
743
* name, because this device does not have the necessary information
744
* (ie the struct omap_mpu_state_s*) to do the clockname to pointer
748
static Property omap_gpio_properties[] = {
749
DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
750
DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk),
751
DEFINE_PROP_END_OF_LIST(),
754
static void omap_gpio_class_init(ObjectClass *klass, void *data)
756
DeviceClass *dc = DEVICE_CLASS(klass);
757
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
759
k->init = omap_gpio_init;
760
dc->reset = omap_gpif_reset;
761
dc->props = omap_gpio_properties;
764
static const TypeInfo omap_gpio_info = {
765
.name = TYPE_OMAP1_GPIO,
766
.parent = TYPE_SYS_BUS_DEVICE,
767
.instance_size = sizeof(struct omap_gpif_s),
768
.class_init = omap_gpio_class_init,
771
static Property omap2_gpio_properties[] = {
772
DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
773
DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk),
774
DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]),
775
DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]),
776
DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]),
777
DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]),
778
DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]),
779
DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]),
780
DEFINE_PROP_END_OF_LIST(),
783
static void omap2_gpio_class_init(ObjectClass *klass, void *data)
785
DeviceClass *dc = DEVICE_CLASS(klass);
786
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
788
k->init = omap2_gpio_init;
789
dc->reset = omap2_gpif_reset;
790
dc->props = omap2_gpio_properties;
793
static const TypeInfo omap2_gpio_info = {
794
.name = TYPE_OMAP2_GPIO,
795
.parent = TYPE_SYS_BUS_DEVICE,
796
.instance_size = sizeof(struct omap2_gpif_s),
797
.class_init = omap2_gpio_class_init,
800
static void omap_gpio_register_types(void)
802
type_register_static(&omap_gpio_info);
803
type_register_static(&omap2_gpio_info);
806
type_init(omap_gpio_register_types)