1
From fb7196f6cae01cfcd522bf98c9bbf25596dccb4a Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Tue, 17 Dec 2013 19:42:29 +0000
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Subject: [PATCH 17/49] target-arm/kvm: Split 32 bit only code into its own
7
Split ARM KVM support code which is 32 bit specific out into its
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own file, which we only compile on 32 bit hosts. This will give
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us a place to add the 64 bit support code without adding lots of
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 1385645602-18662-2-git-send-email-peter.maydell@linaro.org
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Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
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target-arm/Makefile.objs | 1 +
17
target-arm/kvm.c | 491 --------------------------------------------
18
target-arm/kvm32.c | 515 +++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 516 insertions(+), 491 deletions(-)
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create mode 100644 target-arm/kvm32.c
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diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
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index 356fbfc..c9f7944 100644
24
--- a/target-arm/Makefile.objs
25
+++ b/target-arm/Makefile.objs
28
obj-$(CONFIG_SOFTMMU) += machine.o
29
obj-$(CONFIG_KVM) += kvm.o
30
+obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
31
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
32
obj-y += translate.o op_helper.o helper.o cpu.o
33
obj-y += neon_helper.o iwmmxt_helper.o
34
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
35
index f865dac..5cdb3b9 100644
36
--- a/target-arm/kvm.c
37
+++ b/target-arm/kvm.c
38
@@ -100,120 +100,6 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
42
-static inline void set_feature(uint64_t *features, int feature)
44
- *features |= 1ULL << feature;
47
-bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
49
- /* Identify the feature bits corresponding to the host CPU, and
50
- * fill out the ARMHostCPUClass fields accordingly. To do this
51
- * we have to create a scratch VM, create a single CPU inside it,
52
- * and then query that CPU for the relevant ID registers.
54
- int i, ret, fdarray[3];
55
- uint32_t midr, id_pfr0, id_isar0, mvfr1;
56
- uint64_t features = 0;
57
- /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
58
- * we know these will only support creating one kind of guest CPU,
59
- * which is its preferred CPU type.
61
- static const uint32_t cpus_to_try[] = {
62
- QEMU_KVM_ARM_TARGET_CORTEX_A15,
63
- QEMU_KVM_ARM_TARGET_NONE
65
- struct kvm_vcpu_init init;
66
- struct kvm_one_reg idregs[] = {
68
- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
69
- | ENCODE_CP_REG(15, 0, 0, 0, 0, 0),
70
- .addr = (uintptr_t)&midr,
73
- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
74
- | ENCODE_CP_REG(15, 0, 0, 1, 0, 0),
75
- .addr = (uintptr_t)&id_pfr0,
78
- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
79
- | ENCODE_CP_REG(15, 0, 0, 2, 0, 0),
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- .addr = (uintptr_t)&id_isar0,
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- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
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- | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
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- .addr = (uintptr_t)&mvfr1,
89
- if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
93
- ahcc->target = init.target;
95
- /* This is not strictly blessed by the device tree binding docs yet,
96
- * but in practice the kernel does not care about this string so
97
- * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
99
- ahcc->dtb_compatible = "arm,arm-v7";
101
- for (i = 0; i < ARRAY_SIZE(idregs); i++) {
102
- ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
108
- kvm_arm_destroy_scratch_host_vcpu(fdarray);
114
- /* Now we've retrieved all the register information we can
115
- * set the feature bits based on the ID register fields.
116
- * We can assume any KVM supporting CPU is at least a v7
117
- * with VFPv3, LPAE and the generic timers; this in turn implies
118
- * most of the other feature bits, but a few must be tested.
120
- set_feature(&features, ARM_FEATURE_V7);
121
- set_feature(&features, ARM_FEATURE_VFP3);
122
- set_feature(&features, ARM_FEATURE_LPAE);
123
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
125
- switch (extract32(id_isar0, 24, 4)) {
127
- set_feature(&features, ARM_FEATURE_THUMB_DIV);
130
- set_feature(&features, ARM_FEATURE_ARM_DIV);
131
- set_feature(&features, ARM_FEATURE_THUMB_DIV);
137
- if (extract32(id_pfr0, 12, 4) == 1) {
138
- set_feature(&features, ARM_FEATURE_THUMB2EE);
140
- if (extract32(mvfr1, 20, 4) == 1) {
141
- set_feature(&features, ARM_FEATURE_VFP_FP16);
143
- if (extract32(mvfr1, 12, 4) == 1) {
144
- set_feature(&features, ARM_FEATURE_NEON);
146
- if (extract32(mvfr1, 28, 4) == 1) {
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- /* FMAC support implies VFPv4 */
148
- set_feature(&features, ARM_FEATURE_VFP4);
151
- ahcc->features = features;
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static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data)
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ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc);
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@@ -265,144 +151,6 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
160
return cpu->cpu_index;
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-static bool reg_syncs_via_tuple_list(uint64_t regidx)
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- /* Return true if the regidx is a register we should synchronize
166
- * via the cpreg_tuples array (ie is not a core reg we sync by
167
- * hand in kvm_arch_get/put_registers())
169
- switch (regidx & KVM_REG_ARM_COPROC_MASK) {
170
- case KVM_REG_ARM_CORE:
171
- case KVM_REG_ARM_VFP:
178
-static int compare_u64(const void *a, const void *b)
180
- if (*(uint64_t *)a > *(uint64_t *)b) {
183
- if (*(uint64_t *)a < *(uint64_t *)b) {
189
-int kvm_arch_init_vcpu(CPUState *cs)
191
- struct kvm_vcpu_init init;
192
- int i, ret, arraylen;
194
- struct kvm_one_reg r;
195
- struct kvm_reg_list rl;
196
- struct kvm_reg_list *rlp;
197
- ARMCPU *cpu = ARM_CPU(cs);
199
- if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
200
- fprintf(stderr, "KVM is not supported for this guest CPU type\n");
204
- init.target = cpu->kvm_target;
205
- memset(init.features, 0, sizeof(init.features));
206
- if (cpu->start_powered_off) {
207
- init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF;
209
- ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
213
- /* Query the kernel to make sure it supports 32 VFP
214
- * registers: QEMU's "cortex-a15" CPU is always a
215
- * VFP-D32 core. The simplest way to do this is just
216
- * to attempt to read register d31.
218
- r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
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- r.addr = (uintptr_t)(&v);
220
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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- if (ret == -ENOENT) {
225
- /* Populate the cpreg list based on the kernel's idea
226
- * of what registers exist (and throw away the TCG-created list).
229
- ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
230
- if (ret != -E2BIG) {
233
- rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
235
- ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
239
- /* Sort the list we get back from the kernel, since cpreg_tuples
240
- * must be in strictly ascending order.
242
- qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
244
- for (i = 0, arraylen = 0; i < rlp->n; i++) {
245
- if (!reg_syncs_via_tuple_list(rlp->reg[i])) {
248
- switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
249
- case KVM_REG_SIZE_U32:
250
- case KVM_REG_SIZE_U64:
253
- fprintf(stderr, "Can't handle size of register in kernel list\n");
261
- cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
262
- cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
263
- cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
265
- cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
267
- cpu->cpreg_array_len = arraylen;
268
- cpu->cpreg_vmstate_array_len = arraylen;
270
- for (i = 0, arraylen = 0; i < rlp->n; i++) {
271
- uint64_t regidx = rlp->reg[i];
272
- if (!reg_syncs_via_tuple_list(regidx)) {
275
- cpu->cpreg_indexes[arraylen] = regidx;
278
- assert(cpu->cpreg_array_len == arraylen);
280
- if (!write_kvmstate_to_list(cpu)) {
281
- /* Shouldn't happen unless kernel is inconsistent about
282
- * what registers exist.
284
- fprintf(stderr, "Initial read of kernel register state failed\n");
289
- /* Save a copy of the initial register values so that we can
290
- * feed it back to the kernel on VCPU reset.
292
- cpu->cpreg_reset_values = g_memdup(cpu->cpreg_values,
293
- cpu->cpreg_array_len *
294
- sizeof(cpu->cpreg_values[0]));
301
/* We track all the KVM devices which need their memory addresses
302
* passing to the kernel in a list of these structures.
303
* When board init is complete we run through the list and
304
@@ -563,232 +311,6 @@ bool write_list_to_kvmstate(ARMCPU *cpu)
308
-typedef struct Reg {
313
-#define COREREG(KERNELNAME, QEMUFIELD) \
315
- KVM_REG_ARM | KVM_REG_SIZE_U32 | \
316
- KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
317
- offsetof(CPUARMState, QEMUFIELD) \
320
-#define VFPSYSREG(R) \
322
- KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
323
- KVM_REG_ARM_VFP_##R, \
324
- offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
327
-static const Reg regs[] = {
328
- /* R0_usr .. R14_usr */
329
- COREREG(usr_regs.uregs[0], regs[0]),
330
- COREREG(usr_regs.uregs[1], regs[1]),
331
- COREREG(usr_regs.uregs[2], regs[2]),
332
- COREREG(usr_regs.uregs[3], regs[3]),
333
- COREREG(usr_regs.uregs[4], regs[4]),
334
- COREREG(usr_regs.uregs[5], regs[5]),
335
- COREREG(usr_regs.uregs[6], regs[6]),
336
- COREREG(usr_regs.uregs[7], regs[7]),
337
- COREREG(usr_regs.uregs[8], usr_regs[0]),
338
- COREREG(usr_regs.uregs[9], usr_regs[1]),
339
- COREREG(usr_regs.uregs[10], usr_regs[2]),
340
- COREREG(usr_regs.uregs[11], usr_regs[3]),
341
- COREREG(usr_regs.uregs[12], usr_regs[4]),
342
- COREREG(usr_regs.uregs[13], banked_r13[0]),
343
- COREREG(usr_regs.uregs[14], banked_r14[0]),
344
- /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
345
- COREREG(svc_regs[0], banked_r13[1]),
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- COREREG(svc_regs[1], banked_r14[1]),
347
- COREREG(svc_regs[2], banked_spsr[1]),
348
- COREREG(abt_regs[0], banked_r13[2]),
349
- COREREG(abt_regs[1], banked_r14[2]),
350
- COREREG(abt_regs[2], banked_spsr[2]),
351
- COREREG(und_regs[0], banked_r13[3]),
352
- COREREG(und_regs[1], banked_r14[3]),
353
- COREREG(und_regs[2], banked_spsr[3]),
354
- COREREG(irq_regs[0], banked_r13[4]),
355
- COREREG(irq_regs[1], banked_r14[4]),
356
- COREREG(irq_regs[2], banked_spsr[4]),
357
- /* R8_fiq .. R14_fiq and SPSR_fiq */
358
- COREREG(fiq_regs[0], fiq_regs[0]),
359
- COREREG(fiq_regs[1], fiq_regs[1]),
360
- COREREG(fiq_regs[2], fiq_regs[2]),
361
- COREREG(fiq_regs[3], fiq_regs[3]),
362
- COREREG(fiq_regs[4], fiq_regs[4]),
363
- COREREG(fiq_regs[5], banked_r13[5]),
364
- COREREG(fiq_regs[6], banked_r14[5]),
365
- COREREG(fiq_regs[7], banked_spsr[5]),
367
- COREREG(usr_regs.uregs[15], regs[15]),
368
- /* VFP system registers */
374
- VFPSYSREG(FPINST2),
377
-int kvm_arch_put_registers(CPUState *cs, int level)
379
- ARMCPU *cpu = ARM_CPU(cs);
380
- CPUARMState *env = &cpu->env;
381
- struct kvm_one_reg r;
384
- uint32_t cpsr, fpscr;
386
- /* Make sure the banked regs are properly set */
387
- mode = env->uncached_cpsr & CPSR_M;
388
- bn = bank_number(mode);
389
- if (mode == ARM_CPU_MODE_FIQ) {
390
- memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
392
- memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
394
- env->banked_r13[bn] = env->regs[13];
395
- env->banked_r14[bn] = env->regs[14];
396
- env->banked_spsr[bn] = env->spsr;
398
- /* Now we can safely copy stuff down to the kernel */
399
- for (i = 0; i < ARRAY_SIZE(regs); i++) {
401
- r.addr = (uintptr_t)(env) + regs[i].offset;
402
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
408
- /* Special cases which aren't a single CPUARMState field */
409
- cpsr = cpsr_read(env);
410
- r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
411
- KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
412
- r.addr = (uintptr_t)(&cpsr);
413
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
418
- /* VFP registers */
419
- r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
420
- for (i = 0; i < 32; i++) {
421
- r.addr = (uintptr_t)(&env->vfp.regs[i]);
422
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
429
- r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
430
- KVM_REG_ARM_VFP_FPSCR;
431
- fpscr = vfp_get_fpscr(env);
432
- r.addr = (uintptr_t)&fpscr;
433
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
438
- /* Note that we do not call write_cpustate_to_list()
439
- * here, so we are only writing the tuple list back to
440
- * KVM. This is safe because nothing can change the
441
- * CPUARMState cp15 fields (in particular gdb accesses cannot)
442
- * and so there are no changes to sync. In fact syncing would
443
- * be wrong at this point: for a constant register where TCG and
444
- * KVM disagree about its value, the preceding write_list_to_cpustate()
445
- * would not have had any effect on the CPUARMState value (since the
446
- * register is read-only), and a write_cpustate_to_list() here would
447
- * then try to write the TCG value back into KVM -- this would either
448
- * fail or incorrectly change the value the guest sees.
450
- * If we ever want to allow the user to modify cp15 registers via
451
- * the gdb stub, we would need to be more clever here (for instance
452
- * tracking the set of registers kvm_arch_get_registers() successfully
453
- * managed to update the CPUARMState with, and only allowing those
454
- * to be written back up into the kernel).
456
- if (!write_list_to_kvmstate(cpu)) {
463
-int kvm_arch_get_registers(CPUState *cs)
465
- ARMCPU *cpu = ARM_CPU(cs);
466
- CPUARMState *env = &cpu->env;
467
- struct kvm_one_reg r;
470
- uint32_t cpsr, fpscr;
472
- for (i = 0; i < ARRAY_SIZE(regs); i++) {
474
- r.addr = (uintptr_t)(env) + regs[i].offset;
475
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
481
- /* Special cases which aren't a single CPUARMState field */
482
- r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
483
- KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
484
- r.addr = (uintptr_t)(&cpsr);
485
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
489
- cpsr_write(env, cpsr, 0xffffffff);
491
- /* Make sure the current mode regs are properly set */
492
- mode = env->uncached_cpsr & CPSR_M;
493
- bn = bank_number(mode);
494
- if (mode == ARM_CPU_MODE_FIQ) {
495
- memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
497
- memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
499
- env->regs[13] = env->banked_r13[bn];
500
- env->regs[14] = env->banked_r14[bn];
501
- env->spsr = env->banked_spsr[bn];
503
- /* VFP registers */
504
- r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
505
- for (i = 0; i < 32; i++) {
506
- r.addr = (uintptr_t)(&env->vfp.regs[i]);
507
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
514
- r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
515
- KVM_REG_ARM_VFP_FPSCR;
516
- r.addr = (uintptr_t)&fpscr;
517
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
521
- vfp_set_fpscr(env, fpscr);
523
- if (!write_kvmstate_to_list(cpu)) {
526
- /* Note that it's OK to have registers which aren't in CPUState,
527
- * so we can ignore a failure return here.
529
- write_list_to_cpustate(cpu);
534
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
537
@@ -802,19 +324,6 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
541
-void kvm_arch_reset_vcpu(CPUState *cs)
543
- /* Feed the kernel back its initial register state */
544
- ARMCPU *cpu = ARM_CPU(cs);
546
- memmove(cpu->cpreg_values, cpu->cpreg_reset_values,
547
- cpu->cpreg_array_len * sizeof(cpu->cpreg_values[0]));
549
- if (!write_list_to_kvmstate(cpu)) {
554
bool kvm_arch_stop_on_emulation_error(CPUState *cs)
557
diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c
559
index 0000000..a4fde07
561
+++ b/target-arm/kvm32.c
564
+ * ARM implementation of KVM hooks, 32 bit specific code.
566
+ * Copyright Christoffer Dall 2009-2010
568
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
569
+ * See the COPYING file in the top-level directory.
574
+#include <sys/types.h>
575
+#include <sys/ioctl.h>
576
+#include <sys/mman.h>
578
+#include <linux/kvm.h>
580
+#include "qemu-common.h"
581
+#include "qemu/timer.h"
582
+#include "sysemu/sysemu.h"
583
+#include "sysemu/kvm.h"
584
+#include "kvm_arm.h"
586
+#include "hw/arm/arm.h"
588
+static inline void set_feature(uint64_t *features, int feature)
590
+ *features |= 1ULL << feature;
593
+bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
595
+ /* Identify the feature bits corresponding to the host CPU, and
596
+ * fill out the ARMHostCPUClass fields accordingly. To do this
597
+ * we have to create a scratch VM, create a single CPU inside it,
598
+ * and then query that CPU for the relevant ID registers.
600
+ int i, ret, fdarray[3];
601
+ uint32_t midr, id_pfr0, id_isar0, mvfr1;
602
+ uint64_t features = 0;
603
+ /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
604
+ * we know these will only support creating one kind of guest CPU,
605
+ * which is its preferred CPU type.
607
+ static const uint32_t cpus_to_try[] = {
608
+ QEMU_KVM_ARM_TARGET_CORTEX_A15,
609
+ QEMU_KVM_ARM_TARGET_NONE
611
+ struct kvm_vcpu_init init;
612
+ struct kvm_one_reg idregs[] = {
614
+ .id = KVM_REG_ARM | KVM_REG_SIZE_U32
615
+ | ENCODE_CP_REG(15, 0, 0, 0, 0, 0),
616
+ .addr = (uintptr_t)&midr,
619
+ .id = KVM_REG_ARM | KVM_REG_SIZE_U32
620
+ | ENCODE_CP_REG(15, 0, 0, 1, 0, 0),
621
+ .addr = (uintptr_t)&id_pfr0,
624
+ .id = KVM_REG_ARM | KVM_REG_SIZE_U32
625
+ | ENCODE_CP_REG(15, 0, 0, 2, 0, 0),
626
+ .addr = (uintptr_t)&id_isar0,
629
+ .id = KVM_REG_ARM | KVM_REG_SIZE_U32
630
+ | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
631
+ .addr = (uintptr_t)&mvfr1,
635
+ if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
639
+ ahcc->target = init.target;
641
+ /* This is not strictly blessed by the device tree binding docs yet,
642
+ * but in practice the kernel does not care about this string so
643
+ * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
645
+ ahcc->dtb_compatible = "arm,arm-v7";
647
+ for (i = 0; i < ARRAY_SIZE(idregs); i++) {
648
+ ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
654
+ kvm_arm_destroy_scratch_host_vcpu(fdarray);
660
+ /* Now we've retrieved all the register information we can
661
+ * set the feature bits based on the ID register fields.
662
+ * We can assume any KVM supporting CPU is at least a v7
663
+ * with VFPv3, LPAE and the generic timers; this in turn implies
664
+ * most of the other feature bits, but a few must be tested.
666
+ set_feature(&features, ARM_FEATURE_V7);
667
+ set_feature(&features, ARM_FEATURE_VFP3);
668
+ set_feature(&features, ARM_FEATURE_LPAE);
669
+ set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
671
+ switch (extract32(id_isar0, 24, 4)) {
673
+ set_feature(&features, ARM_FEATURE_THUMB_DIV);
676
+ set_feature(&features, ARM_FEATURE_ARM_DIV);
677
+ set_feature(&features, ARM_FEATURE_THUMB_DIV);
683
+ if (extract32(id_pfr0, 12, 4) == 1) {
684
+ set_feature(&features, ARM_FEATURE_THUMB2EE);
686
+ if (extract32(mvfr1, 20, 4) == 1) {
687
+ set_feature(&features, ARM_FEATURE_VFP_FP16);
689
+ if (extract32(mvfr1, 12, 4) == 1) {
690
+ set_feature(&features, ARM_FEATURE_NEON);
692
+ if (extract32(mvfr1, 28, 4) == 1) {
693
+ /* FMAC support implies VFPv4 */
694
+ set_feature(&features, ARM_FEATURE_VFP4);
697
+ ahcc->features = features;
702
+static bool reg_syncs_via_tuple_list(uint64_t regidx)
704
+ /* Return true if the regidx is a register we should synchronize
705
+ * via the cpreg_tuples array (ie is not a core reg we sync by
706
+ * hand in kvm_arch_get/put_registers())
708
+ switch (regidx & KVM_REG_ARM_COPROC_MASK) {
709
+ case KVM_REG_ARM_CORE:
710
+ case KVM_REG_ARM_VFP:
717
+static int compare_u64(const void *a, const void *b)
719
+ if (*(uint64_t *)a > *(uint64_t *)b) {
722
+ if (*(uint64_t *)a < *(uint64_t *)b) {
728
+int kvm_arch_init_vcpu(CPUState *cs)
730
+ struct kvm_vcpu_init init;
731
+ int i, ret, arraylen;
733
+ struct kvm_one_reg r;
734
+ struct kvm_reg_list rl;
735
+ struct kvm_reg_list *rlp;
736
+ ARMCPU *cpu = ARM_CPU(cs);
738
+ if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
739
+ fprintf(stderr, "KVM is not supported for this guest CPU type\n");
743
+ init.target = cpu->kvm_target;
744
+ memset(init.features, 0, sizeof(init.features));
745
+ if (cpu->start_powered_off) {
746
+ init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF;
748
+ ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
752
+ /* Query the kernel to make sure it supports 32 VFP
753
+ * registers: QEMU's "cortex-a15" CPU is always a
754
+ * VFP-D32 core. The simplest way to do this is just
755
+ * to attempt to read register d31.
757
+ r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
758
+ r.addr = (uintptr_t)(&v);
759
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
760
+ if (ret == -ENOENT) {
764
+ /* Populate the cpreg list based on the kernel's idea
765
+ * of what registers exist (and throw away the TCG-created list).
768
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
769
+ if (ret != -E2BIG) {
772
+ rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
774
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
778
+ /* Sort the list we get back from the kernel, since cpreg_tuples
779
+ * must be in strictly ascending order.
781
+ qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
783
+ for (i = 0, arraylen = 0; i < rlp->n; i++) {
784
+ if (!reg_syncs_via_tuple_list(rlp->reg[i])) {
787
+ switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
788
+ case KVM_REG_SIZE_U32:
789
+ case KVM_REG_SIZE_U64:
792
+ fprintf(stderr, "Can't handle size of register in kernel list\n");
800
+ cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
801
+ cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
802
+ cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
804
+ cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
806
+ cpu->cpreg_array_len = arraylen;
807
+ cpu->cpreg_vmstate_array_len = arraylen;
809
+ for (i = 0, arraylen = 0; i < rlp->n; i++) {
810
+ uint64_t regidx = rlp->reg[i];
811
+ if (!reg_syncs_via_tuple_list(regidx)) {
814
+ cpu->cpreg_indexes[arraylen] = regidx;
817
+ assert(cpu->cpreg_array_len == arraylen);
819
+ if (!write_kvmstate_to_list(cpu)) {
820
+ /* Shouldn't happen unless kernel is inconsistent about
821
+ * what registers exist.
823
+ fprintf(stderr, "Initial read of kernel register state failed\n");
828
+ /* Save a copy of the initial register values so that we can
829
+ * feed it back to the kernel on VCPU reset.
831
+ cpu->cpreg_reset_values = g_memdup(cpu->cpreg_values,
832
+ cpu->cpreg_array_len *
833
+ sizeof(cpu->cpreg_values[0]));
840
+typedef struct Reg {
845
+#define COREREG(KERNELNAME, QEMUFIELD) \
847
+ KVM_REG_ARM | KVM_REG_SIZE_U32 | \
848
+ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
849
+ offsetof(CPUARMState, QEMUFIELD) \
852
+#define VFPSYSREG(R) \
854
+ KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
855
+ KVM_REG_ARM_VFP_##R, \
856
+ offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
859
+static const Reg regs[] = {
860
+ /* R0_usr .. R14_usr */
861
+ COREREG(usr_regs.uregs[0], regs[0]),
862
+ COREREG(usr_regs.uregs[1], regs[1]),
863
+ COREREG(usr_regs.uregs[2], regs[2]),
864
+ COREREG(usr_regs.uregs[3], regs[3]),
865
+ COREREG(usr_regs.uregs[4], regs[4]),
866
+ COREREG(usr_regs.uregs[5], regs[5]),
867
+ COREREG(usr_regs.uregs[6], regs[6]),
868
+ COREREG(usr_regs.uregs[7], regs[7]),
869
+ COREREG(usr_regs.uregs[8], usr_regs[0]),
870
+ COREREG(usr_regs.uregs[9], usr_regs[1]),
871
+ COREREG(usr_regs.uregs[10], usr_regs[2]),
872
+ COREREG(usr_regs.uregs[11], usr_regs[3]),
873
+ COREREG(usr_regs.uregs[12], usr_regs[4]),
874
+ COREREG(usr_regs.uregs[13], banked_r13[0]),
875
+ COREREG(usr_regs.uregs[14], banked_r14[0]),
876
+ /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
877
+ COREREG(svc_regs[0], banked_r13[1]),
878
+ COREREG(svc_regs[1], banked_r14[1]),
879
+ COREREG(svc_regs[2], banked_spsr[1]),
880
+ COREREG(abt_regs[0], banked_r13[2]),
881
+ COREREG(abt_regs[1], banked_r14[2]),
882
+ COREREG(abt_regs[2], banked_spsr[2]),
883
+ COREREG(und_regs[0], banked_r13[3]),
884
+ COREREG(und_regs[1], banked_r14[3]),
885
+ COREREG(und_regs[2], banked_spsr[3]),
886
+ COREREG(irq_regs[0], banked_r13[4]),
887
+ COREREG(irq_regs[1], banked_r14[4]),
888
+ COREREG(irq_regs[2], banked_spsr[4]),
889
+ /* R8_fiq .. R14_fiq and SPSR_fiq */
890
+ COREREG(fiq_regs[0], fiq_regs[0]),
891
+ COREREG(fiq_regs[1], fiq_regs[1]),
892
+ COREREG(fiq_regs[2], fiq_regs[2]),
893
+ COREREG(fiq_regs[3], fiq_regs[3]),
894
+ COREREG(fiq_regs[4], fiq_regs[4]),
895
+ COREREG(fiq_regs[5], banked_r13[5]),
896
+ COREREG(fiq_regs[6], banked_r14[5]),
897
+ COREREG(fiq_regs[7], banked_spsr[5]),
899
+ COREREG(usr_regs.uregs[15], regs[15]),
900
+ /* VFP system registers */
906
+ VFPSYSREG(FPINST2),
909
+int kvm_arch_put_registers(CPUState *cs, int level)
911
+ ARMCPU *cpu = ARM_CPU(cs);
912
+ CPUARMState *env = &cpu->env;
913
+ struct kvm_one_reg r;
916
+ uint32_t cpsr, fpscr;
918
+ /* Make sure the banked regs are properly set */
919
+ mode = env->uncached_cpsr & CPSR_M;
920
+ bn = bank_number(mode);
921
+ if (mode == ARM_CPU_MODE_FIQ) {
922
+ memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
924
+ memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
926
+ env->banked_r13[bn] = env->regs[13];
927
+ env->banked_r14[bn] = env->regs[14];
928
+ env->banked_spsr[bn] = env->spsr;
930
+ /* Now we can safely copy stuff down to the kernel */
931
+ for (i = 0; i < ARRAY_SIZE(regs); i++) {
933
+ r.addr = (uintptr_t)(env) + regs[i].offset;
934
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
940
+ /* Special cases which aren't a single CPUARMState field */
941
+ cpsr = cpsr_read(env);
942
+ r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
943
+ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
944
+ r.addr = (uintptr_t)(&cpsr);
945
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
950
+ /* VFP registers */
951
+ r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
952
+ for (i = 0; i < 32; i++) {
953
+ r.addr = (uintptr_t)(&env->vfp.regs[i]);
954
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
961
+ r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
962
+ KVM_REG_ARM_VFP_FPSCR;
963
+ fpscr = vfp_get_fpscr(env);
964
+ r.addr = (uintptr_t)&fpscr;
965
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
970
+ /* Note that we do not call write_cpustate_to_list()
971
+ * here, so we are only writing the tuple list back to
972
+ * KVM. This is safe because nothing can change the
973
+ * CPUARMState cp15 fields (in particular gdb accesses cannot)
974
+ * and so there are no changes to sync. In fact syncing would
975
+ * be wrong at this point: for a constant register where TCG and
976
+ * KVM disagree about its value, the preceding write_list_to_cpustate()
977
+ * would not have had any effect on the CPUARMState value (since the
978
+ * register is read-only), and a write_cpustate_to_list() here would
979
+ * then try to write the TCG value back into KVM -- this would either
980
+ * fail or incorrectly change the value the guest sees.
982
+ * If we ever want to allow the user to modify cp15 registers via
983
+ * the gdb stub, we would need to be more clever here (for instance
984
+ * tracking the set of registers kvm_arch_get_registers() successfully
985
+ * managed to update the CPUARMState with, and only allowing those
986
+ * to be written back up into the kernel).
988
+ if (!write_list_to_kvmstate(cpu)) {
995
+int kvm_arch_get_registers(CPUState *cs)
997
+ ARMCPU *cpu = ARM_CPU(cs);
998
+ CPUARMState *env = &cpu->env;
999
+ struct kvm_one_reg r;
1002
+ uint32_t cpsr, fpscr;
1004
+ for (i = 0; i < ARRAY_SIZE(regs); i++) {
1005
+ r.id = regs[i].id;
1006
+ r.addr = (uintptr_t)(env) + regs[i].offset;
1007
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
1013
+ /* Special cases which aren't a single CPUARMState field */
1014
+ r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
1015
+ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
1016
+ r.addr = (uintptr_t)(&cpsr);
1017
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
1021
+ cpsr_write(env, cpsr, 0xffffffff);
1023
+ /* Make sure the current mode regs are properly set */
1024
+ mode = env->uncached_cpsr & CPSR_M;
1025
+ bn = bank_number(mode);
1026
+ if (mode == ARM_CPU_MODE_FIQ) {
1027
+ memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
1029
+ memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
1031
+ env->regs[13] = env->banked_r13[bn];
1032
+ env->regs[14] = env->banked_r14[bn];
1033
+ env->spsr = env->banked_spsr[bn];
1035
+ /* VFP registers */
1036
+ r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
1037
+ for (i = 0; i < 32; i++) {
1038
+ r.addr = (uintptr_t)(&env->vfp.regs[i]);
1039
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
1046
+ r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
1047
+ KVM_REG_ARM_VFP_FPSCR;
1048
+ r.addr = (uintptr_t)&fpscr;
1049
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
1053
+ vfp_set_fpscr(env, fpscr);
1055
+ if (!write_kvmstate_to_list(cpu)) {
1058
+ /* Note that it's OK to have registers which aren't in CPUState,
1059
+ * so we can ignore a failure return here.
1061
+ write_list_to_cpustate(cpu);
1066
+void kvm_arch_reset_vcpu(CPUState *cs)
1068
+ /* Feed the kernel back its initial register state */
1069
+ ARMCPU *cpu = ARM_CPU(cs);
1071
+ memmove(cpu->cpreg_values, cpu->cpreg_reset_values,
1072
+ cpu->cpreg_array_len * sizeof(cpu->cpreg_values[0]));
1074
+ if (!write_list_to_kvmstate(cpu)) {