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From 99de47d546424fb097ece8832bc514e1f2fd1a6e Mon Sep 17 00:00:00 2001
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From: Alexander Graf <agraf@suse.de>
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Date: Tue, 17 Dec 2013 19:42:33 +0000
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Subject: [PATCH 34/49] target-arm: A64: add support for 'test and branch' imm
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This patch adds emulation for the test and branch insns,
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Signed-off-by: Alexander Graf <agraf@suse.de>
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adapted for new decoder
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remove a TCG temporary
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Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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target-arm/translate-a64.c | 27 +++++++++++++++++++++++++--
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1 file changed, 25 insertions(+), 2 deletions(-)
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diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
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index 4eb2992..1d04303 100644
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--- a/target-arm/translate-a64.c
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+++ b/target-arm/translate-a64.c
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@@ -233,10 +233,33 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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-/* Test & branch (immediate) */
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+/* C3.2.5 Test & branch (immediate)
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+ * 31 30 25 24 23 19 18 5 4 0
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+ * +----+-------------+----+-------+-------------+------+
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+ * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
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+ * +----+-------------+----+-------+-------------+------+
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static void disas_test_b_imm(DisasContext *s, uint32_t insn)
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- unsupported_encoding(s, insn);
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+ unsigned int bit_pos, op, rt;
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+ bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
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+ op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
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+ addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
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+ rt = extract32(insn, 0, 5);
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+ tcg_cmp = tcg_temp_new_i64();
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+ tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
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+ label_match = gen_new_label();
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+ tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
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+ tcg_cmp, 0, label_match);
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+ tcg_temp_free_i64(tcg_cmp);
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+ gen_goto_tb(s, 0, s->pc);
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+ gen_set_label(label_match);
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+ gen_goto_tb(s, 1, addr);
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/* C3.2.2 / C5.6.19 Conditional branch (immediate)