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* Texas Instruments OMAP processors.
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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#include "exec/memory.h"
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# define hw_omap_h "omap.h"
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# define OMAP_EMIFS_BASE 0x00000000
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# define OMAP2_Q0_BASE 0x00000000
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# define OMAP_CS0_BASE 0x00000000
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# define OMAP_CS1_BASE 0x04000000
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# define OMAP_CS2_BASE 0x08000000
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# define OMAP_CS3_BASE 0x0c000000
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# define OMAP_EMIFF_BASE 0x10000000
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# define OMAP_IMIF_BASE 0x20000000
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# define OMAP_LOCALBUS_BASE 0x30000000
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# define OMAP2_Q1_BASE 0x40000000
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# define OMAP2_L4_BASE 0x48000000
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# define OMAP2_SRAM_BASE 0x40200000
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# define OMAP2_L3_BASE 0x68000000
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# define OMAP2_Q2_BASE 0x80000000
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# define OMAP2_Q3_BASE 0xc0000000
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# define OMAP3_Q1_BASE 0x40000000
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# define OMAP3_L4_BASE 0x48000000
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# define OMAP3_SRAM_BASE 0x40200000
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# define OMAP3_L3_BASE 0x68000000
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# define OMAP3_Q2_BASE 0x80000000
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# define OMAP3_Q3_BASE 0xc0000000
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# define OMAP_MPUI_BASE 0xe1000000
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# define OMAP730_SRAM_SIZE 0x00032000
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# define OMAP15XX_SRAM_SIZE 0x00030000
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# define OMAP16XX_SRAM_SIZE 0x00004000
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# define OMAP1611_SRAM_SIZE 0x0003e800
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# define OMAP242X_SRAM_SIZE 0x000a0000
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# define OMAP243X_SRAM_SIZE 0x00010000
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# define OMAP3XXX_SRAM_SIZE 0x00010000
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# define OMAP3XXX_BOOTROM_SIZE 0x00008000
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# define OMAP_CS0_SIZE 0x04000000
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# define OMAP_CS1_SIZE 0x04000000
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# define OMAP_CS2_SIZE 0x04000000
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# define OMAP_CS3_SIZE 0x04000000
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struct omap_mpu_state_s;
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typedef struct clk *omap_clk;
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omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
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void omap_clk_init(struct omap_mpu_state_s *mpu);
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void omap_clk_adduser(struct clk *clk, qemu_irq user);
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void omap_clk_get(omap_clk clk);
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void omap_clk_put(omap_clk clk);
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void omap_clk_onoff(omap_clk clk, int on);
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void omap_clk_canidle(omap_clk clk, int can);
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void omap_clk_setrate(omap_clk clk, int divide, int multiply);
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int64_t omap_clk_getrate(omap_clk clk);
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void omap_clk_reparent(omap_clk clk, omap_clk parent);
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/* OMAP2 l4 Interconnect */
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struct omap_l4_region_s;
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L4TYPE_GENERIC = 0, /* not mapped by default, must be mapped separately */
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L4TYPE_IA, /* initiator agent */
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L4TYPE_TA, /* target agent */
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L4TYPE_LA, /* link register agent */
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L4TYPE_AP /* address protection */
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} omap3_l4_region_type_t;
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struct omap2_l4_agent_info_s {
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struct omap3_l4_agent_info_s {
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struct omap_target_agent_s {
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struct omap_l4_s *bus;
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const struct omap_l4_region_s *start;
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struct omap_l4_region_s {
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int access; /* omap3_l4_region_type_t for OMAP3 */
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struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
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hwaddr base, int ta_num,
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struct omap_target_agent_s *omap2_l4ta_init(
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struct omap_l4_s *bus,
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const struct omap_l4_region_s *regions,
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const struct omap2_l4_agent_info_s *agents,
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struct omap_target_agent_s *omap3_l4ta_init(
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struct omap_l4_s *bus,
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const struct omap_l4_region_s *regions,
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const struct omap3_l4_agent_info_s *agents,
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hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
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int region, MemoryRegion *mr);
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hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
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hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
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/* OMAP2 SDRAM controller */
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struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
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void omap_sdrc_reset(struct omap_sdrc_s *s);
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/* OMAP2 general purpose memory controller */
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struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
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qemu_irq irq, qemu_irq drq);
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void omap_gpmc_reset(struct omap_gpmc_s *s);
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
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void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
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* Common IRQ numbers for level 1 interrupt handler
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* See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
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# define OMAP_INT_CAMERA 1
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# define OMAP_INT_FIQ 3
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# define OMAP_INT_RTDX 6
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# define OMAP_INT_DSP_MMU_ABORT 7
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# define OMAP_INT_HOST 8
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# define OMAP_INT_ABORT 9
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# define OMAP_INT_BRIDGE_PRIV 13
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# define OMAP_INT_GPIO_BANK1 14
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# define OMAP_INT_UART3 15
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# define OMAP_INT_TIMER3 16
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# define OMAP_INT_DMA_CH0_6 19
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# define OMAP_INT_DMA_CH1_7 20
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# define OMAP_INT_DMA_CH2_8 21
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# define OMAP_INT_DMA_CH3 22
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# define OMAP_INT_DMA_CH4 23
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# define OMAP_INT_DMA_CH5 24
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# define OMAP_INT_DMA_LCD 25
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# define OMAP_INT_TIMER1 26
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# define OMAP_INT_WD_TIMER 27
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# define OMAP_INT_BRIDGE_PUB 28
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# define OMAP_INT_TIMER2 30
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# define OMAP_INT_LCD_CTRL 31
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* Common OMAP-15xx IRQ numbers for level 1 interrupt handler
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# define OMAP_INT_15XX_IH2_IRQ 0
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# define OMAP_INT_15XX_LB_MMU 17
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# define OMAP_INT_15XX_LOCAL_BUS 29
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* OMAP-1510 specific IRQ numbers for level 1 interrupt handler
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# define OMAP_INT_1510_SPI_TX 4
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# define OMAP_INT_1510_SPI_RX 5
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# define OMAP_INT_1510_DSP_MAILBOX1 10
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# define OMAP_INT_1510_DSP_MAILBOX2 11
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* OMAP-310 specific IRQ numbers for level 1 interrupt handler
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# define OMAP_INT_310_McBSP2_TX 4
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# define OMAP_INT_310_McBSP2_RX 5
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# define OMAP_INT_310_HSB_MAILBOX1 12
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# define OMAP_INT_310_HSAB_MMU 18
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* OMAP-1610 specific IRQ numbers for level 1 interrupt handler
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# define OMAP_INT_1610_IH2_IRQ 0
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# define OMAP_INT_1610_IH2_FIQ 2
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# define OMAP_INT_1610_McBSP2_TX 4
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# define OMAP_INT_1610_McBSP2_RX 5
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# define OMAP_INT_1610_DSP_MAILBOX1 10
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# define OMAP_INT_1610_DSP_MAILBOX2 11
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# define OMAP_INT_1610_LCD_LINE 12
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# define OMAP_INT_1610_GPTIMER1 17
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# define OMAP_INT_1610_GPTIMER2 18
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# define OMAP_INT_1610_SSR_FIFO_0 29
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* OMAP-730 specific IRQ numbers for level 1 interrupt handler
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# define OMAP_INT_730_IH2_FIQ 0
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# define OMAP_INT_730_IH2_IRQ 1
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# define OMAP_INT_730_USB_NON_ISO 2
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# define OMAP_INT_730_USB_ISO 3
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# define OMAP_INT_730_ICR 4
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# define OMAP_INT_730_EAC 5
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# define OMAP_INT_730_GPIO_BANK1 6
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# define OMAP_INT_730_GPIO_BANK2 7
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# define OMAP_INT_730_GPIO_BANK3 8
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# define OMAP_INT_730_McBSP2TX 10
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# define OMAP_INT_730_McBSP2RX 11
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# define OMAP_INT_730_McBSP2RX_OVF 12
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# define OMAP_INT_730_LCD_LINE 14
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# define OMAP_INT_730_GSM_PROTECT 15
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# define OMAP_INT_730_TIMER3 16
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# define OMAP_INT_730_GPIO_BANK5 17
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# define OMAP_INT_730_GPIO_BANK6 18
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# define OMAP_INT_730_SPGIO_WR 29
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* Common IRQ numbers for level 2 interrupt handler
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# define OMAP_INT_KEYBOARD 1
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# define OMAP_INT_uWireTX 2
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# define OMAP_INT_uWireRX 3
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# define OMAP_INT_I2C 4
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# define OMAP_INT_MPUIO 5
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# define OMAP_INT_USB_HHC_1 6
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# define OMAP_INT_McBSP3TX 10
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# define OMAP_INT_McBSP3RX 11
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# define OMAP_INT_McBSP1TX 12
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# define OMAP_INT_McBSP1RX 13
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# define OMAP_INT_UART1 14
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# define OMAP_INT_UART2 15
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# define OMAP_INT_USB_W2FC 20
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# define OMAP_INT_1WIRE 21
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# define OMAP_INT_OS_TIMER 22
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# define OMAP_INT_OQN 23
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# define OMAP_INT_GAUGE_32K 24
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# define OMAP_INT_RTC_TIMER 25
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# define OMAP_INT_RTC_ALARM 26
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# define OMAP_INT_DSP_MMU 28
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* OMAP-1510 specific IRQ numbers for level 2 interrupt handler
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# define OMAP_INT_1510_BT_MCSI1TX 16
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# define OMAP_INT_1510_BT_MCSI1RX 17
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# define OMAP_INT_1510_SoSSI_MATCH 19
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# define OMAP_INT_1510_MEM_STICK 27
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# define OMAP_INT_1510_COM_SPI_RO 31
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* OMAP-310 specific IRQ numbers for level 2 interrupt handler
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# define OMAP_INT_310_FAC 0
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# define OMAP_INT_310_USB_HHC_2 7
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# define OMAP_INT_310_MCSI1_FE 16
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# define OMAP_INT_310_MCSI2_FE 17
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# define OMAP_INT_310_USB_W2FC_ISO 29
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# define OMAP_INT_310_USB_W2FC_NON_ISO 30
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# define OMAP_INT_310_McBSP2RX_OF 31
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* OMAP-1610 specific IRQ numbers for level 2 interrupt handler
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# define OMAP_INT_1610_FAC 0
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# define OMAP_INT_1610_USB_HHC_2 7
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# define OMAP_INT_1610_USB_OTG 8
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# define OMAP_INT_1610_SoSSI 9
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# define OMAP_INT_1610_BT_MCSI1TX 16
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# define OMAP_INT_1610_BT_MCSI1RX 17
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# define OMAP_INT_1610_SoSSI_MATCH 19
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# define OMAP_INT_1610_MEM_STICK 27
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# define OMAP_INT_1610_McBSP2RX_OF 31
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# define OMAP_INT_1610_STI 32
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# define OMAP_INT_1610_STI_WAKEUP 33
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# define OMAP_INT_1610_GPTIMER3 34
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# define OMAP_INT_1610_GPTIMER4 35
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# define OMAP_INT_1610_GPTIMER5 36
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# define OMAP_INT_1610_GPTIMER6 37
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# define OMAP_INT_1610_GPTIMER7 38
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# define OMAP_INT_1610_GPTIMER8 39
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# define OMAP_INT_1610_GPIO_BANK2 40
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# define OMAP_INT_1610_GPIO_BANK3 41
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# define OMAP_INT_1610_MMC2 42
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# define OMAP_INT_1610_CF 43
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# define OMAP_INT_1610_WAKE_UP_REQ 46
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# define OMAP_INT_1610_GPIO_BANK4 48
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# define OMAP_INT_1610_SPI 49
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# define OMAP_INT_1610_DMA_CH6 53
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# define OMAP_INT_1610_DMA_CH7 54
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# define OMAP_INT_1610_DMA_CH8 55
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# define OMAP_INT_1610_DMA_CH9 56
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# define OMAP_INT_1610_DMA_CH10 57
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# define OMAP_INT_1610_DMA_CH11 58
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# define OMAP_INT_1610_DMA_CH12 59
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# define OMAP_INT_1610_DMA_CH13 60
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# define OMAP_INT_1610_DMA_CH14 61
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# define OMAP_INT_1610_DMA_CH15 62
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# define OMAP_INT_1610_NAND 63
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* OMAP-730 specific IRQ numbers for level 2 interrupt handler
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# define OMAP_INT_730_HW_ERRORS 0
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# define OMAP_INT_730_NFIQ_PWR_FAIL 1
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# define OMAP_INT_730_CFCD 2
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# define OMAP_INT_730_CFIREQ 3
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# define OMAP_INT_730_I2C 4
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# define OMAP_INT_730_PCC 5
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# define OMAP_INT_730_MPU_EXT_NIRQ 6
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# define OMAP_INT_730_SPI_100K_1 7
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# define OMAP_INT_730_SYREN_SPI 8
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# define OMAP_INT_730_VLYNQ 9
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# define OMAP_INT_730_GPIO_BANK4 10
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# define OMAP_INT_730_McBSP1TX 11
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# define OMAP_INT_730_McBSP1RX 12
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# define OMAP_INT_730_McBSP1RX_OF 13
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# define OMAP_INT_730_UART_MODEM_IRDA_2 14
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# define OMAP_INT_730_UART_MODEM_1 15
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# define OMAP_INT_730_MCSI 16
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# define OMAP_INT_730_uWireTX 17
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# define OMAP_INT_730_uWireRX 18
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# define OMAP_INT_730_SMC_CD 19
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# define OMAP_INT_730_SMC_IREQ 20
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# define OMAP_INT_730_HDQ_1WIRE 21
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# define OMAP_INT_730_TIMER32K 22
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# define OMAP_INT_730_MMC_SDIO 23
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# define OMAP_INT_730_UPLD 24
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# define OMAP_INT_730_USB_HHC_1 27
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# define OMAP_INT_730_USB_HHC_2 28
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# define OMAP_INT_730_USB_GENI 29
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# define OMAP_INT_730_USB_OTG 30
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# define OMAP_INT_730_CAMERA_IF 31
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# define OMAP_INT_730_RNG 32
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# define OMAP_INT_730_DUAL_MODE_TIMER 33
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# define OMAP_INT_730_DBB_RF_EN 34
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# define OMAP_INT_730_MPUIO_KEYPAD 35
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# define OMAP_INT_730_SHA1_MD5 36
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# define OMAP_INT_730_SPI_100K_2 37
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# define OMAP_INT_730_RNG_IDLE 38
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# define OMAP_INT_730_MPUIO 39
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# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
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# define OMAP_INT_730_LLPC_OE_FALLING 41
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# define OMAP_INT_730_LLPC_OE_RISING 42
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# define OMAP_INT_730_LLPC_VSYNC 43
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# define OMAP_INT_730_WAKE_UP_REQ 46
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# define OMAP_INT_730_DMA_CH6 53
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# define OMAP_INT_730_DMA_CH7 54
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# define OMAP_INT_730_DMA_CH8 55
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# define OMAP_INT_730_DMA_CH9 56
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# define OMAP_INT_730_DMA_CH10 57
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# define OMAP_INT_730_DMA_CH11 58
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# define OMAP_INT_730_DMA_CH12 59
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# define OMAP_INT_730_DMA_CH13 60
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# define OMAP_INT_730_DMA_CH14 61
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# define OMAP_INT_730_DMA_CH15 62
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# define OMAP_INT_730_NAND 63
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* OMAP-24xx common IRQ numbers
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# define OMAP_INT_24XX_STI 4
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# define OMAP_INT_24XX_SYS_NIRQ 7
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# define OMAP_INT_24XX_L3_IRQ 10
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# define OMAP_INT_24XX_PRCM_MPU_IRQ 11
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# define OMAP_INT_24XX_SDMA_IRQ0 12
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# define OMAP_INT_24XX_SDMA_IRQ1 13
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# define OMAP_INT_24XX_SDMA_IRQ2 14
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# define OMAP_INT_24XX_SDMA_IRQ3 15
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# define OMAP_INT_243X_MCBSP2_IRQ 16
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# define OMAP_INT_243X_MCBSP3_IRQ 17
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# define OMAP_INT_243X_MCBSP4_IRQ 18
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# define OMAP_INT_243X_MCBSP5_IRQ 19
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# define OMAP_INT_24XX_GPMC_IRQ 20
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# define OMAP_INT_24XX_GUFFAW_IRQ 21
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# define OMAP_INT_24XX_IVA_IRQ 22
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# define OMAP_INT_24XX_EAC_IRQ 23
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# define OMAP_INT_24XX_CAM_IRQ 24
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# define OMAP_INT_24XX_DSS_IRQ 25
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# define OMAP_INT_24XX_MAIL_U0_MPU 26
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# define OMAP_INT_24XX_DSP_UMA 27
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# define OMAP_INT_24XX_DSP_MMU 28
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# define OMAP_INT_24XX_GPIO_BANK1 29
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# define OMAP_INT_24XX_GPIO_BANK2 30
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# define OMAP_INT_24XX_GPIO_BANK3 31
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# define OMAP_INT_24XX_GPIO_BANK4 32
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# define OMAP_INT_243X_GPIO_BANK5 33
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# define OMAP_INT_24XX_MAIL_U3_MPU 34
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# define OMAP_INT_24XX_WDT3 35
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# define OMAP_INT_24XX_WDT4 36
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# define OMAP_INT_24XX_GPTIMER1 37
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# define OMAP_INT_24XX_GPTIMER2 38
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# define OMAP_INT_24XX_GPTIMER3 39
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# define OMAP_INT_24XX_GPTIMER4 40
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# define OMAP_INT_24XX_GPTIMER5 41
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# define OMAP_INT_24XX_GPTIMER6 42
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# define OMAP_INT_24XX_GPTIMER7 43
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# define OMAP_INT_24XX_GPTIMER8 44
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# define OMAP_INT_24XX_GPTIMER9 45
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# define OMAP_INT_24XX_GPTIMER10 46
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# define OMAP_INT_24XX_GPTIMER11 47
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# define OMAP_INT_24XX_GPTIMER12 48
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# define OMAP_INT_24XX_PKA_IRQ 50
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# define OMAP_INT_24XX_SHA1MD5_IRQ 51
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# define OMAP_INT_24XX_RNG_IRQ 52
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# define OMAP_INT_24XX_MG_IRQ 53
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# define OMAP_INT_24XX_I2C1_IRQ 56
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# define OMAP_INT_24XX_I2C2_IRQ 57
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# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
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# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
426
# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
427
# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
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# define OMAP_INT_243X_MCBSP1_IRQ 64
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# define OMAP_INT_24XX_MCSPI1_IRQ 65
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# define OMAP_INT_24XX_MCSPI2_IRQ 66
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# define OMAP_INT_24XX_SSI1_IRQ0 67
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# define OMAP_INT_24XX_SSI1_IRQ1 68
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# define OMAP_INT_24XX_SSI2_IRQ0 69
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# define OMAP_INT_24XX_SSI2_IRQ1 70
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# define OMAP_INT_24XX_SSI_GDD_IRQ 71
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# define OMAP_INT_24XX_UART1_IRQ 72
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# define OMAP_INT_24XX_UART2_IRQ 73
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# define OMAP_INT_24XX_UART3_IRQ 74
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# define OMAP_INT_24XX_USB_IRQ_GEN 75
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# define OMAP_INT_24XX_USB_IRQ_NISO 76
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# define OMAP_INT_24XX_USB_IRQ_ISO 77
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# define OMAP_INT_24XX_USB_IRQ_HGEN 78
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# define OMAP_INT_24XX_USB_IRQ_HSOF 79
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# define OMAP_INT_24XX_USB_IRQ_OTG 80
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# define OMAP_INT_24XX_VLYNQ_IRQ 81
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# define OMAP_INT_24XX_MMC_IRQ 83
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# define OMAP_INT_24XX_MS_IRQ 84
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# define OMAP_INT_24XX_FAC_IRQ 85
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# define OMAP_INT_24XX_MCSPI3_IRQ 91
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# define OMAP_INT_243X_HS_USB_MC 92
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# define OMAP_INT_243X_HS_USB_DMA 93
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# define OMAP_INT_243X_CARKIT 94
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# define OMAP_INT_34XX_GPTIMER12 95
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* OMAP-3XXX common IRQ numbers
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#define OMAP_INT_3XXX_EMUINT 0 /* MPU emulation */
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#define OMAP_INT_3XXX_COMMTX 1 /* MPU emulation */
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#define OMAP_INT_3XXX_COMMRX 2 /* MPU emulation */
461
#define OMAP_INT_3XXX_BENCH 3 /* MPU emulation */
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#define OMAP_INT_3XXX_MCBSP2_ST_IRQ 4 /* Sidetone MCBSP2 overflow */
463
#define OMAP_INT_3XXX_MCBSP3_ST_IRQ 5 /* Sidetone MCBSP3 overflow */
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#define OMAP_INT_3XXX_SSM_ABORT_IRQ 6
465
#define OMAP_INT_3XXX_SYS_NIRQ 7 /* External source (active low) */
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#define OMAP_INT_3XXX_D2D_FW_IRQ 8
467
#define OMAP_INT_3XXX_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
468
#define OMAP_INT_3XXX_SMX_APP_IRQ 10 /* L3 interconnect error for application */
469
#define OMAP_INT_3XXX_PRCM_MPU_IRQ 11 /* PRCM module IRQ */
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#define OMAP_INT_3XXX_SDMA_IRQ0 12 /* System DMA request 0 */
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#define OMAP_INT_3XXX_SDMA_IRQ1 13 /* System DMA request 1 */
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#define OMAP_INT_3XXX_SDMA_IRQ2 14 /* System DMA request 2 */
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#define OMAP_INT_3XXX_SDMA_IRQ3 15 /* System DMA request 3 */
474
#define OMAP_INT_3XXX_MCBSP1_IRQ 16 /* MCBSP module 1 IRQ */
475
#define OMAP_INT_3XXX_MCBSP2_IRQ 17 /* MCBSP module 2 IRQ */
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#define OMAP_INT_3XXX_SR1_IRQ 18 /* SmartReflex 1 */
477
#define OMAP_INT_3XXX_SR2_IRQ 19 /* SmartReflex 2 */
478
#define OMAP_INT_3XXX_GPMC_IRQ 20 /* General-purpose memory controller module */
479
#define OMAP_INT_3XXX_SGX_IRQ 21 /* 2D/3D graphics module */
480
#define OMAP_INT_3XXX_MCBSP3_IRQ 22 /* MCBSP module 3 */
481
#define OMAP_INT_3XXX_MCBSP4_IRQ 23 /* MCBSP module 4 */
482
#define OMAP_INT_3XXX_CAM_IRQ0 24 /* Camera interface request 0 */
483
#define OMAP_INT_3XXX_DSS_IRQ 25 /* Display subsystem module */
484
#define OMAP_INT_3XXX_MAIL_U0_MPU 26 /* Mailbox user 0 request */
485
#define OMAP_INT_3XXX_MCBSP5_IRQ 27 /* MCBSP module 5 */
486
#define OMAP_INT_3XXX_IVA2_MMU_IRQ 28 /* IVA2 MMU */
487
#define OMAP_INT_3XXX_GPIO1_MPU_IRQ 29 /* GPIO module 1 */
488
#define OMAP_INT_3XXX_GPIO2_MPU_IRQ 30 /* GPIO module 2 */
489
#define OMAP_INT_3XXX_GPIO3_MPU_IRQ 31 /* GPIO module 3 */
490
#define OMAP_INT_3XXX_GPIO4_MPU_IRQ 32 /* GPIO module 4 */
491
#define OMAP_INT_3XXX_GPIO5_MPU_IRQ 33 /* GPIO module 5 */
492
#define OMAP_INT_3XXX_GPIO6_MPU_IRQ 34 /* GPIO module 6 */
493
#define OMAP_INT_3XXX_USIM_IRQ 35
494
#define OMAP_INT_3XXX_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
495
#define OMAP_INT_3XXX_GPT1_IRQ 37 /* General-purpose timer module 1 */
496
#define OMAP_INT_3XXX_GPT2_IRQ 38 /* General-purpose timer module 2 */
497
#define OMAP_INT_3XXX_GPT3_IRQ 39 /* General-purpose timer module 3 */
498
#define OMAP_INT_3XXX_GPT4_IRQ 40 /* General-purpose timer module 4 */
499
#define OMAP_INT_3XXX_GPT5_IRQ 41 /* General-purpose timer module 5 */
500
#define OMAP_INT_3XXX_GPT6_IRQ 42 /* General-purpose timer module 6 */
501
#define OMAP_INT_3XXX_GPT7_IRQ 43 /* General-purpose timer module 7 */
502
#define OMAP_INT_3XXX_GPT8_IRQ 44 /* General-purpose timer module 8 */
503
#define OMAP_INT_3XXX_GPT9_IRQ 45 /* General-purpose timer module 9 */
504
#define OMAP_INT_3XXX_GPT10_IRQ 46 /* General-purpose timer module 10 */
505
#define OMAP_INT_3XXX_GPT11_IRQ 47 /* General-purpose timer module 11 */
506
#define OMAP_INT_3XXX_MCSPI4_IRQ 48 /* MCSPI module 4 */
507
#define OMAP_INT_3XXX_SHA1MD52_IRQ 49
508
#define OMAP_INT_3XXX_FPKA_READY 50
509
#define OMAP_INT_3XXX_SHA1MD51_IRQ 51
510
#define OMAP_INT_3XXX_RNG_IRQ 52
511
#define OMAP_INT_3XXX_MG_IRQ 53
512
#define OMAP_INT_3XXX_MCBSP4_IRQ_TX 54 /* MCBSP module 4 transmit */
513
#define OMAP_INT_3XXX_MCBSP4_IRQ_RX 55 /* MCBSP module 4 receive */
514
#define OMAP_INT_3XXX_I2C1_IRQ 56 /* I2C module 1 */
515
#define OMAP_INT_3XXX_I2C2_IRQ 57 /* I2C module 2 */
516
#define OMAP_INT_3XXX_HDQ_IRQ 58 /* HDQ/1-Wire */
517
#define OMAP_INT_3XXX_MCBSP1_IRQ_TX 59 /* MCBSP module 1 transmit */
518
#define OMAP_INT_3XXX_MCBSP1_IRQ_RX 60 /* MCBSP module 1 receive */
519
#define OMAP_INT_3XXX_I2C3_IRQ 61 /* I2C module 3 */
520
#define OMAP_INT_3XXX_MCBSP2_IRQ_TX 62 /* MCBSP module 2 transmit */
521
#define OMAP_INT_3XXX_MCBSP2_IRQ_RX 63 /* MCBSP module 2 receive */
522
#define OMAP_INT_3XXX_FPKA_ERROR 64
523
#define OMAP_INT_3XXX_MCSPI1_IRQ 65 /* MCSPI module 1 */
524
#define OMAP_INT_3XXX_MCSPI2_IRQ 66 /* MCSPI module 2 */
525
/* IRQ67 is reserved */
526
/* IRQ68 is reserved */
527
/* IRQ69 is reserved */
528
/* IRQ70 is reserved */
529
/* IRQ71 is reserved */
530
#define OMAP_INT_3XXX_UART1_IRQ 72 /* UART module 1 */
531
#define OMAP_INT_3XXX_UART2_IRQ 73 /* UART module 2 */
532
#define OMAP_INT_3XXX_UART3_IRQ 74 /* UART module 3 (also infrared)*/
533
#define OMAP_INT_3XXX_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite1 and 2 */
534
#define OMAP_INT_3XXX_OHCI_IRQ 76 /* OHCI controller HSUSB MP Host interrupt */
535
#define OMAP_INT_3XXX_EHCI_IRQ 77 /* EHCI controller HSUSB MP Host interrupt */
536
#define OMAP_INT_3XXX_TLL_IRQ 78 /* HSUSB MP TLL interrupt */
537
/* IRQ79 is reserved */
538
#define OMAP_INT_3XXX_UART4_IRQ 80 /* UART module 4 (OMAP3630 only) */
539
#define OMAP_INT_3XXX_MCBSP5_IRQ_TX 81 /* MCBSP module 5 transmit */
540
#define OMAP_INT_3XXX_MCBSP5_IRQ_RX 82 /* MCBSP module 5 receive */
541
#define OMAP_INT_3XXX_MMC1_IRQ 83 /* MMC/SD module 1 */
542
#define OMAP_INT_3XXX_MS_IRQ 84
543
/* IRQ85 is reserved */
544
#define OMAP_INT_3XXX_MMC2_IRQ 86 /* MMC/SD module 2 */
545
#define OMAP_INT_3XXX_MPU_ICR_IRQ 87 /* MPU ICR */
546
#define OMAP_INT_3XXX_D2DFRINT 88 /* 3G coprocessor */
547
#define OMAP_INT_3XXX_MCBSP3_IRQ_TX 89 /* MCBSP module 3 transmit */
548
#define OMAP_INT_3XXX_MCBSP3_IRQ_RX 90 /* MCBSP module 3 receive */
549
#define OMAP_INT_3XXX_MCSPI3_IRQ 91 /* MCSPI module 3 */
550
#define OMAP_INT_3XXX_HSUSB_MC 92 /* High-Speed USB OTG controller */
551
#define OMAP_INT_3XXX_HSUSB_DMA 93 /* High-Speed USB OTG DMA controller */
552
#define OMAP_INT_3XXX_MMC3_IRQ 94 /* MMC/SD module 3 */
553
#define OMAP_INT_3XXX_GPT12_IRQ 95 /* General-purpose timer module 12 */
556
enum omap_dma_model {
564
struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
565
MemoryRegion *sysmem,
566
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
567
enum omap_dma_model model);
568
struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
569
MemoryRegion *sysmem,
570
struct omap_mpu_state_s *mpu, int fifo,
571
int chans, omap_clk iclk, omap_clk fclk);
572
struct soc_dma_s *omap3_dma4_init(struct omap_target_agent_s *ta,
573
struct omap_mpu_state_s *mpu,
574
qemu_irq *irqs, int chans,
575
omap_clk iclk, omap_clk fclk);
576
void omap_dma_reset(struct soc_dma_s *s);
583
/* Only used in OMAP DMA 3.x gigacells */
587
imif, /* omap16xx: ocp_t1 */
589
local, /* omap16xx: ocp_t2 */
591
__omap_dma_port_last,
599
} omap_dma_addressing_t;
601
/* Only used in OMAP DMA 3.x gigacells */
602
struct omap_dma_lcd_channel_s {
603
enum omap_dma_port src;
605
hwaddr src_f1_bottom;
607
hwaddr src_f2_bottom;
609
/* Used in OMAP DMA 3.2 gigacell */
610
unsigned char brust_f1;
611
unsigned char pack_f1;
612
unsigned char data_type_f1;
613
unsigned char brust_f2;
614
unsigned char pack_f2;
615
unsigned char data_type_f2;
616
unsigned char end_prog;
617
unsigned char repeat;
618
unsigned char auto_init;
619
unsigned char priority;
621
unsigned char running;
623
unsigned char omap_3_1_compatible_disable;
625
unsigned char lch_type;
626
int16_t element_index_f1;
627
int16_t element_index_f2;
628
int32_t frame_index_f1;
629
int32_t frame_index_f2;
630
uint16_t elements_f1;
632
uint16_t elements_f2;
634
omap_dma_addressing_t mode_f1;
635
omap_dma_addressing_t mode_f2;
637
/* Destination port is fixed. */
643
hwaddr phys_framebuffer[2];
645
struct omap_mpu_state_s *mpu;
646
} *omap_dma_get_lcdch(struct soc_dma_s *s);
649
* DMA request numbers for OMAP1
650
* See /usr/include/asm-arm/arch-omap/dma.h in Linux.
652
# define OMAP_DMA_NO_DEVICE 0
653
# define OMAP_DMA_MCSI1_TX 1
654
# define OMAP_DMA_MCSI1_RX 2
655
# define OMAP_DMA_I2C_RX 3
656
# define OMAP_DMA_I2C_TX 4
657
# define OMAP_DMA_EXT_NDMA_REQ0 5
658
# define OMAP_DMA_EXT_NDMA_REQ1 6
659
# define OMAP_DMA_UWIRE_TX 7
660
# define OMAP_DMA_MCBSP1_TX 8
661
# define OMAP_DMA_MCBSP1_RX 9
662
# define OMAP_DMA_MCBSP3_TX 10
663
# define OMAP_DMA_MCBSP3_RX 11
664
# define OMAP_DMA_UART1_TX 12
665
# define OMAP_DMA_UART1_RX 13
666
# define OMAP_DMA_UART2_TX 14
667
# define OMAP_DMA_UART2_RX 15
668
# define OMAP_DMA_MCBSP2_TX 16
669
# define OMAP_DMA_MCBSP2_RX 17
670
# define OMAP_DMA_UART3_TX 18
671
# define OMAP_DMA_UART3_RX 19
672
# define OMAP_DMA_CAMERA_IF_RX 20
673
# define OMAP_DMA_MMC_TX 21
674
# define OMAP_DMA_MMC_RX 22
675
# define OMAP_DMA_NAND 23 /* Not in OMAP310 */
676
# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
677
# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
678
# define OMAP_DMA_USB_W2FC_RX0 26
679
# define OMAP_DMA_USB_W2FC_RX1 27
680
# define OMAP_DMA_USB_W2FC_RX2 28
681
# define OMAP_DMA_USB_W2FC_TX0 29
682
# define OMAP_DMA_USB_W2FC_TX1 30
683
# define OMAP_DMA_USB_W2FC_TX2 31
685
/* These are only for 1610 */
686
# define OMAP_DMA_CRYPTO_DES_IN 32
687
# define OMAP_DMA_SPI_TX 33
688
# define OMAP_DMA_SPI_RX 34
689
# define OMAP_DMA_CRYPTO_HASH 35
690
# define OMAP_DMA_CCP_ATTN 36
691
# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
692
# define OMAP_DMA_CMT_APE_TX_CHAN_0 38
693
# define OMAP_DMA_CMT_APE_RV_CHAN_0 39
694
# define OMAP_DMA_CMT_APE_TX_CHAN_1 40
695
# define OMAP_DMA_CMT_APE_RV_CHAN_1 41
696
# define OMAP_DMA_CMT_APE_TX_CHAN_2 42
697
# define OMAP_DMA_CMT_APE_RV_CHAN_2 43
698
# define OMAP_DMA_CMT_APE_TX_CHAN_3 44
699
# define OMAP_DMA_CMT_APE_RV_CHAN_3 45
700
# define OMAP_DMA_CMT_APE_TX_CHAN_4 46
701
# define OMAP_DMA_CMT_APE_RV_CHAN_4 47
702
# define OMAP_DMA_CMT_APE_TX_CHAN_5 48
703
# define OMAP_DMA_CMT_APE_RV_CHAN_5 49
704
# define OMAP_DMA_CMT_APE_TX_CHAN_6 50
705
# define OMAP_DMA_CMT_APE_RV_CHAN_6 51
706
# define OMAP_DMA_CMT_APE_TX_CHAN_7 52
707
# define OMAP_DMA_CMT_APE_RV_CHAN_7 53
708
# define OMAP_DMA_MMC2_TX 54
709
# define OMAP_DMA_MMC2_RX 55
710
# define OMAP_DMA_CRYPTO_DES_OUT 56
713
* DMA request numbers for the OMAP2
715
# define OMAP24XX_DMA_NO_DEVICE 0
716
# define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
717
# define OMAP24XX_DMA_EXT_DMAREQ0 2
718
# define OMAP24XX_DMA_EXT_DMAREQ1 3
719
# define OMAP24XX_DMA_GPMC 4
720
# define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
721
# define OMAP24XX_DMA_DSS 6
722
# define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
723
# define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
724
# define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
725
# define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
726
# define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
727
# define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
728
# define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
729
# define OMAP24XX_DMA_EXT_DMAREQ2 14
730
# define OMAP24XX_DMA_EXT_DMAREQ3 15
731
# define OMAP24XX_DMA_EXT_DMAREQ4 16
732
# define OMAP24XX_DMA_EAC_AC_RD 17
733
# define OMAP24XX_DMA_EAC_AC_WR 18
734
# define OMAP24XX_DMA_EAC_MD_UL_RD 19
735
# define OMAP24XX_DMA_EAC_MD_UL_WR 20
736
# define OMAP24XX_DMA_EAC_MD_DL_RD 21
737
# define OMAP24XX_DMA_EAC_MD_DL_WR 22
738
# define OMAP24XX_DMA_EAC_BT_UL_RD 23
739
# define OMAP24XX_DMA_EAC_BT_UL_WR 24
740
# define OMAP24XX_DMA_EAC_BT_DL_RD 25
741
# define OMAP24XX_DMA_EAC_BT_DL_WR 26
742
# define OMAP24XX_DMA_I2C1_TX 27
743
# define OMAP24XX_DMA_I2C1_RX 28
744
# define OMAP24XX_DMA_I2C2_TX 29
745
# define OMAP24XX_DMA_I2C2_RX 30
746
# define OMAP24XX_DMA_MCBSP1_TX 31
747
# define OMAP24XX_DMA_MCBSP1_RX 32
748
# define OMAP24XX_DMA_MCBSP2_TX 33
749
# define OMAP24XX_DMA_MCBSP2_RX 34
750
# define OMAP24XX_DMA_SPI1_TX0 35
751
# define OMAP24XX_DMA_SPI1_RX0 36
752
# define OMAP24XX_DMA_SPI1_TX1 37
753
# define OMAP24XX_DMA_SPI1_RX1 38
754
# define OMAP24XX_DMA_SPI1_TX2 39
755
# define OMAP24XX_DMA_SPI1_RX2 40
756
# define OMAP24XX_DMA_SPI1_TX3 41
757
# define OMAP24XX_DMA_SPI1_RX3 42
758
# define OMAP24XX_DMA_SPI2_TX0 43
759
# define OMAP24XX_DMA_SPI2_RX0 44
760
# define OMAP24XX_DMA_SPI2_TX1 45
761
# define OMAP24XX_DMA_SPI2_RX1 46
763
# define OMAP24XX_DMA_UART1_TX 49
764
# define OMAP24XX_DMA_UART1_RX 50
765
# define OMAP24XX_DMA_UART2_TX 51
766
# define OMAP24XX_DMA_UART2_RX 52
767
# define OMAP24XX_DMA_UART3_TX 53
768
# define OMAP24XX_DMA_UART3_RX 54
769
# define OMAP24XX_DMA_USB_W2FC_TX0 55
770
# define OMAP24XX_DMA_USB_W2FC_RX0 56
771
# define OMAP24XX_DMA_USB_W2FC_TX1 57
772
# define OMAP24XX_DMA_USB_W2FC_RX1 58
773
# define OMAP24XX_DMA_USB_W2FC_TX2 59
774
# define OMAP24XX_DMA_USB_W2FC_RX2 60
775
# define OMAP24XX_DMA_MMC1_TX 61
776
# define OMAP24XX_DMA_MMC1_RX 62
777
# define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
778
# define OMAP24XX_DMA_EXT_DMAREQ5 64
781
* DMA request numbers for the OMAP3
782
* Note that the numbers have to match the values that are
783
* written to CCRi SYNCHRO_CONTROL bits, i.e. actual line
784
* number plus one! Zero is a reserved value (defined as
785
* NO_DEVICE here). Other missing values are reserved.
787
#define OMAP3XXX_DMA_NO_DEVICE 0
789
#define OMAP3XXX_DMA_EXT_DMAREQ0 2
790
#define OMAP3XXX_DMA_EXT_DMAREQ1 3
791
#define OMAP3XXX_DMA_GPMC 4
793
#define OMAP3XXX_DMA_DSS_LINETRIGGER 6
794
#define OMAP3XXX_DMA_EXT_DMAREQ2 7
796
#define OMAP3XXX_DMA_SPI3_TX0 15
797
#define OMAP3XXX_DMA_SPI3_RX0 16
798
#define OMAP3XXX_DMA_MCBSP3_TX 17
799
#define OMAP3XXX_DMA_MCBSP3_RX 18
800
#define OMAP3XXX_DMA_MCBSP4_TX 19
801
#define OMAP3XXX_DMA_MCBSP4_RX 20
802
#define OMAP3XXX_DMA_MCBSP5_TX 21
803
#define OMAP3XXX_DMA_MCBSP5_RX 22
804
#define OMAP3XXX_DMA_SPI3_TX1 23
805
#define OMAP3XXX_DMA_SPI3_RX1 24
806
#define OMAP3XXX_DMA_I2C3_TX 25
807
#define OMAP3XXX_DMA_I2C3_RX 26
808
#define OMAP3XXX_DMA_I2C1_TX 27
809
#define OMAP3XXX_DMA_I2C1_RX 28
810
#define OMAP3XXX_DMA_I2C2_TX 29
811
#define OMAP3XXX_DMA_I2C2_RX 30
812
#define OMAP3XXX_DMA_MCBSP1_TX 31
813
#define OMAP3XXX_DMA_MCBSP1_RX 32
814
#define OMAP3XXX_DMA_MCBSP2_TX 33
815
#define OMAP3XXX_DMA_MCBSP2_RX 34
816
#define OMAP3XXX_DMA_SPI1_TX0 35
817
#define OMAP3XXX_DMA_SPI1_RX0 36
818
#define OMAP3XXX_DMA_SPI1_TX1 37
819
#define OMAP3XXX_DMA_SPI1_RX1 38
820
#define OMAP3XXX_DMA_SPI1_TX2 39
821
#define OMAP3XXX_DMA_SPI1_RX2 40
822
#define OMAP3XXX_DMA_SPI1_TX3 41
823
#define OMAP3XXX_DMA_SPI1_RX3 42
824
#define OMAP3XXX_DMA_SPI2_TX0 43
825
#define OMAP3XXX_DMA_SPI2_RX0 44
826
#define OMAP3XXX_DMA_SPI2_TX1 45
827
#define OMAP3XXX_DMA_SPI2_RX1 46
828
#define OMAP3XXX_DMA_MMC2_TX 47
829
#define OMAP3XXX_DMA_MMC2_RX 48
830
#define OMAP3XXX_DMA_UART1_TX 49
831
#define OMAP3XXX_DMA_UART1_RX 50
832
#define OMAP3XXX_DMA_UART2_TX 51
833
#define OMAP3XXX_DMA_UART2_RX 52
834
#define OMAP3XXX_DMA_UART3_TX 53
835
#define OMAP3XXX_DMA_UART3_RX 54
837
#define OMAP3XXX_DMA_MMC1_TX 61
838
#define OMAP3XXX_DMA_MMC1_RX 62
839
#define OMAP3XXX_DMA_MS 63
840
#define OMAP3XXX_DMA_EXT_DMAREQ3 64
841
#define OMAP3XXX_DMA_AES2_TX 65
842
#define OMAP3XXX_DMA_AES2_RX 66
843
#define OMAP3XXX_DMA_DES2_TX 67
844
#define OMAP3XXX_DMA_DES2_RX 68
845
#define OMAP3XXX_DMA_SHA1MD5_RX 69
846
#define OMAP3XXX_DMA_SPI4_TX0 70
847
#define OMAP3XXX_DMA_SPI4_RX0 71
848
#define OMAP3XXX_DMA_DSS0 72
849
#define OMAP3XXX_DMA_DSS1 73
850
#define OMAP3XXX_DMA_DSS2 74
851
#define OMAP3XXX_DMA_DSS3 75
853
#define OMAP3XXX_DMA_MMC3_TX 77
854
#define OMAP3XXX_DMA_MMC3_RX 78
855
#define OMAP3XXX_DMA_USIM_TX 79
856
#define OMAP3XXX_DMA_USIM_RX 80
857
#define OMAP3XXX_DMA_UART4_TX 81
858
#define OMAP3XXX_DMA_UART4_RX 82
862
struct omap_gp_timer_s;
863
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
864
qemu_irq irq, omap_clk fclk, omap_clk iclk);
865
void omap_gp_timer_reset(struct omap_gp_timer_s *s);
866
void omap_gp_timer_change_clk(struct omap_gp_timer_s *timer);
868
/* OMAP2 sysctimer */
869
struct omap_synctimer_s;
870
struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
871
struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
872
void omap_synctimer_reset(struct omap_synctimer_s *s);
874
void omap_uart_attach(DeviceState *qdev, CharDriverState *chr,
878
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
879
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
880
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
883
uint16_t (*receive)(void *opaque);
884
void (*send)(void *opaque, uint16_t data);
888
void omap_uwire_attach(struct omap_uwire_s *s,
889
uWireSlave *slave, int chipselect);
892
SPIBus *omap_mcspi_bus(DeviceState *omap_mcspi, int bus_number);
897
/* The CPU can call this if it is generating the clock signal on the
898
* i2s port. The CODEC can ignore it if it is set up as a clock
899
* master and generates its own clock. */
900
void (*set_rate)(void *opaque, int in, int out);
902
void (*tx_swallow)(void *opaque);
919
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
921
void omap_tap_init(struct omap_target_agent_s *ta,
922
struct omap_mpu_state_s *mpu);
925
struct omap_lcd_panel_s;
926
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
927
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
930
struct omap_dma_lcd_channel_s *dma,
936
void (*write)(void *opaque, int dc, uint16_t value);
937
void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
938
uint16_t (*read)(void *opaque, int dc);
941
void omap_dss_reset(struct omap_dss_s *s);
942
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
943
MemoryRegion *sysmem,
945
qemu_irq irq, qemu_irq drq,
946
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
947
omap_clk ick1, omap_clk ick2);
948
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
952
struct omap_mmc_s *omap_mmc_init(hwaddr base,
953
MemoryRegion *sysmem,
954
BlockDriverState *bd,
955
qemu_irq irq, qemu_irq dma[], omap_clk clk);
956
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
957
BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
958
omap_clk fclk, omap_clk iclk);
959
void omap_mmc_reset(struct omap_mmc_s *s);
960
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
961
void omap_mmc_enable(struct omap_mmc_s *s, int enable);
964
i2c_bus *omap_i2c_bus(DeviceState *omap_i2c);
966
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
967
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
968
# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
969
# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
970
# define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
971
# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
972
# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
973
# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
974
# define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630)
976
# define cpu_is_omap15xx(cpu) \
977
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
978
# define cpu_is_omap16xx(cpu) \
979
(cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
980
# define cpu_is_omap24xx(cpu) \
981
(cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
983
# define cpu_class_omap1(cpu) \
984
(cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
985
# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
986
# define cpu_class_omap3(cpu) \
987
(cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
989
struct omap_mpu_state_s {
990
enum omap_mpu_model {
1010
MemoryRegion ulpd_pm_iomem;
1011
MemoryRegion pin_cfg_iomem;
1012
MemoryRegion id_iomem;
1013
MemoryRegion id_iomem_e18;
1014
MemoryRegion id_iomem_ed4;
1015
MemoryRegion id_iomem_e20;
1016
MemoryRegion mpui_iomem;
1017
MemoryRegion tcmi_iomem;
1018
MemoryRegion clkm_iomem;
1019
MemoryRegion clkdsp_iomem;
1020
MemoryRegion mpui_io_iomem;
1021
MemoryRegion tap_iomem;
1022
MemoryRegion imif_ram;
1023
MemoryRegion emiff_ram;
1027
struct omap_dma_port_if_s {
1028
uint32_t (*read[3])(struct omap_mpu_state_s *s,
1030
void (*write[3])(struct omap_mpu_state_s *s,
1031
hwaddr offset, uint32_t value);
1032
int (*addr_valid)(struct omap_mpu_state_s *s,
1034
} port[__omap_dma_port_last];
1036
unsigned long sdram_size;
1037
unsigned long sram_size;
1039
/* MPUI-TIPB peripherals */
1040
DeviceState *uart[4];
1044
struct omap_mcbsp_s *mcbsp1;
1045
struct omap_mcbsp_s *mcbsp3;
1047
/* MPU public TIPB peripherals */
1048
struct omap_32khz_timer_s *os_timer;
1050
struct omap_mmc_s *mmc;
1052
struct omap_mpuio_s *mpuio;
1054
struct omap_uwire_s *microwire;
1056
struct omap_pwl_s *pwl;
1057
struct omap_pwt_s *pwt;
1058
DeviceState *i2c[2];
1060
struct omap_rtc_s *rtc;
1062
struct omap_mcbsp_s *mcbsp2;
1064
struct omap_lpg_s *led[2];
1066
/* MPU private TIPB peripherals */
1069
struct soc_dma_s *dma;
1071
struct omap_mpu_timer_s *timer[3];
1072
struct omap_watchdog_timer_s *wdt;
1074
struct omap_lcd_panel_s *lcd;
1076
uint32_t ulpd_pm_regs[21];
1077
int64_t ulpd_gauge_start;
1079
uint32_t func_mux_ctrl[14];
1080
uint32_t comp_mode_ctrl[1];
1081
uint32_t pull_dwn_ctrl[4];
1082
uint32_t gate_inh_ctrl[1];
1083
uint32_t voltage_ctrl[1];
1084
uint32_t test_dbg_ctrl[1];
1085
uint32_t mod_conf_ctrl[1];
1090
struct omap_tipb_bridge_s *private_tipb;
1091
struct omap_tipb_bridge_s *public_tipb;
1093
uint32_t tcmi_regs[17];
1095
struct dpll_ctl_s *dpll[3];
1100
int clocking_scheme;
1102
uint16_t arm_idlect1;
1103
uint16_t arm_idlect2;
1104
uint16_t arm_ewupct;
1105
uint16_t arm_rstct1;
1106
uint16_t arm_rstct2;
1107
uint16_t arm_ckout1;
1109
uint16_t dsp_idlect1;
1110
uint16_t dsp_idlect2;
1111
uint16_t dsp_rstct2;
1114
/* OMAP2-only peripherals */
1115
struct omap_l4_s *l4;
1117
struct omap_gp_timer_s *gptimer[12];
1118
struct omap_synctimer_s *synctimer;
1120
struct omap_prcm_s *prcm;
1121
struct omap_sdrc_s *sdrc;
1122
struct omap_gpmc_s *gpmc;
1123
struct omap_sysctl_s *sysc;
1127
struct omap_dss_s *dss;
1129
struct omap_eac_s *eac;
1133
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
1134
unsigned long sdram_size,
1138
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
1139
unsigned long sdram_size,
1142
#define OMAP_FMT_plx "%#08" HWADDR_PRIx
1144
uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
1145
void omap_badwidth_write8(void *opaque, hwaddr addr,
1147
uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
1148
void omap_badwidth_write16(void *opaque, hwaddr addr,
1150
uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
1151
void omap_badwidth_write32(void *opaque, hwaddr addr,
1154
void omap_mpu_wakeup(void *opaque, int irq, int req);
1156
# define OMAP_BAD_REG(paddr) \
1157
fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
1158
__FUNCTION__, paddr)
1159
# define OMAP_RO_REG(paddr) \
1160
fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1161
__FUNCTION__, paddr)
1163
/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1164
(Board-specifc tags are not here) */
1165
#define OMAP_TAG_CLOCK 0x4f01
1166
#define OMAP_TAG_MMC 0x4f02
1167
#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1168
#define OMAP_TAG_USB 0x4f04
1169
#define OMAP_TAG_LCD 0x4f05
1170
#define OMAP_TAG_GPIO_SWITCH 0x4f06
1171
#define OMAP_TAG_UART 0x4f07
1172
#define OMAP_TAG_FBMEM 0x4f08
1173
#define OMAP_TAG_STI_CONSOLE 0x4f09
1174
#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1175
#define OMAP_TAG_PARTITION 0x4f0b
1176
#define OMAP_TAG_TEA5761 0x4f10
1177
#define OMAP_TAG_TMP105 0x4f11
1178
#define OMAP_TAG_BOOT_REASON 0x4f80
1179
#define OMAP_TAG_FLASH_PART_STR 0x4f81
1180
#define OMAP_TAG_VERSION_STR 0x4f82
1183
OMAP_GPIOSW_TYPE_COVER = 0 << 4,
1184
OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1185
OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
1188
#define OMAP_GPIOSW_INVERTED 0x0001
1189
#define OMAP_GPIOSW_OUTPUT 0x0002
1191
# define TCMI_VERBOSE 1
1193
# ifdef TCMI_VERBOSE
1194
# define OMAP_8B_REG(paddr) \
1195
fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1196
__FUNCTION__, paddr)
1197
# define OMAP_16B_REG(paddr) \
1198
fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1199
__FUNCTION__, paddr)
1200
# define OMAP_32B_REG(paddr) \
1201
fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1202
__FUNCTION__, paddr)
1204
# define OMAP_8B_REG(paddr)
1205
# define OMAP_16B_REG(paddr)
1206
# define OMAP_32B_REG(paddr)
1209
# define OMAP_MPUI_REG_MASK 0x000007ff
1211
#endif /* hw_omap_h */