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From 2ae8fac7f11fcd4d410bfb9308d353bc37cbee16 Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Mon, 18 Feb 2013 16:58:30 +0000
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Subject: [PATCH 42/70] add hw/omap3_boot.c file
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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omap3 bootrom emulation
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small changes in boot rom code
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- update comments and include a note for r12=1 smc call
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- leave the cpu in SYS mode when jumping to bootloader code
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Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
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Changes by: Loïc Minier <loic.minier@linaro.org>
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Fix use of p after free() in omap3_mmc_fat_boot()
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Fix logic test to use && in omap3_mmc_fat_boot
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Changes by: Peter Maydell <peter.maydell@linaro.org>
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Remove code which was erroneously overriding the detection of a CHSETUP
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header in an OMAP boot image loaded from an MMC card.
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Fix raw mode boot (try sectors 0 and 256, use right offsets)
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- do not map boot rom at address zero
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- make use of the arm cp15 vector base address register
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- run boot rom emulation from omap3 instead of board
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Changes by: Peter Chubb <peter.chubb@nicta.com.au>
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- bugfixes to make FAT12/FAT16 work
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hw/misc/Makefile.objs | 1 +
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hw/misc/omap3_boot.c | 959 ++++++++++++++++++++++++++++++++++++++++++++++++++
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include/hw/arm/omap.h | 6 +
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3 files changed, 966 insertions(+)
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create mode 100644 hw/misc/omap3_boot.c
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diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
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index f674365..aee75c1 100644
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--- a/hw/misc/Makefile.objs
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+++ b/hw/misc/Makefile.objs
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@@ -38,6 +38,7 @@ obj-$(CONFIG_OMAP) += omap_gpmc.o
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obj-$(CONFIG_OMAP) += omap_l4.o
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obj-$(CONFIG_OMAP) += omap_sdrc.o
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obj-$(CONFIG_OMAP) += omap_tap.o
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+obj-$(CONFIG_OMAP) += omap3_boot.o
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obj-$(CONFIG_SLAVIO) += slavio_misc.o
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obj-$(CONFIG_ZYNQ) += zynq_slcr.o
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diff --git a/hw/misc/omap3_boot.c b/hw/misc/omap3_boot.c
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index 0000000..92d74c3
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+++ b/hw/misc/omap3_boot.c
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+ * TI OMAP3 boot ROM emulation. Based on information in the OMAP34xx 3.1
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+ * Technical Reference Manual from Texas Instruments.
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+ * Copyright (C) 2009 Nokia Corporation
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+ * The OMAP3 boot ROM service routines accessed via ARM SMC instruction
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+ * are not available in this emulation due to the limited availability
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+ * of public documentation on the ARM TrustZone functionality. However
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+ * it seems executing the SMC instruction as a NOP causes no harm.
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 or
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+ * (at your option) any later version of the License.
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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+#include "hw/arm/omap.h"
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+#include "sysemu/sysemu.h"
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+#include "sysemu/char.h"
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+#include "hw/block/flash.h"
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+#include "sysemu/blockdev.h"
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+#include "exec/address-spaces.h"
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+//#define OMAP3_BOOT_DEBUG
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+#ifdef OMAP3_BOOT_DEBUG
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+#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
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+ __LINE__, ##__VA_ARGS__);
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+/* list of supported NAND devices according to the OMAP34xx TRM */
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+static const struct {
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+ uint32_t capacity_Mb;
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+} omap3_boot_nand_devices[] = {
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+ {0xe6, 512, 64}, {0x33, 512, 128}, {0x73, 512, 128},
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+ {0x43, 512, 128}, {0x53, 512, 128}, {0x35, 512, 256},
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+ {0x75, 512, 256}, {0x45, 512, 256}, {0x55, 512, 256},
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+ {0x36, 512, 512}, {0x76, 512, 512}, {0x46, 512, 512},
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+ {0x56, 512, 512}, {0xa2, 2048, 512}, {0xf2, 2048, 512},
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+ {0xb2, 2048, 512}, {0xc2, 2048, 512}, {0x39, 512, 1024},
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+ {0x79, 512, 1024}, {0x49, 512, 1024}, {0x59, 512, 1024},
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+ {0x78, 512, 1024}, {0x72, 512, 1024}, {0x74, 512, 1024},
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+ {0xa1, 2048, 1024}, {0xf1, 2048, 1024}, {0xb1, 2048, 1024},
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+ {0xc1, 2048, 1024}, {0xaa, 2048, 2048}, {0xda, 2048, 2048},
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+ {0xba, 2048, 2048}, {0xca, 2048, 2048}, {0x71, 512, 2048},
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+ {0x51, 512, 2048}, {0x31, 512, 2048}, {0x41, 512, 2048},
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+ {0xac, 2048, 4096}, {0xdc, 2048, 4096}, {0xbc, 2048, 4096},
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+ {0xcc, 2048, 4096}, {0xa3, 2048, 8192}, {0xd3, 2048, 8192},
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+ {0xb3, 2048, 8192}, {0xc3, 2048, 8192}, {0xa5, 2048, 16384},
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+ {0xd5, 2048, 16384}, {0xb5, 2048, 16384}, {0xc5, 2048, 16384},
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+ {0xa7, 2048, 32768}, {0xb7, 2048, 32768}, {0xae, 2048, 65536},
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+ {0xbe, 2048, 65536},
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+struct omap3_nand_boot_desc_s {
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+ uint32_t capacity_Mb;
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+static const uint8_t omap3_boot_rom[] = { /* 0x40014000-0x4001bfff */
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+ /* 0x40014000: ROM Exception vectors */
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+ 0x3e, 0x00, 0x00, 0xea, /* b 0x40014100 */
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+ 0x18, 0xf0, 0x9f, 0xe5, /* ldr pc, [pc, #0x18] */
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+ 0x18, 0xf0, 0x9f, 0xe5, /* ldr pc, [pc, #0x18] */
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+ 0x18, 0xf0, 0x9f, 0xe5, /* ldr pc, [pc, #0x18] */
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+ 0x18, 0xf0, 0x9f, 0xe5, /* ldr pc, [pc, #0x18] */
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+ 0x18, 0xf0, 0x9f, 0xe5, /* ldr pc, [pc, #0x18] */
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+ 0x18, 0xf0, 0x9f, 0xe5, /* ldr pc, [pc, #0x18] */
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+ 0x18, 0xf0, 0x9f, 0xe5, /* ldr pc, [pc, #0x18] */
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+ /* 0x40014020: ROM CRC */
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+ 0xff, 0xff, 0xff, 0xff,
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+ /* 0x40014024: unused(?), we use it for some data */
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+ 0xc8, 0xff, 0x20, 0x40, /* 0x40014024: undef sram vector address */
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+ 0xcc, 0xff, 0x20, 0x40, /* 0x40014028: swi sram vector address */
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+ 0xd0, 0xff, 0x20, 0x40, /* 0x4001402c: pabt sram vector address */
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+ 0xd4, 0xff, 0x20, 0x40, /* 0x40014030: dabt sram vector address */
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+ 0xd8, 0xff, 0x20, 0x40, /* 0x40014034: unused sram vector address */
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+ 0xdc, 0xff, 0x20, 0x40, /* 0x40014038: irq sram vector address */
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+ 0xe0, 0xff, 0x20, 0x40, /* 0x4001403c: fiq sram vector address */
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+ 0xff, 0xff, 0xff, 0xff, /* 0x40014040: boot loader image start address */
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+ 0xff, 0xff, 0xff, 0xff, /* 0x40014044: booting parameter structure 0-3 */
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+ 0xff, 0xff, 0xff, 0xff, /* 0x40014048: booting parameter structure 4-7 */
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+ 0xff, 0xff, 0xff, 0xff, /* 0x4001404c: booting parameter structure 8-11 */
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+ 0x0e, 0xf0, 0xb0, 0xe1, /* 0x40014050: "movs pc, lr" */
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+ 0xff, 0xff, 0xff, 0xff, /* 0x40014054 */
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+ 0xff, 0xff, 0xff, 0xff, /* 0x40014058 */
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+ 0xff, 0xff, 0xff, 0xff, /* 0x4001405c */
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+ 0xfe, 0xff, 0xff, 0xea, /* 0x40014060: monitor vector 0 (unused) */
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+ 0xfe, 0xff, 0xff, 0xea, /* 0x40014064: monitor vector 1 (unused) */
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+ 0x15, 0x00, 0x00, 0xea, /* 0x40014068: monitor vector 2 (smc) */
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+ 0xfe, 0xff, 0xff, 0xea, /* 0x4001406c: monitor vector 3 (pabt) */
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+ 0xfe, 0xff, 0xff, 0xea, /* 0x40014070: monitor vector 4 (dabt) */
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+ 0xfe, 0xff, 0xff, 0xea, /* 0x40014074: monitor vector 5 (unused) */
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+ 0xfe, 0xff, 0xff, 0xea, /* 0x40014078: monitor vector 6 (irq) */
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+ 0xfe, 0xff, 0xff, 0xea, /* 0x4001407c: monitor vector 7 (fiq) */
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+ /* 0x40014080: Dead loops */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x40014080 @ undefined exception */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x40014084 @ swi exception */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x40014088 @ prefetch abort exception */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x4001408c @ data abort exception */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x40014090 @ unused exception */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x40014094 @ irq exception */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x40014098 @ fiq exception */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x4001409c @ validation tests pass */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140a0 @ validation tests fail */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140a4 @ boot failed: no more devices */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140a8 @ image not executed or returned */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140ac @ reserved */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140b0 @ reserved */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140b4 @ reserved */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140b8 @ reserved */
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+ 0xfe, 0xff, 0xff, 0xea, /* b 0x400140bc @ reserved */
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+ /* 0x400140c0: should perform a software reset & jump to r0 */
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+ 0x00, 0xf0, 0xa0, 0xe1, /* mov pc, r0 */
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+ /* 0x400140c4: monitor mode smc vector handler */
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+ /* @ r12=1 is used to invalidate l2, we skip it */
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+ 0x02, 0x00, 0x5c, 0xe3, /* cmp r12, #2 @ write to l2 cache aux ctrl */
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+ 0x50, 0x0f, 0x29, 0xee, /* mcreq p15, 1, r0, c9, c0, 2 */
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+ 0x03, 0x00, 0x5c, 0xe3, /* cmp r12, #3 @ write to aux ctrl */
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+ 0x30, 0x0f, 0x01, 0xee, /* mcreq p15, 0, r0, c1, c0, 1 @ aux ctrl*/
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+ 0x0e, 0xf0, 0xb0, 0xe1, /* movs pc, r14 */
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ /* 0x40014100: code, ROM emulation uses this to launch the
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+ * boot loader after it has been read into memory */
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+ 0xc8, 0x10, 0x1f, 0xe5, /* ldr r1, [#0x40014040] @ boot loader start */
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+ 0xb0, 0x0c, 0x0f, 0xe3, /* movw r0, #0xfcb0 */
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+ 0x20, 0x00, 0x44, 0xe3, /* movt r0, #0x4020 @ stack top at 0x4020fcb0 */
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+ 0xdf, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdf @ enter SYS mode */
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+ 0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
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+ 0x80, 0x0c, 0x40, 0xe2, /* sub r0, r0, #32768 @ 32kB SYS/USR stack */
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+ 0xd1, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd1 @ enter FIQ mode */
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+ 0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
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+ 0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048 @ 2kB FIQ stack */
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+ 0xd2, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd2 @ enter IRQ mode */
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+ 0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
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+ 0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048 @ 2kB IRQ stack */
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+ 0xd7, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd7 @ enter ABT mode */
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+ 0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
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+ 0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048 @ 2kB ABT stack */
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+ 0xdb, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdb @ enter UND mode */
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+ 0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 */
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+ 0x08, 0x0c, 0x40, 0xe2, /* sub r0, r0, #2048 @ 2kB UND stack */
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+ 0xd3, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xd3 @ enter SVC mode */
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+ 0x00, 0xd0, 0xa0, 0xe1, /* mov sp, r0 @ 23kB left for SVC stack */
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+ 0xdf, 0xf0, 0x21, 0xe3, /* msr cpsr_c, #0xdf @ enter SYS mode */
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+ 0x40, 0x04, 0xa0, 0xe3, /* mov r0, #0x40000000 @ r0 -> vba */
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+ 0x05, 0x09, 0x80, 0xe2, /* add r0, r0, #0x14000 */
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+ 0x10, 0x0f, 0x0c, 0xfe, /* mcr2 p15, 0, r0, c12, c0, 0 */
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+ 0x60, 0x00, 0x80, 0xe2, /* add r0, r0, #0x60 @ r0 -> monitor vba */
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+ 0x30, 0x0f, 0x0c, 0xfe, /* mcr2 p15, 0, r0, c12, c0, 1 */
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+ 0x1c, 0x00, 0x40, 0xe2, /* sub r0, r0, #1c @ r0 -> booting parameter struct */
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+ 0x01, 0xf0, 0xa0, 0xe1, /* mov pc, r1 */
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+/* SRAM exception vectors, to be placed at 0x4020ffc8 */
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+static const uint8_t omap3_sram_vectors[] = {
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+ 0x14, 0xf0, 0x9f, 0xe5, /* ldr pc, [#0x4020ffe4] @ undefined */
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+ 0x14, 0xf0, 0x9f, 0xe5, /* ldr pc, [#0x4020ffe8] @ swi */
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+ 0x14, 0xf0, 0x9f, 0xe5, /* ldr pc, [#0x4020ffec] @ prefetch abort */
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+ 0x14, 0xf0, 0x9f, 0xe5, /* ldr pc, [#0x4020fff0] @ data abort */
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+ 0x14, 0xf0, 0x9f, 0xe5, /* ldr pc, [#0x4020fff4] @ unused */
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+ 0x14, 0xf0, 0x9f, 0xe5, /* ldr pc, [#0x4020fff8] @ irq */
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+ 0x14, 0xf0, 0x9f, 0xe5, /* ldr pc, [#0x4020fffc] @ fiq */
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+ 0x80, 0x40, 0x01, 0x00, /* 0x14080 */
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+ 0x50, 0x40, 0x01, 0x40, /* 0x40014050 (default is 0x14084) */
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+ 0x88, 0x40, 0x01, 0x00, /* 0x14088 */
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+ 0x8c, 0x40, 0x01, 0x00, /* 0x1408c */
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+ 0x90, 0x40, 0x01, 0x00, /* 0x14090 */
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+ 0x94, 0x40, 0x01, 0x00, /* 0x14094 */
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+ 0x98, 0x40, 0x01, 0x00, /* 0x14098 */
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+static inline uint32_t omap3_get_le32(const void *p)
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+ const uint8_t *q = (const uint8_t *)p;
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+ v |= q[2]; v <<= 8;
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+ v |= q[1]; v <<= 8;
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+static inline uint32_t omap3_get_le16(const void *p)
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+ const uint8_t *q = (const uint8_t *)p;
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+static inline void omap3_boot_setlsb(hwaddr addr, uint16_t lsb)
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+ cpu_physical_memory_read(addr, x, 4);
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+ x[1] = (lsb >> 8) & 0xff;
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+ cpu_physical_memory_write(addr, x, 4);
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+} omap3_boot_device_t;
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+struct omap3_boot_s {
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+ struct omap_mpu_state_s *mpu;
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+ omap3_boot_device_t devicetype;
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+static struct omap3_boot_s *omap3_boot_init(struct omap_mpu_state_s *mpu,
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+ omap3_boot_device_t dtype,
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+ const uint8_t *data,
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+ struct omap3_boot_s *s = g_malloc0(sizeof(struct omap3_boot_s));
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+ s->devicetype = dtype;
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+ if (data_len >= 512) {
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+ if (!strncasecmp((char *)(data + 0x14), "chsettings", 10)
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+ || !strncasecmp((char *)(data + 0x14), "chram", 5)
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+ || !strncasecmp((char *)(data + 0x14), "chflash", 7)
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+ || !strncasecmp((char *)(data + 0x14), "chmmcsd", 7))
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+ s->state = confighdr;
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+static void omap3_boot_chsettings(struct omap3_boot_s *boot,
329
+ const uint8_t *chtoc)
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+ if (omap3_get_le32(chtoc) != 0xc0c0c0c1) {
334
+ TRACE("invalid section verification key");
337
+ if (!chtoc[4]) { /* section disabled? */
340
+ if (omap3_get_le16(chtoc + 5) != 0x0001) {
341
+ TRACE("unsupported CH version (0x%04x)", omap3_get_le16(chtoc));
344
+ boot->chflags |= 0x01;
345
+ flags = omap3_get_le32(chtoc + 8);
348
+ cpu_physical_memory_write(0x48307270, chtoc + 0x00, 4); /* PRM_CLKSRC_CTRL */
349
+ cpu_physical_memory_write(0x48306d40, chtoc + 0x04, 4); /* PRM_CLKSEL */
350
+ cpu_physical_memory_write(0x48005140, chtoc + 0x08, 4); /* CM_CLKSEL1_EMU */
351
+ if (flags & (1 << 2)) { /* clock configuration */
352
+ cpu_physical_memory_write(0x48004a40, chtoc + 0x0c, 4); /* CM_CLKSEL_CORE */
353
+ cpu_physical_memory_write(0x48004c40, chtoc + 0x10, 4); /* CM_CLKSEL_WKUP */
355
+ if (flags & (1 << 5)) { /* DPLL3 CORE */
356
+ if (flags & (1 << 8)) { /* enable DPLL3 bypass */
357
+ cpu_physical_memory_read(0x48004d00, (uint8_t *)&x, 4);
358
+ x &= ~7; x |= 5; /* set DPLL3 bypass */
359
+ cpu_physical_memory_write(0x48004d00, (uint8_t *)&x, 4);
361
+ cpu_physical_memory_write(0x48004d00, chtoc + 0x14, 4); /* CM_CLKEN_PLL */
362
+ cpu_physical_memory_write(0x48004d30, chtoc + 0x18, 4); /* CM_AUTOIDLE_PLL */
363
+ cpu_physical_memory_write(0x48004d40, chtoc + 0x1c, 4); /* CM_CLKSEL1_PLL */
365
+ if (flags & (1 << 3)) { /* DPLL4 PER */
366
+ if (flags & (1 << 6)) { /* enable DPLL4 bypass */
367
+ cpu_physical_memory_read(0x48004d00, (uint8_t *)&x, 4);
368
+ x &= ~0x70000; x |= 0x10000; /* set DPLL4 in stop mode */
369
+ cpu_physical_memory_write(0x48004d00, (uint8_t *)&x, 4);
371
+ cpu_physical_memory_write(0x48004d00, chtoc + 0x20, 4); /* CM_CLKEN_PLL */
372
+ cpu_physical_memory_write(0x48004d30, chtoc + 0x24, 4); /* CM_AUTOIDLE_PLL */
373
+ cpu_physical_memory_write(0x48004d44, chtoc + 0x28, 4); /* CM_CLKSEL2_PLL */
374
+ cpu_physical_memory_write(0x48004d48, chtoc + 0x2c, 4); /* CM_CLKSEL3_PLL */
376
+ if (flags & (1 << 3)) { /* DPLL1 MPU */
377
+ if (flags & (1 << 7)) { /* enable DPLL1 bypass */
378
+ cpu_physical_memory_read(0x48004904, (uint8_t *)&x, 4);
379
+ x &= ~7; x |= 5; /* set DPLL1 bypass */
380
+ cpu_physical_memory_write(0x48004904, (uint8_t *)&x, 4);
382
+ cpu_physical_memory_write(0x48004904, chtoc + 0x30, 4); /* CM_CLKEN_PLL_MPU */
383
+ cpu_physical_memory_write(0x48004934, chtoc + 0x34, 4); /* CM_AUTOIDLE_PLL_MPU */
384
+ cpu_physical_memory_write(0x48004940, chtoc + 0x38, 4); /* CM_CLKSEL1_PLL_MPU */
385
+ cpu_physical_memory_write(0x48004944, chtoc + 0x3c, 4); /* CM_CLKSEL2_PLL_MPU */
386
+ cpu_physical_memory_write(0x48004948, chtoc + 0x40, 4); /* CM_CLKSTCTRL_MPU */
388
+ switch ((flags >> 24) & 0xff) {
389
+ case 0x01: x = 0; break; /* 12MHz */
390
+ case 0x02: x = 1; break; /* 13MHz */
391
+ case 0x03: x = 5; break; /* 16.8MHz */
392
+ case 0x04: x = 2; break; /* 19.2MHz */
393
+ case 0x05: x = 3; break; /* 26MHz */
394
+ case 0x06: x = 4; break; /* 38.4MHz */
396
+ TRACE("unsupported SYS.CLK setting (0x%02x)", (flags >> 24) & 0xff);
400
+ if (x != omap3_get_le32(chtoc + 0x04)) {
401
+ TRACE("mismatch in SYS.CLK id and PRM_CLKSEL value");
406
+static void omap3_boot_chram(struct omap3_boot_s *boot,
407
+ const uint8_t *chtoc)
409
+ if (omap3_get_le32(chtoc) != 0xc0c0c0c2) {
410
+ TRACE("invalid section verification key");
413
+ if (!chtoc[4]) { /* section disabled? */
416
+ boot->chflags |= 0x02;
417
+ omap3_boot_setlsb(0x6d000040, omap3_get_le16(chtoc + 0x0a)); /* SDRC_CS_CFG */
418
+ omap3_boot_setlsb(0x6d000044, omap3_get_le16(chtoc + 0x0c)); /* SDRC_SHARING */
419
+ cpu_physical_memory_write(0x6d000060, chtoc + 0x10, 4); /* SDRC_DLLA_CTRL */
421
+ cpu_physical_memory_write(0x6d000080, chtoc + 0x20, 4); /* SDRC_MCFG_0 */
422
+ omap3_boot_setlsb(0x6d000084, omap3_get_le16(chtoc + 0x24)); /* SDRC_MR_0 */
423
+ omap3_boot_setlsb(0x6d000088, omap3_get_le16(chtoc + 0x26)); /* SDRC_EMR1_0? */
424
+ omap3_boot_setlsb(0x6d00008c, omap3_get_le16(chtoc + 0x28)); /* SDRC_EMR2_0 */
425
+ omap3_boot_setlsb(0x6d000090, omap3_get_le16(chtoc + 0x2a)); /* SDRC_EMR3_0? */
426
+ cpu_physical_memory_write(0x6d00009c, chtoc + 0x2c, 4); /* SDRC_ACTIM_CTRLA_0 */
427
+ cpu_physical_memory_write(0x6d0000a0, chtoc + 0x30, 4); /* SDRC_ACTIM_CTRLB_0 */
428
+ cpu_physical_memory_write(0x6d0000a4, chtoc + 0x34, 4); /* SDRC_RFR_CTRL_0 */
430
+ cpu_physical_memory_write(0x6d0000b0, chtoc + 0x20, 4); /* SDRC_MCFG_1 */
431
+ omap3_boot_setlsb(0x6d0000b4, omap3_get_le16(chtoc + 0x24)); /* SDRC_MR_1 */
432
+ omap3_boot_setlsb(0x6d0000b8, omap3_get_le16(chtoc + 0x26)); /* SDRC_EMR1_1? */
433
+ omap3_boot_setlsb(0x6d0000bc, omap3_get_le16(chtoc + 0x28)); /* SDRC_EMR2_1 */
434
+ omap3_boot_setlsb(0x6d0000c0, omap3_get_le16(chtoc + 0x2a)); /* SDRC_EMR3_1? */
435
+ cpu_physical_memory_write(0x6d0000cc, chtoc + 0x2c, 4); /* SDRC_ACTIM_CTRLA_1 */
436
+ cpu_physical_memory_write(0x6d0000d0, chtoc + 0x30, 4); /* SDRC_ACTIM_CTRLB_1 */
437
+ cpu_physical_memory_write(0x6d0000d4, chtoc + 0x34, 4); /* SDRC_RFR_CTRL_1 */
440
+static void omap3_boot_chflash(struct omap3_boot_s *boot,
441
+ const uint8_t *chtoc)
443
+ if (omap3_get_le32(chtoc) != 0xc0c0c0c3) {
444
+ TRACE("invalid section verification key");
447
+ if (!chtoc[4]) { /* section disabled? */
450
+ boot->chflags |= 0x04;
451
+ omap3_boot_setlsb(0x6e000010, omap3_get_le16(chtoc + 0x08)); /* GPMC_SYSCONFIG */
452
+ omap3_boot_setlsb(0x6e00001c, omap3_get_le16(chtoc + 0x0a)); /* GPMC_IRQENABLE */
453
+ omap3_boot_setlsb(0x6e000040, omap3_get_le16(chtoc + 0x0c)); /* GPMC_TIMEOUT_CONTROL */
454
+ omap3_boot_setlsb(0x6e000050, omap3_get_le16(chtoc + 0x0e)); /* GPMC_CONFIG */
455
+ cpu_physical_memory_write(0x6e000060, chtoc + 0x10, 4); /* GPMC_CONFIG1_0 */
456
+ cpu_physical_memory_write(0x6e000064, chtoc + 0x14, 4); /* GPMC_CONFIG2_0 */
457
+ cpu_physical_memory_write(0x6e000068, chtoc + 0x18, 4); /* GPMC_CONFIG3_0 */
458
+ cpu_physical_memory_write(0x6e00006c, chtoc + 0x1c, 4); /* GPMC_CONFIG4_0 */
459
+ cpu_physical_memory_write(0x6e000070, chtoc + 0x20, 4); /* GPMC_CONFIG5_0 */
460
+ cpu_physical_memory_write(0x6e000074, chtoc + 0x24, 4); /* GPMC_CONFIG6_0 */
461
+ cpu_physical_memory_write(0x6e000078, chtoc + 0x28, 4); /* GPMC_CONFIG7_0 */
462
+ cpu_physical_memory_write(0x6e0001e0, chtoc + 0x2c, 4); /* GPMC_PREFETCH_CONFIG1 */
463
+ omap3_boot_setlsb(0x6e0001e4, omap3_get_le16(chtoc + 0x30)); /* GPMC_PREFETCH_CONFIG2 */
464
+ omap3_boot_setlsb(0x6e0001ec, omap3_get_le16(chtoc + 0x32)); /* GPMC_PREFETCH_CONTROL */
465
+ /* TODO: ECC config registers. The TRM spec is not clear on these */
468
+static void omap3_boot_chmmcsd(struct omap3_boot_s *boot,
469
+ const uint8_t *chtoc)
471
+ if (omap3_get_le32(chtoc) != 0xc0c0c0c4) {
472
+ TRACE("invalid section verification key");
475
+ if (!chtoc[4]) { /* section disabled? */
478
+ boot->chflags |= 0x08;
479
+ /* TODO: MMCHS registers */
482
+/* returns non-zero if more blocks are needed */
483
+static uint32_t omap3_boot_block(const uint8_t *data,
485
+ struct omap3_boot_s *s)
487
+ const uint8_t *p = 0;
490
+ switch (s->state) {
493
+ for (p = data; i >= 32 && omap3_get_le32(p) != 0xffffffff; p += 32, i -= 32) {
494
+ if (!strcasecmp((char *)(p + 0x14), "chsettings"))
495
+ omap3_boot_chsettings(s, p + omap3_get_le32(p));
496
+ else if (!strcasecmp((char *)(p + 0x14), "chram"))
497
+ omap3_boot_chram(s, p + omap3_get_le32(p));
498
+ else if (!strcasecmp((char *)(p + 0x14), "chflash"))
499
+ omap3_boot_chflash(s, p + omap3_get_le32(p));
500
+ else if (!strcasecmp((char *)(p + 0x14), "chmmcsd"))
501
+ omap3_boot_chmmcsd(s, p + omap3_get_le32(p));
503
+ TRACE("unknown CHTOC item \"%s\"", (char *)(p + 0x14));
511
+ s->state = imagehdr;
518
+ s->count = omap3_get_le32(data);
519
+ s->addr = omap3_get_le32(data + 4);
520
+ if (!s->count || (s->count >> 24) || !s->addr || s->addr == 0xffffffff)
522
+ /* patch image start address in boot ROM */
523
+ cpu_physical_memory_write_rom(0x40014040, data + 4, 4);
524
+ /* start copying image */
530
+ i = (s->count >= data_len) ? data_len : s->count;
531
+ cpu_physical_memory_write(s->addr, data, i);
543
+/* returns non-zero if boot has finished succesfully */
544
+static int omap3_boot_finish(struct omap3_boot_s *s)
547
+ 0, 0, 0, 0, /* last received booting message */
548
+ (uint8_t)s->devicetype,
552
+ 0, 0, 0, 0 /* device descriptor */
554
+ int result = (s->state == done);
557
+ /* fill in the booting parameter structure */
558
+ cpu_physical_memory_write_rom(0x40014044, x, 12);
564
+/* returns ptr to matching dir entry / zero entry or 0 if unsuccessful */
565
+static const uint8_t *omap3_scan_fat_dir_sector(const uint8_t *s)
569
+ /* there are 0x10 items with 0x20 bytes per item */
570
+ for (i = 0x10; i--; s += 0x20) {
571
+ if (*s == 0xe5 || (s[0x0b] & 0x0f) == 0x0f) continue; /* erased/LFN */
572
+ if (!*s || !strncasecmp((void *)s, "mlo ", 8+3)) return s;
577
+struct omap3_fat_drv_s {
578
+ BlockDriverState *bs;
579
+ uint8_t ptype; /* 12, 16, 32 */
580
+ uint64_t c0; /* physical byte offset for data cluster 0 */
581
+ uint64_t fat; /* physical byte offset for used FAT sector 0 */
582
+ uint32_t spc; /* sectors per cluster */
585
+/* returns cluster data in the buffer and next cluster chain number
586
+ or 0 if unsuccessful */
587
+static uint32_t omap3_read_fat_cluster(uint8_t *data,
588
+ struct omap3_fat_drv_s *drv,
592
+ uint32_t len = drv->spc * 0x200; /* number of bytes to read */
594
+ switch (drv->ptype) { /* check for EOF */
595
+ case 12: if (cl > 0xff0) return 0; break;
596
+ case 16: if (cl > 0xfff0) return 0; break;
597
+ case 32: if (cl > 0x0ffffff0) return 0; break;
601
+ if (bdrv_pread(drv->bs,
602
+ drv->c0 + (cl - 2) * len,
606
+ switch (drv->ptype) { /* determine next cluster # */
608
+ hw_error("%s: FAT12 parsing not implemented!", __FUNCTION__);
611
+ return (bdrv_pread(drv->bs, drv->fat + cl * 2, buf, 2) != 2)
612
+ ? 0 : omap3_get_le16(buf);
614
+ return (bdrv_pread(drv->bs, drv->fat + cl * 4, buf, 4) != 4)
615
+ ? 0 : omap3_get_le32(buf) & 0x0fffffff;
622
+static int omap3_mmc_fat_boot(BlockDriverState *bs,
625
+ struct omap_mpu_state_s *mpu)
627
+ struct omap3_fat_drv_s drv;
628
+ struct omap3_boot_s *boot;
629
+ uint32_t i, j, cluster0, fatsize, bootsize, rootsize;
630
+ const uint8_t *p, *q;
634
+ /* determine FAT type */
637
+ fatsize = omap3_get_le16(sector + 0x16);
639
+ fatsize = omap3_get_le32(sector + 0x24);
640
+ bootsize = omap3_get_le16(sector + 0x0e);
641
+ cluster0 = bootsize + fatsize * sector[0x10];
642
+ rootsize = omap3_get_le16(sector + 0x11);
643
+ if (rootsize & 0x0f)
646
+ drv.spc = sector[0x0d];
647
+ i = omap3_get_le16(sector + 0x13);
649
+ i = omap3_get_le32(sector + 0x20);
650
+ i = (i - (cluster0 + rootsize)) / drv.spc;
651
+ drv.ptype = (i < 4085) ? 12 : (i < 65525) ? 16 : 32;
653
+ /* search for boot loader file */
655
+ drv.fat = (bootsize + pstart) * 0x200;
656
+ drv.c0 = (cluster0 + pstart) * 0x200;
657
+ if (drv.ptype == 32) {
658
+ i = omap3_get_le32(sector + 0x2c); /* first root cluster # */
659
+ j = omap3_get_le16(sector + 0x28);
661
+ drv.fat += (j & 0x0f) * fatsize * 0x200;
662
+ cluster = g_malloc0(drv.spc * 0x200);
663
+ for (p = 0; !p && (i = omap3_read_fat_cluster(cluster, &drv, i)); ) {
664
+ for (j = drv.spc, q=cluster; j-- && !p; q += 0x200)
665
+ p = omap3_scan_fat_dir_sector(q);
667
+ memcpy(sector, p, 0x200); /* save the sector */
668
+ /* allows referring to p after freeing cluster */
673
+ } else { /* FAT12/16 */
675
+ * drv.c0 points to start of root directory
677
+ for (i = rootsize, j = 0, p = 0; i-- && !p; j++) {
678
+ if (bdrv_pread(drv.bs, drv.c0 + j * 0x200, sector, 0x200) != 0x200)
680
+ p = omap3_scan_fat_dir_sector(sector);
683
+ * Adjust start of clusters to point after the root directory.
685
+ drv.c0 += 0x200 * rootsize;
688
+ if (p && *p) { /* did we indeed find the file? */
690
+ * FAT16 Spec says to ignore bytes at offset 0x14 (the FAT32
691
+ * high-order cylinder number bytes); but the omap3 bootrom
692
+ * seems always to use them.
694
+ i = omap3_get_le16(p + 0x14);
696
+ i |= omap3_get_le16(p + 0x1a);
697
+ j = drv.spc * 0x200;
698
+ uint8 *data = g_malloc0(j);
699
+ if ((i = omap3_read_fat_cluster(data, &drv, i))) {
700
+ boot = omap3_boot_init(mpu, mmc1, data, j);
701
+ while (omap3_boot_block(data, j, boot))
702
+ i = omap3_read_fat_cluster(data, &drv, i);
703
+ result = omap3_boot_finish(boot);
705
+ TRACE("unable to read MLO file contents from SD card");
709
+ TRACE("MLO file not found in the root directory");
714
+static int omap3_mmc_raw_boot(BlockDriverState *bs,
716
+ struct omap_mpu_state_s *mpu)
718
+ struct omap3_boot_s *boot;
721
+ /* We try to load an image from sectors 0 and 256 */
722
+ uint32_t boot_sectors[] = { 0, 256 };
725
+ for (idx = 0; !result && idx < ARRAY_SIZE(boot_sectors); idx++) {
726
+ i = boot_sectors[idx];
727
+ if (bdrv_pread(bs, i * 0x200, sector, 0x200) != 0x200) {
728
+ TRACE("error trying to read sector %u on boot device", i);
732
+ boot = omap3_boot_init(mpu, mmc1, sector, 0x200);
733
+ if (boot->state == confighdr) {
734
+ /* CH must be present for raw boot */
735
+ while (omap3_boot_block(sector, 0x200, boot)) {
737
+ if (bdrv_pread(bs, i * 0x200, sector, 0x200) != 0x200) {
738
+ TRACE("error trying to read sector %u on boot device", i);
744
+ result = (boot->state == done);
750
+/* returns non-zero if successful, zero if unsuccessful */
751
+static int omap3_mmc_boot(struct omap_mpu_state_s *s)
753
+ DriveInfo *di = drive_get(IF_SD, 0, 0);
754
+ uint8_t *sector, *p;
755
+ uint32_t pstart, i;
758
+ /* very simple implementation for GP device boot,
759
+ supports only two modes:
760
+ 1. MBR partition table with an active FAT partition
761
+ and boot loader file (MLO) in its root directory, or
762
+ 2. CH sector located on first sector, followed by boot loader image */
764
+ sector = g_malloc0(0x200);
765
+ if (bdrv_pread(di->bdrv, 0, sector, 0x200) == 0x200) {
766
+ for (i = 0, p = sector + 0x1be; i < 4; i++, p += 0x10)
767
+ if (p[0] == 0x80) break;
768
+ if (sector[0x1fe] == 0x55 && sector[0x1ff] == 0xaa /* signature */
769
+ && i < 4 /* active partition exists */
770
+ && (p[4] == 1 || p[4] == 4 || p[4] == 6 || p[4] == 11
771
+ || p[4] == 12 || p[4] == 14 || p[4] == 15) /* FAT */
772
+ && bdrv_pread(di->bdrv,
773
+ (pstart = omap3_get_le32(p + 8)) * 0x200,
774
+ sector, 0x200) == 0x200
775
+ && sector[0x1fe] == 0x55 && sector[0x1ff] == 0xaa)
776
+ result = omap3_mmc_fat_boot(di->bdrv, sector, pstart, s);
778
+ result = omap3_mmc_raw_boot(di->bdrv, sector, s);
785
+static inline void omap3_nand_sendcmd(struct omap3_nand_boot_desc_s *nd,
788
+ uint8_t x[2] = {cmd, 0};
789
+ cpu_physical_memory_write(0x6e00007c, x, nd->bus16 ? 2 : 1);
792
+static inline void omap3_nand_sendaddr_byte(struct omap3_nand_boot_desc_s *nd,
795
+ uint8_t x[2] = { a, 0 };
797
+ cpu_physical_memory_write(0x6e000080, x, nd->bus16 ? 2 : 1);
800
+static inline uint8_t omap3_nand_readbyte(struct omap3_nand_boot_desc_s *nd)
804
+ cpu_physical_memory_read(0x6e000084, x, nd->bus16 ? 2 : 1);
808
+static inline void omap3_nand_readpage(struct omap3_nand_boot_desc_s *nd,
814
+ omap3_nand_sendcmd(nd, 0x00); /* read page */
815
+ omap3_nand_sendaddr_byte(nd, 0x00);
816
+ if (nd->pagesize >= 2048) {
817
+ omap3_nand_sendaddr_byte(nd, 0x00);
818
+ omap3_nand_sendaddr_byte(nd, (uint8_t)(pageaddr & 0xff));
819
+ omap3_nand_sendaddr_byte(nd, (uint8_t)((pageaddr >> 8) & 0xff));
820
+ if (nd->capacity_Mb >= 2048)
821
+ omap3_nand_sendaddr_byte(nd, (uint8_t)((pageaddr >> 16) & 0xff));
822
+ omap3_nand_sendcmd(nd, 0x30); /* confirm read */
824
+ omap3_nand_sendaddr_byte(nd, (uint8_t)(pageaddr & 0xff));
825
+ omap3_nand_sendaddr_byte(nd, (uint8_t)((pageaddr >> 8) & 0xff));
828
+ for (i = nd->pagesize / 2; i--; data += 2)
829
+ cpu_physical_memory_read(0x6e000084, data, 2);
831
+ for (i = nd->pagesize; i--; data++)
832
+ cpu_physical_memory_read(0x6e000084, data, 1);
836
+/* returns non-zero if successful, zero if unsuccessful */
837
+static int omap3_nand_boot(struct omap_mpu_state_s *mpu, int bus16)
839
+ struct omap3_nand_boot_desc_s *nd;
840
+ struct omap3_boot_s *boot;
846
+ /* TODO: support bad block marks */
847
+ nd = g_malloc0(sizeof(struct omap3_nand_boot_desc_s));
849
+ omap3_nand_sendcmd(nd, 0xff); /* reset */
850
+ omap3_nand_sendcmd(nd, 0x90); /* read id */
851
+ omap3_nand_sendaddr_byte(nd, 0);
852
+ id[0] = omap3_nand_readbyte(nd); /* manufacturer id */
853
+ id[1] = omap3_nand_readbyte(nd); /* device id */
854
+ id[2] = omap3_nand_readbyte(nd); /* don't care */
855
+ id[3] = omap3_nand_readbyte(nd); /* attributes */
856
+ for (i = 0; omap3_boot_nand_devices[i].id; i++) {
857
+ if (omap3_boot_nand_devices[i].id == id[1]) {
858
+ nd->capacity_Mb = omap3_boot_nand_devices[i].capacity_Mb;
859
+ if (nd->capacity_Mb > 1024)
860
+ nd->pagesize = 1024 * (1 << (id[3] & 3));
862
+ nd->pagesize = omap3_boot_nand_devices[i].pagesize;
866
+ /* TODO: if device is not recognized at this state, we should
867
+ * issue READ ID2 command to the device and get device parameters
869
+ if (nd->pagesize) {
870
+ data = g_malloc0(nd->pagesize);
871
+ /* TODO: scan through 4 first blocks for image */
872
+ omap3_nand_readpage(nd, 0, data);
873
+ boot = omap3_boot_init(mpu, nand, data, nd->pagesize);
874
+ while (omap3_boot_block(data, nd->pagesize, boot))
875
+ omap3_nand_readpage(nd, ++page, data);
876
+ result = omap3_boot_finish(boot);
883
+static inline void omap3_onenand_writereg(uint16_t reg, uint16_t value)
885
+ cpu_to_le16s(&value);
886
+ cpu_physical_memory_write(0x08000000 + (reg << 1), (void *)&value, 2);
889
+static inline uint16_t omap3_onenand_readreg(uint16_t reg)
892
+ cpu_physical_memory_read(0x08000000 + (reg << 1), (void *)&value, 2);
893
+ return le16_to_cpu(value);
896
+static int omap3_onenand_readpage(uint16_t pagesize,
901
+ omap3_onenand_writereg(0xf100, b);
902
+ omap3_onenand_writereg(0xf107, (p & 0x3f) << 2);
903
+ omap3_onenand_writereg(0xf200, 0x0800);
904
+ omap3_onenand_writereg(0xf101, 0);
905
+ omap3_onenand_writereg(0xf241, 0);
906
+ omap3_onenand_writereg(0xf220, 0);
907
+ if (!(omap3_onenand_readreg(0xf241) & 0x8000) ||
908
+ (omap3_onenand_readreg(0xf240) & 0x0400))
910
+ cpu_physical_memory_read(0x08000400, (void *)d, pagesize);
914
+static int omap3_onenand_boot(struct omap_mpu_state_s *s)
917
+ uint16_t i, j, pagesize;
919
+ struct omap3_boot_s *boot;
922
+ /* reset device type at cs0: 16bit NOR, no wait monitoring */
923
+ stl_le_p(&x, 0x79001000);
924
+ cpu_physical_memory_write(0x6e000060, (void *)&x, 4); /* GPMC_CONFIG1_0 */
925
+ /* map cs0 at 0x08000000 */
926
+ stl_le_p(&x, 0x00000848);
927
+ cpu_physical_memory_write(0x6e000078, (void *)&x, 4); /* GPMC_CONFIG7_0 */
928
+ /* try to read onenand registers */
929
+ x = omap3_onenand_readreg(0xf000); /* manufacturer id */
930
+ if (!x || (x >> 8)) { /* we accept any non-zero 8bit id */
933
+ pagesize = omap3_onenand_readreg(0xf003);
934
+ if (pagesize != 2048 && pagesize != 1024) {
935
+ hw_error("%s: OneNAND page size %d not supported",
936
+ __FUNCTION__, pagesize);
939
+ /* search for boot loader */
940
+ page = g_malloc0(pagesize);
941
+ for (i = 0; i < 4; i++) { /* search 4 blocks */
942
+ if (omap3_onenand_readpage(pagesize, i, 0, page)) {
943
+ boot = omap3_boot_init(s, onenand, page, pagesize);
944
+ for (j = 1; omap3_boot_block(page, pagesize, boot); j++)
945
+ if (!omap3_onenand_readpage(pagesize, i, j, page))
947
+ result = omap3_boot_finish(boot);
956
+void omap3_boot_rom_init(struct omap_mpu_state_s *s)
958
+ const uint8_t rom_version[4] = { 0x00, 0x14, 0x00, 0x00 }; /* v. 14.00 */
960
+ if (!s->bootrom_initialized) {
961
+ s->bootrom_initialized = 1;
962
+ memory_region_init_ram(&s->bootrom, NULL, "omap3_boot_rom",
963
+ OMAP3XXX_BOOTROM_SIZE);
964
+ memory_region_set_readonly(&s->bootrom, true);
965
+ memory_region_add_subregion(get_system_memory(),
966
+ OMAP3_Q1_BASE + 0x14000,
968
+ cpu_physical_memory_write_rom(OMAP3_Q1_BASE + 0x14000,
970
+ sizeof(omap3_boot_rom));
971
+ cpu_physical_memory_write_rom(OMAP3_Q1_BASE + 0x1bffc,
973
+ sizeof(rom_version));
974
+ cpu_physical_memory_write(OMAP3_SRAM_BASE + 0xffc8,
975
+ omap3_sram_vectors,
976
+ sizeof(omap3_sram_vectors));
980
+void omap3_boot_rom_emu(struct omap_mpu_state_s *s)
982
+ uint8_t x[4] = {0, 0, 0, 0};
985
+ /* only emulate the boot rom if it was initialized earlier */
986
+ if (!s->bootrom_initialized) {
990
+ /* here we are relying on all memories to be attached and gpmc_attach
991
+ * to fill in DEVICETYPE field correctly for CS0 for us */
992
+ cpu_physical_memory_read(0x6e000060, x, 4); /* GPMC_CONFIG1_0 */
993
+ switch (((x[1] >> 2) & 3)) {
995
+ result = omap3_onenand_boot(s);
998
+ result = omap3_nand_boot(s, ((x[1] >> 4) & 3) == 1);
1004
+ /* if no boot loader found yet, try the MMC/SD card... */
1006
+ result = omap3_mmc_boot(s);
1008
+ /* move PC to the boot ROM reset vector */
1009
+ s->cpu->env.regs[15] = 0x40014000;
1011
+ if (!result) { /* no boot device found */
1012
+ /* move PC to the appropriate ROM dead loop address */
1013
+ s->cpu->env.regs[15] = 0x400140a4;
1014
+ /* ...on second thought, let's just call it a day and quit */
1015
+ hw_error("no boot device found");
1018
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
1019
index 9d0a0b7..30046d1 100644
1020
--- a/include/hw/arm/omap.h
1021
+++ b/include/hw/arm/omap.h
1022
@@ -1127,6 +1127,8 @@ struct omap_mpu_state_s {
1023
struct omap_dss_s *dss;
1025
struct omap_eac_s *eac;
1026
+ MemoryRegion bootrom;
1027
+ int bootrom_initialized;
1031
@@ -1139,6 +1141,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
1032
unsigned long sdram_size,
1036
+void omap3_boot_rom_init(struct omap_mpu_state_s *s);
1037
+void omap3_boot_rom_emu(struct omap_mpu_state_s *s);
1039
#define OMAP_FMT_plx "%#08" HWADDR_PRIx
1041
uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);