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Viewing changes to debian/patches/linaro/0011-hw-omap_clk.c-Add-OMAP3-clock-tree-definitions.patch

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-04 12:13:08 UTC
  • mfrom: (10.1.45 sid)
  • Revision ID: package-import@ubuntu.com-20140204121308-1xq92lrfs75agw2g
Tags: 1.7.0+dfsg-3ubuntu1~ppa1
* Merge 1.7.0+dfsg-3 from debian.  Remaining changes:
  - debian/patches/ubuntu:
    * expose-vmx_qemu64cpu.patch
    * linaro (omap3) and arm64 patches
    * ubuntu/target-ppc-add-stubs-for-kvm-breakpoints: fix FTBFS
      on ppc
    * ubuntu/CVE-2013-4377.patch: fix denial of service via virtio
  - debian/qemu-system-x86.modprobe: set kvm_intel nested=1 options
  - debian/control:
    * add arm64 to Architectures
    * add qemu-common and qemu-system-aarch64 packages
  - debian/qemu-system-common.install: add debian/tmp/usr/lib
  - debian/qemu-system-common.preinst: add kvm group
  - debian/qemu-system-common.postinst: remove acl placed by udev,
    and add udevadm trigger.
  - qemu-system-x86.links: add eepro100.rom, remove pxe-virtio,
    pxe-e1000 and pxe-rtl8139.
  - add qemu-system-x86.qemu-kvm.upstart and .default
  - qemu-user-static.postinst-in: remove arm64 binfmt
  - debian/rules:
    * allow parallel build
    * add aarch64 to system_targets and sys_systems
    * add qemu-kvm-spice links
    * install qemu-system-x86.modprobe
  - add debian/qemu-system-common.links for OVMF.fd link
* Remove kvm-img, kvm-nbd, kvm-ifup and kvm-ifdown symlinks.

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debian/patches/linaro/0011-hw-omap_clk.c-Add-OMAP3-clock-tree-definitions.patch
1
 
From ce6ac11c14ce9c3cf4ab9b299612ecc5044a2c47 Mon Sep 17 00:00:00 2001
2
 
From: =?UTF-8?q?Juha=20Riihim=C3=A4ki?= <juha.riihimaki@nokia.com>
3
 
Date: Mon, 18 Feb 2013 16:58:25 +0000
4
 
Subject: [PATCH 11/70] hw/omap_clk.c: Add OMAP3 clock tree definitions
5
 
MIME-Version: 1.0
6
 
Content-Type: text/plain; charset=UTF-8
7
 
Content-Transfer-Encoding: 8bit
8
 
 
9
 
Add the clock tree definitions for OMAP3 SOCs.
10
 
 
11
 
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
12
 
[Riku Voipio: Fixes and restructuring patchset]
13
 
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
14
 
[Peter Maydell: More fixes and cleanups for upstream submission]
15
 
Signed-off-by:  Peter Maydell <peter.maydell@linaro.org>
16
 
---
17
 
 hw/misc/omap_clk.c | 735 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
18
 
 1 file changed, 727 insertions(+), 8 deletions(-)
19
 
 
20
 
diff --git a/hw/misc/omap_clk.c b/hw/misc/omap_clk.c
21
 
index 80a3c50..0ccb07a 100644
22
 
--- a/hw/misc/omap_clk.c
23
 
+++ b/hw/misc/omap_clk.c
24
 
@@ -34,7 +34,8 @@ struct clk {
25
 
 #define CLOCK_IN_OMAP16XX      (1 << 13)
26
 
 #define CLOCK_IN_OMAP242X      (1 << 14)
27
 
 #define CLOCK_IN_OMAP243X      (1 << 15)
28
 
-#define CLOCK_IN_OMAP343X      (1 << 16)
29
 
+#define CLOCK_IN_OMAP34XX       (1 << 16)
30
 
+#define CLOCK_IN_OMAP36XX       (1 << 17)
31
 
     uint32_t flags;
32
 
     int id;
33
 
 
34
 
@@ -947,6 +948,629 @@ static struct clk omapctrl_clk = {
35
 
     .parent    = &core_l4_iclk,
36
 
 };
37
 
 
38
 
+/* OMAP3 Clocks */
39
 
+
40
 
+static struct clk omap3_sys_32k = {
41
 
+    .name       = "omap3_sys_32k",
42
 
+    .rate       = 32768,
43
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
44
 
+};
45
 
+
46
 
+static struct clk omap3_osc_sys_clk12 = {
47
 
+    .name       = "omap3_osc_sys_clk12",
48
 
+    .rate       = 12000000,
49
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
50
 
+};
51
 
+
52
 
+static struct clk omap3_osc_sys_clk13 = {
53
 
+    .name       = "omap3_osc_sys_clk13",
54
 
+    .rate       = 13000000,
55
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
56
 
+};
57
 
+
58
 
+static struct clk omap3_osc_sys_clk168 = {
59
 
+    .name       = "omap3_osc_sys_clk168",
60
 
+    .rate       = 16800000,
61
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
62
 
+};
63
 
+
64
 
+static struct clk omap3_osc_sys_clk192 = {
65
 
+    .name       = "omap3_osc_sys_clk192",
66
 
+    .rate       = 19200000,
67
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
68
 
+};
69
 
+
70
 
+static struct clk omap3_osc_sys_clk26 = {
71
 
+    .name       = "omap3_osc_sys_clk26",
72
 
+    .rate       = 26000000,
73
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
74
 
+};
75
 
+
76
 
+static struct clk omap3_osc_sys_clk384 = {
77
 
+    .name       = "omap3_osc_sys_clk384",
78
 
+    .rate       = 38400000,
79
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
80
 
+};
81
 
+
82
 
+/*Is the altclk is enabled in beagle board?*/
83
 
+static struct clk omap3_sys_altclk = {
84
 
+    .name       = "omap3_sys_altclk",
85
 
+    .rate       = 13000000,
86
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
87
 
+};
88
 
+
89
 
+/*PRM*/
90
 
+static struct clk omap3_sys_clk = {
91
 
+    .name       = "omap3_sys_clk",
92
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
93
 
+    .parent     = &omap3_osc_sys_clk26,
94
 
+};
95
 
+
96
 
+static struct clk omap3_32k_fclk = {
97
 
+    .name       = "omap3_32k_fclk",
98
 
+    .rate       = 32768,
99
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
100
 
+    .parent     = &omap3_sys_32k,
101
 
+};
102
 
+
103
 
+/*DPLL3:
104
 
+ *       Input: SYS_CLK
105
 
+ *   Output:
106
 
+ *           DPLL3_M2_CLK  (CORE_CLK)
107
 
+ *           DPLL3_M2*2_CLK   (CORE*2_CLK)
108
 
+ *           EMULE_CORE_ALWON_CLK
109
 
+ */
110
 
+static struct clk omap3_core_clk = {
111
 
+    .name       = "omap3_core_clk",
112
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
113
 
+    .parent     = &omap3_sys_clk,
114
 
+};
115
 
+
116
 
+static struct clk omap3_core2_clk = {
117
 
+    .name       = "omap3_core2_clk",
118
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
119
 
+    .parent     = &omap3_sys_clk,
120
 
+};
121
 
+
122
 
+static struct clk omap3_emu_core_alwon_clk = {
123
 
+    .name       = "omap3_emu_core_alwon_clk",
124
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
125
 
+    .parent     = &omap3_sys_clk,
126
 
+};
127
 
+
128
 
+/*DPLL1 : it is for MPU
129
 
+ *    Input:
130
 
+ *           reference clock: SYS_CLK
131
 
+ *           bypass clock : CORE_CLK from dpll3
132
 
+ *    Output:
133
 
+ *           MPU_CLK (DPLL_CLK_M2)
134
 
+ */
135
 
+static struct clk omap3_mpu_clk = {
136
 
+    .name       = "omap3_mpu_clk",
137
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
138
 
+    .parent     = &omap3_core_clk,          /*between sys_clk and core_clk*/
139
 
+};
140
 
+
141
 
+/*DPLL2: it is for iva2*/
142
 
+static struct clk omap3_iva2_clk = {
143
 
+    .name       = "omap3_iva2_clk",
144
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
145
 
+    .parent     = &omap3_core_clk,          /*between sys_clk and core_clk*/
146
 
+};
147
 
+
148
 
+/* DPLL4:
149
 
+ *      INPUT: SYS_CLK
150
 
+ *      OUTPUT:
151
 
+ *              M2: 96M_FCLK
152
 
+ *              M3: TO TV(54M_FCLK)
153
 
+ *              M4: DSS1_ALWON_CLK
154
 
+ *              M5: CAM_CLK
155
 
+ *              M6: EMUL_PER_ALWON_CLK
156
 
+ */
157
 
+static struct clk omap3_dpll4_inref = {
158
 
+    .name   = "omap3_dpll4_inref",
159
 
+    .flags = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
160
 
+    .parent = &omap3_sys_clk,
161
 
+};
162
 
+
163
 
+static struct clk omap3_96m_fclk = {
164
 
+    .name       = "omap3_96m_fclk",
165
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
166
 
+    .parent     = &omap3_dpll4_inref,
167
 
+};
168
 
+
169
 
+static struct clk omap3_54m_fclk = {
170
 
+    .name       = "omap3_54m_fclk",
171
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
172
 
+    .parent     = &omap3_dpll4_inref,
173
 
+};
174
 
+
175
 
+static struct clk omap3_dss1_alwon_fclk = {
176
 
+    .name       = "omap3_dss1_alwon_fclk",
177
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
178
 
+    .parent     = &omap3_dpll4_inref,
179
 
+};
180
 
+
181
 
+static struct clk omap3_cam_mclk = {
182
 
+    .name       = "omap3_cam_mclk",
183
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
184
 
+    .parent     = &omap3_dpll4_inref,
185
 
+};
186
 
+
187
 
+static struct clk omap3_per_alwon_clk = {
188
 
+    .name       = "omap3_per_alwon_clk",
189
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
190
 
+    .parent     = &omap3_dpll4_inref,
191
 
+};
192
 
+
193
 
+/* DPLL5:
194
 
+ *      INPUT: SYS_CLK
195
 
+ *      OUTPUT:
196
 
+ *              M2: 120M_FCLK
197
 
+ */
198
 
+static struct clk omap3_120m_fclk = {
199
 
+    .name       = "omap3_120m_fclk",
200
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
201
 
+    .parent     = &omap3_sys_clk,
202
 
+};
203
 
+
204
 
+/*CM*/
205
 
+static struct clk omap3_48m_fclk = {
206
 
+    .name       = "omap3_48m_fclk",
207
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
208
 
+    .parent     = &omap3_96m_fclk, /* omap3_96m_fclk and omap3_sys_altclk */
209
 
+    .divisor = 2,
210
 
+    .multiplier = 1,
211
 
+};
212
 
+
213
 
+static struct clk omap3_12m_fclk = {
214
 
+    .name       = "omap3_12m_fclk",
215
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
216
 
+    .parent     = &omap3_96m_fclk, /*omap3_96m_fclk and omap3_sys_altclk */
217
 
+    .divisor = 8,
218
 
+    .multiplier = 1,
219
 
+};
220
 
+
221
 
+/*Common interface clock*/
222
 
+/*   Input: core_clk
223
 
+ *   Output:
224
 
+ *           l3x2_iclk
225
 
+ *           l3_iclk
226
 
+ *           l4_iclk
227
 
+ *           rm_iclk
228
 
+ */
229
 
+static struct clk omap3_l3x2_iclk = {
230
 
+    .name       = "omap3_l3x2_iclk",
231
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
232
 
+    .parent     = &omap3_core_clk,
233
 
+};
234
 
+
235
 
+static struct clk omap3_l3_iclk = {
236
 
+    .name       = "omap3_l3_iclk",
237
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
238
 
+    .parent     = &omap3_core_clk,
239
 
+};
240
 
+
241
 
+static struct clk omap3_l4_iclk = {
242
 
+    .name       = "omap3_l4_iclk",
243
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
244
 
+    .parent     = &omap3_l3_iclk,
245
 
+};
246
 
+static struct clk omap3_rm_iclk = {
247
 
+    .name       = "omap3_rm_iclk",
248
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
249
 
+    .parent     = &omap3_l4_iclk,
250
 
+};
251
 
+
252
 
+/*Core power domain clock*/
253
 
+/*   Input: cm_sys_clk
254
 
+ *            cm_32k_clk
255
 
+ *            120m_fclk
256
 
+ *            96m_fclk
257
 
+ *            48m_fclk
258
 
+ *            12m_fclk
259
 
+ *            l3_iclk
260
 
+ *            l4_iclk
261
 
+ *   Output:
262
 
+ *           gp10_fclk
263
 
+ *           gp11_fclk
264
 
+ *           core_32k_fclk
265
 
+ *           cpefuse_fclk
266
 
+ *           core_120M_fclk
267
 
+ *           usbttl_sap_fclk
268
 
+ *           core_96m_fclk
269
 
+ *           core_48m_flck
270
 
+ *           core_12m_fclk
271
 
+ *           core_l3_iclk
272
 
+ *           security_l3_iclk
273
 
+ *           core_l4_iclk
274
 
+ *           security_l4_iclk2
275
 
+ */
276
 
+static struct clk omap3_gp10_fclk = {
277
 
+    .name       = "omap3_gp10_fclk",
278
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
279
 
+    .parent     = &omap3_32k_fclk,   /*omap3_32k_fclk and omap3_sys_clk*/
280
 
+};
281
 
+
282
 
+static struct clk omap3_gp11_fclk = {
283
 
+    .name       = "omap3_gp11_fclk",
284
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
285
 
+    .parent     = &omap3_32k_fclk,   /*omap3_32k_fclk and omap3_sys_clk*/
286
 
+};
287
 
+
288
 
+static struct clk omap3_core_32k_fclk = {
289
 
+    .name       = "omap3_core_32k_fclk",
290
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
291
 
+    .parent     = &omap3_32k_fclk,
292
 
+};
293
 
+
294
 
+static struct clk omap3_cpefuse_fclk = {
295
 
+    .name       = "omap3_cpefuse_fclk",
296
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
297
 
+    .parent     = &omap3_sys_clk,
298
 
+};
299
 
+
300
 
+static struct clk omap3_core_120m_fclk = {
301
 
+    .name       = "omap3_core_120m_fclk",
302
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
303
 
+    .parent     = &omap3_120m_fclk,
304
 
+};
305
 
+
306
 
+static struct clk omap3_core_96m_fclk = {
307
 
+    .name       = "omap3_core_96m_fclk",
308
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
309
 
+    .parent     = &omap3_96m_fclk,
310
 
+    .divisor = 1,
311
 
+    .multiplier = 1,
312
 
+};
313
 
+
314
 
+static struct clk omap3_core_48m_fclk = {
315
 
+    .name       = "omap3_core_48m_fclk",
316
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
317
 
+    .parent     = &omap3_48m_fclk,
318
 
+};
319
 
+
320
 
+static struct clk omap3_core_12m_fclk = {
321
 
+    .name       = "omap3_core_12m_fclk",
322
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
323
 
+    .parent     = &omap3_12m_fclk,
324
 
+};
325
 
+
326
 
+static struct clk omap3_core_l3_iclk = {
327
 
+    .name       = "omap3_core_l3_iclk",
328
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
329
 
+    .parent     = &omap3_l3_iclk,
330
 
+};
331
 
+
332
 
+static struct clk omap3_core_l4_iclk = {
333
 
+    .name       = "omap3_core_l4_iclk",
334
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX | ALWAYS_ENABLED,
335
 
+    .parent     = &omap3_l4_iclk,
336
 
+};
337
 
+
338
 
+/* CORE_L3 interface clock based clocks */
339
 
+static struct clk omap3_sdrc_iclk = {
340
 
+    .name       = "omap3_sdrc_iclk",
341
 
+    .flags      = CLOCK_IN_OMAP34XX  | CLOCK_IN_OMAP36XX,
342
 
+    .parent     = &omap3_core_l3_iclk,
343
 
+};
344
 
+
345
 
+
346
 
+/*WKUP Power Domain*/
347
 
+static struct clk omap3_wkup_32k_fclk = {
348
 
+    .name       = "omap3_wkup_32k_fclk",
349
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
350
 
+    .parent     = &omap3_32k_fclk,
351
 
+};
352
 
+
353
 
+static struct clk omap3_wkup_l4_iclk = {
354
 
+    .name       = "omap3_wkup_l4_iclk",
355
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
356
 
+    .enabled    = 1,
357
 
+    .parent     = &omap3_sys_clk,
358
 
+};
359
 
+
360
 
+static struct clk omap3_gp1_fclk = {
361
 
+    .name       = "omap3_gp1_fclk",
362
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
363
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
364
 
+};
365
 
+
366
 
+static struct clk omap3_gp12_fclk = {
367
 
+    .name       = "omap3_gp12_fclk",
368
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
369
 
+    .parent     = &omap3_32k_fclk,        /* SECURE_32K_FCLK -> 32-kHz osc */
370
 
+};
371
 
+
372
 
+/*PER Power Domain clock*/
373
 
+/*gp2-gp9 timer*/
374
 
+static struct clk omap3_gp2_fclk = {
375
 
+    .name       = "omap3_gp2_fclk",
376
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
377
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
378
 
+};
379
 
+
380
 
+static struct clk omap3_gp3_fclk = {
381
 
+    .name       = "omap3_gp3_fclk",
382
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
383
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
384
 
+};
385
 
+
386
 
+static struct clk omap3_gp4_fclk = {
387
 
+    .name       = "omap3_gp4_fclk",
388
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
389
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
390
 
+};
391
 
+
392
 
+static struct clk omap3_gp5_fclk = {
393
 
+    .name       = "omap3_gp5_fclk",
394
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
395
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
396
 
+};
397
 
+
398
 
+static struct clk omap3_gp6_fclk = {
399
 
+    .name       = "omap3_gp6_fclk",
400
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
401
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
402
 
+};
403
 
+
404
 
+static struct clk omap3_gp7_fclk = {
405
 
+    .name       = "omap3_gp7_fclk",
406
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
407
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
408
 
+};
409
 
+
410
 
+static struct clk omap3_gp8_fclk = {
411
 
+    .name       = "omap3_gp8_fclk",
412
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
413
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
414
 
+};
415
 
+
416
 
+static struct clk omap3_gp9_fclk = {
417
 
+    .name       = "omap3_gp9_fclk",
418
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
419
 
+    .parent     = &omap3_32k_fclk,        /*omap3_32k_fclk and omap3_sys_clk*/
420
 
+};
421
 
+
422
 
+static struct clk omap3_per_96m_fclk = {
423
 
+    .name       = "omap3_per_96m_fclk",
424
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
425
 
+    .parent     = &omap3_96m_fclk,
426
 
+};
427
 
+
428
 
+static struct clk omap3_per_48m_fclk = {
429
 
+    .name       = "omap3_per_48m_fclk",
430
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
431
 
+    .parent     = &omap3_48m_fclk,
432
 
+};
433
 
+
434
 
+static struct clk omap3_per_32k_fclk = {
435
 
+    .name       = "omap3_per_32k_fclk",
436
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
437
 
+    .parent     = &omap3_32k_fclk,
438
 
+};
439
 
+
440
 
+static struct clk omap3_per_l4_iclk = {
441
 
+    .name       = "omap3_per_l4_iclk",
442
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
443
 
+    .enabled    = 1,
444
 
+    .parent     = &omap3_l4_iclk,
445
 
+};
446
 
+
447
 
+/*UART Clocks*/
448
 
+static struct clk omap3_uart1_fclk = {
449
 
+    .name       = "omap3_uart1_fclk",
450
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
451
 
+    .parent     = &omap3_core_48m_fclk,
452
 
+};
453
 
+
454
 
+static struct clk omap3_uart1_iclk = {
455
 
+    .name       = "omap3_uart1_iclk",
456
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
457
 
+    .parent     = &omap3_core_l4_iclk,
458
 
+};
459
 
+
460
 
+static struct clk omap3_uart2_fclk = {
461
 
+    .name       = "omap3_uart2_fclk",
462
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
463
 
+    .parent     = &omap3_core_48m_fclk,
464
 
+};
465
 
+
466
 
+static struct clk omap3_uart2_iclk = {
467
 
+    .name       = "omap3_uart2_iclk",
468
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
469
 
+    .parent     = &omap3_core_l4_iclk,
470
 
+};
471
 
+
472
 
+static struct clk omap3_uart3_fclk = {
473
 
+    .name       = "omap3_uart3_fclk",
474
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
475
 
+    .parent     = &omap3_per_48m_fclk,
476
 
+};
477
 
+
478
 
+static struct clk omap3_uart3_iclk = {
479
 
+    .name       = "omap3_uart3_iclk",
480
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
481
 
+    .parent     = &omap3_core_l4_iclk,
482
 
+};
483
 
+
484
 
+static struct clk omap3_uart4_fclk = {
485
 
+    .name       = "omap3_uart4_fclk",
486
 
+    .flags      = CLOCK_IN_OMAP36XX,
487
 
+    .parent     = &omap3_per_48m_fclk,
488
 
+};
489
 
+
490
 
+static struct clk omap3_uart4_iclk = {
491
 
+    .name       = "omap3_uart4_iclk",
492
 
+    .flags      = CLOCK_IN_OMAP36XX,
493
 
+    .parent     = &omap3_core_l4_iclk,
494
 
+};
495
 
+
496
 
+/*INTC Clock*/
497
 
+static struct clk omap3_mpu_intc_fclk = {
498
 
+    .name       = "omap3_mpu_intc_fclk",
499
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
500
 
+    .divisor    = 2,
501
 
+    .parent     = &omap3_mpu_clk,
502
 
+};
503
 
+
504
 
+static struct clk omap3_mpu_intc_iclk = {
505
 
+    .name       = "omap3_mpu_intc_iclk",
506
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
507
 
+    .divisor    = 2,
508
 
+    .parent     = &omap3_mpu_clk,
509
 
+};
510
 
+
511
 
+/*SDMA clock*/
512
 
+static struct clk omap3_sdma_fclk = {
513
 
+    .name       = "omap3_sdma_fclk",
514
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
515
 
+    .parent     = &omap3_core_l3_iclk,
516
 
+};
517
 
+
518
 
+static struct clk omap3_sdma_iclk = {
519
 
+    .name       = "omap3_sdma_iclk",
520
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
521
 
+    .parent     = &omap3_core_l4_iclk,
522
 
+};
523
 
+
524
 
+/*CLKOUT*/
525
 
+static struct clk omap3_sys_clkout1 = {
526
 
+    .name   = "omap3_sys_clkout1",
527
 
+    .flags = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
528
 
+    .parent = &omap3_osc_sys_clk26, /* same parent as as SYS_CLK */
529
 
+};
530
 
+
531
 
+static struct clk omap3_sys_clkout2 = {
532
 
+    .name       = "omap3_sys_clkout2",
533
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
534
 
+    .parent     = &omap3_core_clk, /*CORE_CLK CM_SYS_CLK CM_96M_FCLK 54MHz clk*/
535
 
+};
536
 
+
537
 
+/*MMC Clock*/
538
 
+static struct clk omap3_mmc1_fclk = {
539
 
+    .name       = "omap3_mmc1_fclk",
540
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
541
 
+    .parent     = &omap3_per_96m_fclk,
542
 
+};
543
 
+
544
 
+static struct clk omap3_mmc1_iclk = {
545
 
+    .name       = "omap3_mmc1_iclk",
546
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
547
 
+    .parent     = &omap3_per_l4_iclk,
548
 
+};
549
 
+
550
 
+static struct clk omap3_mmc2_fclk = {
551
 
+    .name       = "omap3_mmc2_fclk",
552
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
553
 
+    .parent     = &omap3_per_96m_fclk,
554
 
+};
555
 
+
556
 
+static struct clk omap3_mmc2_iclk = {
557
 
+    .name       = "omap3_mmc2_iclk",
558
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
559
 
+    .parent     = &omap3_per_l4_iclk,
560
 
+};
561
 
+
562
 
+static struct clk omap3_mmc3_fclk = {
563
 
+    .name       = "omap3_mmc3_fclk",
564
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
565
 
+    .parent     = &omap3_per_96m_fclk,
566
 
+};
567
 
+
568
 
+static struct clk omap3_mmc3_iclk = {
569
 
+    .name       = "omap3_mmc3_iclk",
570
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
571
 
+    .parent     = &omap3_per_l4_iclk,
572
 
+};
573
 
+
574
 
+/*I2C Clocks*/
575
 
+static struct clk omap3_i2c1_fclk = {
576
 
+    .name       = "omap3_i2c1_fclk",
577
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
578
 
+    .parent     = &omap3_per_96m_fclk,
579
 
+};
580
 
+
581
 
+static struct clk omap3_i2c1_iclk = {
582
 
+    .name       = "omap3_i2c1_iclk",
583
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
584
 
+    .parent     = &omap3_core_l4_iclk,
585
 
+};
586
 
+
587
 
+static struct clk omap3_i2c2_fclk = {
588
 
+    .name       = "omap3_i2c2_fclk",
589
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
590
 
+    .parent     = &omap3_per_96m_fclk,
591
 
+};
592
 
+
593
 
+static struct clk omap3_i2c2_iclk = {
594
 
+    .name       = "omap3_i2c2_iclk",
595
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
596
 
+    .parent     = &omap3_core_l4_iclk,
597
 
+};
598
 
+
599
 
+static struct clk omap3_i2c3_fclk = {
600
 
+    .name       = "omap3_i2c3_fclk",
601
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
602
 
+    .parent     = &omap3_per_96m_fclk,
603
 
+};
604
 
+
605
 
+static struct clk omap3_i2c3_iclk = {
606
 
+    .name       = "omap3_i2c3_iclk",
607
 
+    .flags      = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
608
 
+    .parent     = &omap3_core_l4_iclk,
609
 
+};
610
 
+
611
 
+/* SPI clocks */
612
 
+static struct clk omap3_spi1_fclk = {
613
 
+    .name   = "omap3_spi1_fclk",
614
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
615
 
+    .parent = &omap3_core_48m_fclk,
616
 
+};
617
 
+
618
 
+static struct clk omap3_spi1_iclk = {
619
 
+    .name   = "omap3_spi1_iclk",
620
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
621
 
+    .parent = &omap3_core_l4_iclk,
622
 
+};
623
 
+
624
 
+static struct clk omap3_spi2_fclk = {
625
 
+    .name   = "omap3_spi2_fclk",
626
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
627
 
+    .parent = &omap3_core_48m_fclk,
628
 
+};
629
 
+
630
 
+static struct clk omap3_spi2_iclk = {
631
 
+    .name   = "omap3_spi2_iclk",
632
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
633
 
+    .parent = &omap3_core_l4_iclk,
634
 
+};
635
 
+
636
 
+static struct clk omap3_spi3_fclk = {
637
 
+    .name   = "omap3_spi3_fclk",
638
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
639
 
+    .parent = &omap3_core_48m_fclk,
640
 
+};
641
 
+
642
 
+static struct clk omap3_spi3_iclk = {
643
 
+    .name   = "omap3_spi3_iclk",
644
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
645
 
+    .parent = &omap3_core_l4_iclk,
646
 
+};
647
 
+
648
 
+static struct clk omap3_spi4_fclk = {
649
 
+    .name   = "omap3_spi4_fclk",
650
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
651
 
+    .parent = &omap3_core_48m_fclk,
652
 
+};
653
 
+
654
 
+static struct clk omap3_spi4_iclk = {
655
 
+    .name   = "omap3_spi4_iclk",
656
 
+    .flags  = CLOCK_IN_OMAP34XX | CLOCK_IN_OMAP36XX,
657
 
+    .parent = &omap3_core_l4_iclk,
658
 
+};
659
 
+
660
 
+
661
 
 static struct clk *onchip_clks[] = {
662
 
     /* OMAP 1 */
663
 
 
664
 
@@ -1090,6 +1714,98 @@ static struct clk *onchip_clks[] = {
665
 
     &dss_l4_iclk,
666
 
     &omapctrl_clk,
667
 
 
668
 
+    /* OMAP 3*/
669
 
+
670
 
+    &omap3_sys_32k,
671
 
+    &omap3_osc_sys_clk12,
672
 
+    &omap3_osc_sys_clk13,
673
 
+    &omap3_osc_sys_clk168,
674
 
+    &omap3_osc_sys_clk192,
675
 
+    &omap3_osc_sys_clk26,
676
 
+    &omap3_osc_sys_clk384,
677
 
+    &omap3_sys_altclk,
678
 
+    &omap3_sys_clk,
679
 
+    &omap3_32k_fclk,
680
 
+    &omap3_core_clk,
681
 
+    &omap3_core2_clk,
682
 
+    &omap3_emu_core_alwon_clk,
683
 
+    &omap3_mpu_clk,
684
 
+    &omap3_iva2_clk,
685
 
+    &omap3_dpll4_inref,
686
 
+    &omap3_96m_fclk,
687
 
+    &omap3_54m_fclk,
688
 
+    &omap3_dss1_alwon_fclk,
689
 
+    &omap3_cam_mclk,
690
 
+    &omap3_per_alwon_clk,
691
 
+    &omap3_120m_fclk,
692
 
+    &omap3_48m_fclk,
693
 
+    &omap3_12m_fclk,
694
 
+    &omap3_l3x2_iclk,
695
 
+    &omap3_l3_iclk,
696
 
+    &omap3_l4_iclk,
697
 
+    &omap3_rm_iclk,
698
 
+    &omap3_gp10_fclk,
699
 
+    &omap3_gp11_fclk,
700
 
+    &omap3_core_32k_fclk,
701
 
+    &omap3_cpefuse_fclk,
702
 
+    &omap3_core_120m_fclk,
703
 
+    &omap3_core_96m_fclk,
704
 
+    &omap3_core_48m_fclk,
705
 
+    &omap3_core_12m_fclk,
706
 
+    &omap3_core_l3_iclk,
707
 
+    &omap3_core_l4_iclk,
708
 
+    &omap3_sdrc_iclk,
709
 
+    &omap3_wkup_32k_fclk,
710
 
+    &omap3_wkup_l4_iclk,
711
 
+    &omap3_gp1_fclk,
712
 
+    &omap3_gp12_fclk,
713
 
+    &omap3_gp2_fclk,
714
 
+    &omap3_gp3_fclk,
715
 
+    &omap3_gp4_fclk,
716
 
+    &omap3_gp5_fclk,
717
 
+    &omap3_gp6_fclk,
718
 
+    &omap3_gp7_fclk,
719
 
+    &omap3_gp8_fclk,
720
 
+    &omap3_gp9_fclk,
721
 
+    &omap3_per_96m_fclk,
722
 
+    &omap3_per_48m_fclk,
723
 
+    &omap3_per_32k_fclk,
724
 
+    &omap3_per_l4_iclk,
725
 
+    &omap3_uart1_fclk,
726
 
+    &omap3_uart1_iclk,
727
 
+    &omap3_uart2_fclk,
728
 
+    &omap3_uart2_iclk,
729
 
+    &omap3_uart3_fclk,
730
 
+    &omap3_uart3_iclk,
731
 
+    &omap3_uart4_fclk,
732
 
+    &omap3_uart4_iclk,
733
 
+    &omap3_mpu_intc_fclk,
734
 
+    &omap3_mpu_intc_iclk,
735
 
+    &omap3_sdma_fclk,
736
 
+    &omap3_sdma_iclk,
737
 
+    &omap3_sys_clkout1,
738
 
+    &omap3_sys_clkout2,
739
 
+    &omap3_mmc1_fclk,
740
 
+    &omap3_mmc1_iclk,
741
 
+    &omap3_mmc2_fclk,
742
 
+    &omap3_mmc2_iclk,
743
 
+    &omap3_mmc3_fclk,
744
 
+    &omap3_mmc3_iclk,
745
 
+    &omap3_i2c1_fclk,
746
 
+    &omap3_i2c1_iclk,
747
 
+    &omap3_i2c2_fclk,
748
 
+    &omap3_i2c2_iclk,
749
 
+    &omap3_i2c3_fclk,
750
 
+    &omap3_i2c3_iclk,
751
 
+    &omap3_spi1_fclk,
752
 
+    &omap3_spi1_iclk,
753
 
+    &omap3_spi2_fclk,
754
 
+    &omap3_spi2_iclk,
755
 
+    &omap3_spi3_fclk,
756
 
+    &omap3_spi3_iclk,
757
 
+    &omap3_spi4_fclk,
758
 
+    &omap3_spi4_iclk,
759
 
+
760
 
     NULL
761
 
 };
762
 
 
763
 
@@ -1223,18 +1939,21 @@ void omap_clk_init(struct omap_mpu_state_s *mpu)
764
 
     int count;
765
 
     int flag;
766
 
 
767
 
-    if (cpu_is_omap310(mpu))
768
 
+    if (cpu_is_omap310(mpu)) {
769
 
         flag = CLOCK_IN_OMAP310;
770
 
-    else if (cpu_is_omap1510(mpu))
771
 
+    } else if (cpu_is_omap1510(mpu)) {
772
 
         flag = CLOCK_IN_OMAP1510;
773
 
-    else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
774
 
+    } else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu)) {
775
 
         flag = CLOCK_IN_OMAP242X;
776
 
-    else if (cpu_is_omap2430(mpu))
777
 
-        flag = CLOCK_IN_OMAP243X;
778
 
-    else if (cpu_is_omap3430(mpu))
779
 
+    } else if (cpu_is_omap2430(mpu)) {
780
 
         flag = CLOCK_IN_OMAP243X;
781
 
-    else
782
 
+    } else if (cpu_is_omap3430(mpu)) {
783
 
+        flag = CLOCK_IN_OMAP34XX;
784
 
+    } else if (cpu_is_omap3630(mpu)) {
785
 
+        flag = CLOCK_IN_OMAP36XX;
786
 
+    } else {
787
 
         return;
788
 
+    }
789
 
 
790
 
     for (i = onchip_clks, count = 0; *i; i ++)
791
 
         if ((*i)->flags & flag)
792
 
1.8.5.2
793