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From af0a1192fc770c6d6921d83fab897cc561c9b3c9 Mon Sep 17 00:00:00 2001
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From: Will Newton <will.newton@linaro.org>
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Date: Fri, 6 Dec 2013 17:01:42 +0000
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Subject: [PATCH 15/49] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM
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This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
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Signed-off-by: Will Newton <will.newton@linaro.org>
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Message-id: 1386158099-9239-7-git-send-email-will.newton@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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target-arm/translate.c | 31 ++++++++++++++++++++++---------
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1 file changed, 22 insertions(+), 9 deletions(-)
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diff --git a/target-arm/translate.c b/target-arm/translate.c
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index 9a8069e..73ed266 100644
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--- a/target-arm/translate.c
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+++ b/target-arm/translate.c
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@@ -4553,7 +4553,7 @@ static void gen_neon_narrow_op(int op, int u, int size,
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#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
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#define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
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#define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
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-#define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */
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+#define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
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static const uint8_t neon_3r_sizes[] = {
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[NEON_3R_VHADD] = 0x7,
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@@ -4586,7 +4586,7 @@ static const uint8_t neon_3r_sizes[] = {
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[NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
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[NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
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[NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
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- [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */
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+ [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */
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/* Symbolic constants for op fields for Neon 2-register miscellaneous.
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@@ -4847,8 +4847,9 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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- case NEON_3R_VRECPS_VRSQRTS:
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+ case NEON_3R_FLOAT_MISC:
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+ /* VMAXNM/VMINNM in ARMv8 */
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+ if (u && !arm_feature(env, ARM_FEATURE_V8)) {
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@@ -5137,11 +5138,23 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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tcg_temp_free_ptr(fpstatus);
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- case NEON_3R_VRECPS_VRSQRTS:
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- gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
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- gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
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+ case NEON_3R_FLOAT_MISC:
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+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
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+ gen_helper_vfp_maxnms(tmp, tmp, tmp2, fpstatus);
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+ gen_helper_vfp_minnms(tmp, tmp, tmp2, fpstatus);
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+ tcg_temp_free_ptr(fpstatus);
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+ gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
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+ gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);