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From 3c164ca61b304200f0acbcf53826a46bb1c04da0 Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Mon, 18 Feb 2013 16:58:33 +0000
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Subject: [PATCH 59/70] Add Cortex A8 r2 support
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target-arm/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 41 insertions(+)
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diff --git a/target-arm/cpu.c b/target-arm/cpu.c
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index e46fc4a..3dd5b02 100644
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--- a/target-arm/cpu.c
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+++ b/target-arm/cpu.c
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@@ -550,6 +550,46 @@ static void cortex_a8_initfn(Object *obj)
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define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
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+static void cortex_a8_r2_initfn(Object *obj)
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+ * 1. do we really need this?
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+ * 2. are these register values all correct? mostly same as A8 currently
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+ ARMCPU *cpu = ARM_CPU(obj);
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+ set_feature(&cpu->env, ARM_FEATURE_V7);
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+ set_feature(&cpu->env, ARM_FEATURE_VFP3);
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+ set_feature(&cpu->env, ARM_FEATURE_NEON);
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+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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+ set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);
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+ cpu->midr = 0x410fc083;
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+ cpu->reset_fpsid = 0x410330c2;
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+ cpu->mvfr0 = 0x11110222;
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+ cpu->mvfr1 = 0x00011111;
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+ cpu->ctr = 0x82048004;
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+ cpu->reset_sctlr = 0x00c50078;
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+ cpu->id_pfr0 = 0x1031;
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+ cpu->id_pfr1 = 0x11;
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+ cpu->id_dfr0 = 0x400;
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+ cpu->id_mmfr0 = 0x31100003;
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+ cpu->id_mmfr1 = 0x20000000;
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+ cpu->id_mmfr2 = 0x01202000;
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+ cpu->id_mmfr3 = 0x11;
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+ cpu->id_isar0 = 0x00101111;
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+ cpu->id_isar1 = 0x12112111;
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+ cpu->id_isar2 = 0x21232031;
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+ cpu->id_isar3 = 0x11112131;
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+ cpu->id_isar4 = 0x00111142;
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+ cpu->clidr = (1 << 27) | (2 << 24) | 3;
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+ cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
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+ cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
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+ cpu->ccsidr[2] = 0xf03fe03a; /* 256k L2 cache. */
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+ cpu->reset_auxcr = 2;
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+ define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
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static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
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/* power_control should be set to maximum latency. Again,
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* default to 0 and set by private hook
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@@ -874,6 +914,7 @@ static const ARMCPUInfo arm_cpus[] = {
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{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
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+ { .name = "cortex-a8-r2",.initfn = cortex_a8_r2_initfn },
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{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
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{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
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{ .name = "ti925t", .initfn = ti925t_initfn },