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#include "nv30_context.h"
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#include "nouveau/nouveau_util.h"
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nv30_state_framebuffer_validate(struct nv30_context *nv30)
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struct pipe_framebuffer_state *fb = &nv30->framebuffer;
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struct nouveau_channel *chan = nv30->screen->base.channel;
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struct nouveau_grobj *rankine = nv30->screen->rankine;
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struct nv04_surface *rt[2], *zeta = NULL;
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uint32_t rt_enable = 0, rt_format = 0;
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int i, colour_format = 0, zeta_format = 0, depth_only = 0;
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struct nouveau_stateobj *so = so_new(12, 18, 10);
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unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
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unsigned w = fb->width;
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unsigned h = fb->height;
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struct nv30_miptree *nv30mt;
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int colour_bits = 32, zeta_bits = 32;
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for (i = 0; i < fb->nr_cbufs; i++) {
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assert(colour_format == fb->cbufs[i]->format);
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colour_format = fb->cbufs[i]->format;
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rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
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rt[i] = (struct nv04_surface *)fb->cbufs[i];
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if (rt_enable & NV34TCL_RT_ENABLE_COLOR1)
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rt_enable |= NV34TCL_RT_ENABLE_MRT;
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zeta_format = fb->zsbuf->format;
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zeta = (struct nv04_surface *)fb->zsbuf;
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if (rt_enable & (NV34TCL_RT_ENABLE_COLOR0|NV34TCL_RT_ENABLE_COLOR1)) {
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/* Render to at least a colour buffer */
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if (!(rt[0]->base.texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
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assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
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for (i = 1; i < fb->nr_cbufs; i++)
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assert(!(rt[i]->base.texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR));
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rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
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(log2i(rt[0]->base.width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
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(log2i(rt[0]->base.height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
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rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
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} else if (fb->zsbuf) {
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/* Render to depth buffer only */
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if (!(zeta->base.texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
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assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
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rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
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(log2i(zeta->base.width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
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(log2i(zeta->base.height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
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rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
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switch (colour_format) {
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case PIPE_FORMAT_B8G8R8X8_UNORM:
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rt_format |= NV34TCL_RT_FORMAT_COLOR_X8R8G8B8;
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case PIPE_FORMAT_B8G8R8A8_UNORM:
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rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
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case PIPE_FORMAT_B5G6R5_UNORM:
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rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
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switch (zeta_format) {
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case PIPE_FORMAT_Z16_UNORM:
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rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
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case PIPE_FORMAT_S8Z24_UNORM:
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case PIPE_FORMAT_X8Z24_UNORM:
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rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
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if (colour_bits > zeta_bits) {
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if (depth_only || (rt_enable & NV34TCL_RT_ENABLE_COLOR0)) {
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struct nv04_surface *rt0 = (depth_only ? zeta : rt[0]);
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uint32_t pitch = rt0->pitch;
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pitch |= (zeta->pitch << 16);
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pitch |= (pitch << 16);
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nv30mt = (struct nv30_miptree *) rt0->base.texture;
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so_method(so, rankine, NV34TCL_DMA_COLOR0, 1);
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so_reloc (so, nouveau_bo(nv30mt->buffer), 0, rt_flags | NOUVEAU_BO_OR,
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chan->vram->handle, chan->gart->handle);
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so_method(so, rankine, NV34TCL_COLOR0_PITCH, 2);
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so_reloc (so, nouveau_bo(nv30mt->buffer), rt0->base.offset,
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rt_flags | NOUVEAU_BO_LOW, 0, 0);
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if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
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nv30mt = (struct nv30_miptree *)rt[1]->base.texture;
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so_method(so, rankine, NV34TCL_DMA_COLOR1, 1);
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so_reloc (so, nouveau_bo(nv30mt->buffer), 0, rt_flags | NOUVEAU_BO_OR,
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chan->vram->handle, chan->gart->handle);
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so_method(so, rankine, NV34TCL_COLOR1_OFFSET, 2);
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so_reloc (so, nouveau_bo(nv30mt->buffer), rt[1]->base.offset,
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rt_flags | NOUVEAU_BO_LOW, 0, 0);
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so_data (so, rt[1]->pitch);
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nv30mt = (struct nv30_miptree *)zeta->base.texture;
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so_method(so, rankine, NV34TCL_DMA_ZETA, 1);
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so_reloc (so, nouveau_bo(nv30mt->buffer), 0, rt_flags | NOUVEAU_BO_OR,
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chan->vram->handle, chan->gart->handle);
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so_method(so, rankine, NV34TCL_ZETA_OFFSET, 1);
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so_reloc (so, nouveau_bo(nv30mt->buffer), zeta->base.offset,
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rt_flags | NOUVEAU_BO_LOW, 0, 0);
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/* TODO: allocate LMA depth buffer */
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so_method(so, rankine, NV34TCL_RT_ENABLE, 1);
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so_data (so, rt_enable);
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so_method(so, rankine, NV34TCL_RT_HORIZ, 3);
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so_data (so, (w << 16) | 0);
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so_data (so, (h << 16) | 0);
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so_data (so, rt_format);
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so_method(so, rankine, NV34TCL_VIEWPORT_HORIZ, 2);
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so_data (so, (w << 16) | 0);
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so_data (so, (h << 16) | 0);
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so_method(so, rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
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so_data (so, ((w - 1) << 16) | 0);
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so_data (so, ((h - 1) << 16) | 0);
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so_method(so, rankine, 0x1d88, 1);
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so_data (so, (1 << 12) | h);
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/* Wonder why this is needed, context should all be set to zero on init */
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so_method(so, rankine, NV34TCL_VIEWPORT_TX_ORIGIN, 1);
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so_ref(so, &nv30->state.hw[NV30_STATE_FB]);
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struct nv30_state_entry nv30_state_framebuffer = {
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.validate = nv30_state_framebuffer_validate,