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Viewing changes to src/mesa/drivers/dri/i915/i915_vtbl.c

  • Committer: Bazaar Package Importer
  • Author(s): Robert Hooker, Robert Hooker, Christopher James Halse Rogers
  • Date: 2010-09-14 08:55:40 UTC
  • mfrom: (1.2.28 upstream)
  • Revision ID: james.westby@ubuntu.com-20100914085540-m4fpl0hdjlfd4jgz
Tags: 7.9~git20100909-0ubuntu1
https://launchpad.net/bugs/631413
https://launchpad.net/bugs/628930
https://launchpad.net/bugs/628727
https://launchpad.net/bugs/596292
https://launchpad.net/bugs/599741
https://launchpad.net/bugs/630315
https://launchpad.net/bugs/613694
https://launchpad.net/bugs/599741
https://launchpad.net/bugs/578619
https://launchpad.net/bugs/626943
https://launchpad.net/bugs/610541
https://launchpad.net/bugs/601052
[ Robert Hooker ]
* New upstream git snapshot up to commit 94118fe2d4b1e5 (LP: #631413)
* New features include ATI HD5xxx series support in r600, and a vastly
  improved glsl compiler.
* Remove pre-generated .pc's, use the ones generated at build time
  instead.
* Remove all references to mesa-utils now that its no longer shipped
  with the mesa source.
* Disable the experimental ARB_fragment_shader option by default on
  i915, it exposes incomplete functionality that breaks KDE compositing
  among other things. It can be enabled via driconf still. (LP: #628930).

[ Christopher James Halse Rogers ]
* debian/patches/04_osmesa_version.diff:
  - Refresh for new upstream
* Bugs fixed in this release:
  - Fixes severe rendering corruption in Unity on radeon (LP: #628727,
    LP: #596292, LP: #599741, LP: #630315, LP: #613694, LP: #599741).
  - Also fixes rendering in gnome-shell (LP: #578619).
  - Flickering in OpenGL apps on radeon (LP: #626943, LP: #610541).
  - Provides preliminary support for new intel chips (LP: #601052).
* debian/rules:
  - Update configure flags to match upstream reshuffling.
  - Explicitly remove gallium DRI drivers that we don't want to ship.
* Update debian/gbp.conf for this Maverick-specific packaging
* libegl1-mesa-dri-x11,kms: There are no longer separate kms or x11 drivers
  for EGL, libegl1-mesa-drivers now contains a single driver that provides
  both backends.

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Lines of Context:
src/mesa/drivers/dri/i915/i915_vtbl.c
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   struct i915_hw_state *state = &i915->state;
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   int i, count, aper_count;
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   GLuint dirty;
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   dri_bo *aper_array[3 + I915_TEX_UNITS];
 
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   drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
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   GET_CURRENT_CONTEXT(ctx);
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   BATCH_LOCALS;
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   }
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   if (dirty & I915_UPLOAD_BUFFERS) {
369
 
      GLuint count = 15;
 
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      GLuint count;
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      if (INTEL_DEBUG & DEBUG_STATE)
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         fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
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      count = 14;
 
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      if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 
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         count++;
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      if (state->depth_region)
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          count += 3;
 
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         count += 3;
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      BEGIN_BATCH(count);
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      OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
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      OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
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      OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
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      assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
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      OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 
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      if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 
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         OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
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      OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
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      OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
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      OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
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   for (i = 0; i < I915_TEX_UNITS; i++) {
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      if (i915->state.tex_buffer[i] != NULL) {
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         dri_bo_unreference(i915->state.tex_buffer[i]);
 
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         drm_intel_bo_unreference(i915->state.tex_buffer[i]);
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         i915->state.tex_buffer[i] = NULL;
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      }
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   }
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   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
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   GLuint value;
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   struct i915_hw_state *state = &i915->state;
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   uint32_t draw_x, draw_y;
 
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   uint32_t draw_x, draw_y, draw_offset;
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   if (state->draw_region != color_regions[0]) {
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      intel_region_release(&state->draw_region);
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      draw_y = 0;
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   }
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   draw_offset = (draw_y << 16) | draw_x;
 
628
 
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   /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
625
 
   state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH;
 
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   if (draw_offset != i915->last_draw_offset) {
 
631
      FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
 
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               (ctx->DrawBuffer->Width + draw_x > 2048) ||
 
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               (ctx->DrawBuffer->Height + draw_y > 2048));
 
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      state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
 
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      i915->last_draw_offset = draw_offset;
 
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   } else
 
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      state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 
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   state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
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   state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
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   state->Buffer[I915_DESTREG_DRAWRECT3] = (draw_y << 16) | draw_x;
 
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   state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
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   state->Buffer[I915_DESTREG_DRAWRECT4] =
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      ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
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      ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
632
 
   state->Buffer[I915_DESTREG_DRAWRECT5] = (draw_y << 16) | draw_x;
 
646
   state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
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   I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
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}
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    * difficulties associated with them (physical address requirements).
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    */
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   i915->state.emitted = 0;
 
663
   i915->last_draw_offset = 0;
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}
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static void