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Viewing changes to src/gallium/drivers/nv50/nv50_texture.h

  • Committer: Bazaar Package Importer
  • Author(s): Robert Hooker, Robert Hooker, Christopher James Halse Rogers
  • Date: 2010-09-14 08:55:40 UTC
  • mfrom: (1.2.28 upstream)
  • Revision ID: james.westby@ubuntu.com-20100914085540-m4fpl0hdjlfd4jgz
Tags: 7.9~git20100909-0ubuntu1
[ Robert Hooker ]
* New upstream git snapshot up to commit 94118fe2d4b1e5 (LP: #631413)
* New features include ATI HD5xxx series support in r600, and a vastly
  improved glsl compiler.
* Remove pre-generated .pc's, use the ones generated at build time
  instead.
* Remove all references to mesa-utils now that its no longer shipped
  with the mesa source.
* Disable the experimental ARB_fragment_shader option by default on
  i915, it exposes incomplete functionality that breaks KDE compositing
  among other things. It can be enabled via driconf still. (LP: #628930).

[ Christopher James Halse Rogers ]
* debian/patches/04_osmesa_version.diff:
  - Refresh for new upstream
* Bugs fixed in this release:
  - Fixes severe rendering corruption in Unity on radeon (LP: #628727,
    LP: #596292, LP: #599741, LP: #630315, LP: #613694, LP: #599741).
  - Also fixes rendering in gnome-shell (LP: #578619).
  - Flickering in OpenGL apps on radeon (LP: #626943, LP: #610541).
  - Provides preliminary support for new intel chips (LP: #601052).
* debian/rules:
  - Update configure flags to match upstream reshuffling.
  - Explicitly remove gallium DRI drivers that we don't want to ship.
* Update debian/gbp.conf for this Maverick-specific packaging
* libegl1-mesa-dri-x11,kms: There are no longer separate kms or x11 drivers
  for EGL, libegl1-mesa-drivers now contains a single driver that provides
  both backends.

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/* Texture image control block */
 
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#define NV50TIC_0_0_SWIZZLE_MASK                                  0x3ffc0000
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#define NV50TIC_0_0_MAPA_MASK                                     0x38000000
 
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#define NV50TIC_0_0_MAPA_SHIFT                                            27
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#define NV50TIC_0_0_MAPA_ZERO                                     0x00000000
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#define NV50TIC_0_0_MAPA_C0                                       0x10000000
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#define NV50TIC_0_0_MAPA_C1                                       0x18000000
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#define NV50TIC_0_0_MAPA_C3                                       0x28000000
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#define NV50TIC_0_0_MAPA_ONE                                      0x38000000
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#define NV50TIC_0_0_MAPB_MASK                                     0x07000000
 
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#define NV50TIC_0_0_MAPB_SHIFT                                            24
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#define NV50TIC_0_0_MAPB_ZERO                                     0x00000000
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#define NV50TIC_0_0_MAPB_C0                                       0x02000000
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#define NV50TIC_0_0_MAPB_C1                                       0x03000000
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#define NV50TIC_0_0_MAPB_C3                                       0x05000000
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#define NV50TIC_0_0_MAPB_ONE                                      0x07000000
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#define NV50TIC_0_0_MAPG_MASK                                     0x00e00000
 
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#define NV50TIC_0_0_MAPG_SHIFT                                            21
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#define NV50TIC_0_0_MAPG_ZERO                                     0x00000000
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#define NV50TIC_0_0_MAPG_C0                                       0x00400000
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#define NV50TIC_0_0_MAPG_C1                                       0x00600000
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#define NV50TIC_0_0_MAPG_C3                                       0x00a00000
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#define NV50TIC_0_0_MAPG_ONE                                      0x00e00000
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#define NV50TIC_0_0_MAPR_MASK                                     0x001c0000
 
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#define NV50TIC_0_0_MAPR_SHIFT                                            18
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#define NV50TIC_0_0_MAPR_ZERO                                     0x00000000
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#define NV50TIC_0_0_MAPR_C0                                       0x00080000
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#define NV50TIC_0_0_MAPR_C1                                       0x000c0000
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#define NV50TIC_0_1_OFFSET_LOW_MASK                               0xffffffff
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#define NV50TIC_0_1_OFFSET_LOW_SHIFT                                       0
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#define NV50TIC_0_2_UNKNOWN_MASK                                  0xffffffff
 
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#define NV50TIC_0_2_COLORSPACE_SRGB                               0x00000400
 
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#define NV50TIC_0_2_TARGET_1D                                     0x00000000
 
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#define NV50TIC_0_2_TARGET_2D                                     0x00004000
 
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#define NV50TIC_0_2_TARGET_3D                                     0x00008000
 
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#define NV50TIC_0_2_TARGET_CUBE                                   0x0000c000
 
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#define NV50TIC_0_2_TARGET_1D_ARRAY                               0x00010000
 
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#define NV50TIC_0_2_TARGET_2D_ARRAY                               0x00014000
 
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#define NV50TIC_0_2_TARGET_BUFFER                                 0x00018000
 
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#define NV50TIC_0_2_TARGET_RECT                                   0x0001c000
 
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/* #define NV50TIC_0_0_TILE_MODE_LINEAR                           0x00040000 */
 
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#define NV50TIC_0_2_TILE_MODE_Y_MASK                              0x01c00000
 
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#define NV50TIC_0_2_TILE_MODE_Y_SHIFT                                     22
 
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#define NV50TIC_0_2_TILE_MODE_Z_MASK                              0x0e000000
 
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#define NV50TIC_0_2_TILE_MODE_Z_SHIFT                                     25
 
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#define NV50TIC_0_2_NORMALIZED_COORDS                             0x80000000
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#define NV50TIC_0_3_UNKNOWN_MASK                                  0xffffffff
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#define NV50TIC_0_4_WIDTH_MASK                                    0x0000ffff
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#define NV50TIC_0_4_WIDTH_SHIFT                                            0
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#define NV50TIC_0_5_DEPTH_MASK                                    0xffff0000
 
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#define NV50TIC_0_5_LAST_LEVEL_MASK                               0xf0000000
 
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#define NV50TIC_0_5_LAST_LEVEL_SHIFT                                      28
 
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#define NV50TIC_0_5_DEPTH_MASK                                    0x0fff0000
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#define NV50TIC_0_5_DEPTH_SHIFT                                           16
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#define NV50TIC_0_5_HEIGHT_MASK                                   0x0000ffff
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#define NV50TIC_0_5_HEIGHT_SHIFT                                           0
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#define NV50TIC_0_6_UNKNOWN_MASK                                  0xffffffff
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#define NV50TIC_0_7_OFFSET_HIGH_MASK                              0xffffffff
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#define NV50TIC_0_7_OFFSET_HIGH_SHIFT                                      0
 
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#define NV50TIC_0_7_BASE_LEVEL_MASK                               0x0000000f
 
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#define NV50TIC_0_7_BASE_LEVEL_SHIFT                                       0
 
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#define NV50TIC_0_7_MAX_LEVEL_MASK                                0x000000f0
 
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#define NV50TIC_0_7_MAX_LEVEL_SHIFT                                        4
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/* Texture sampler control block */
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#define NV50TSC_1_0_WRAPS_MASK                                   0x00000007