2
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "pipe/p_shader_tokens.h"
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#include "tgsi/tgsi_parse.h"
25
#include "tgsi/tgsi_scan.h"
26
#include "tgsi/tgsi_dump.h"
27
#include "util/u_format.h"
28
#include "r600_screen.h"
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#include "r600_context.h"
30
#include "r600_shader.h"
33
#include "r600_opcodes.h"
39
struct r600_shader_tgsi_instruction;
41
struct r600_shader_ctx {
42
struct tgsi_shader_info info;
43
struct tgsi_parse_context parse;
44
const struct tgsi_token *tokens;
46
unsigned file_offset[TGSI_FILE_COUNT];
48
struct r600_shader_tgsi_instruction *inst_info;
50
struct r600_shader *shader;
54
u32 max_driver_temp_used;
57
struct r600_shader_tgsi_instruction {
61
int (*process)(struct r600_shader_ctx *ctx);
64
static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
65
static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
66
static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
68
static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
70
struct r600_context *rctx = r600_context(ctx);
71
const struct util_format_description *desc;
72
enum pipe_format resource_format[160];
73
unsigned i, nresources = 0;
74
struct r600_bc *bc = &shader->bc;
75
struct r600_bc_cf *cf;
76
struct r600_bc_vtx *vtx;
78
if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
80
for (i = 0; i < rctx->vertex_elements->count; i++) {
81
resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
83
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
85
case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
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case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
87
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
88
desc = util_format_description(resource_format[vtx->buffer_id]);
90
R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
93
vtx->dst_sel_x = desc->swizzle[0];
94
vtx->dst_sel_y = desc->swizzle[1];
95
vtx->dst_sel_z = desc->swizzle[2];
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vtx->dst_sel_w = desc->swizzle[3];
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return r600_bc_build(&shader->bc);
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int r600_pipe_shader_create(struct pipe_context *ctx,
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struct r600_context_state *rpshader,
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const struct tgsi_token *tokens)
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struct r600_screen *rscreen = r600_screen(ctx->screen);
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//fprintf(stderr, "--------------------------------------------------------------\n");
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//tgsi_dump(tokens, 0);
115
if (rpshader == NULL)
117
rpshader->shader.family = radeon_get_family(rscreen->rw);
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rpshader->shader.use_mem_constant = rscreen->use_mem_constant;
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r = r600_shader_from_tgsi(tokens, &rpshader->shader);
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R600_ERR("translation from TGSI failed !\n");
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r = r600_bc_build(&rpshader->shader.bc);
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R600_ERR("building bytecode failed !\n");
129
//fprintf(stderr, "______________________________________________________________\n");
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static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
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struct r600_context *rctx = r600_context(ctx);
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struct radeon_state *state;
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state = &rpshader->rstate[0];
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radeon_state_fini(&rpshader->rstate[0]);
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return rctx->vtbl->vs_shader(rctx, rpshader, state);
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static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
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struct r600_context *rctx = r600_context(ctx);
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struct radeon_state *state;
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state = &rpshader->rstate[0];
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radeon_state_fini(state);
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return rctx->vtbl->ps_shader(rctx, rpshader, state);
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static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
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struct r600_screen *rscreen = r600_screen(ctx->screen);
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struct r600_context *rctx = r600_context(ctx);
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struct r600_shader *rshader = &rpshader->shader;
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/* copy new shader */
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radeon_bo_decref(rscreen->rw, rpshader->bo);
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rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
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if (rpshader->bo == NULL) {
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radeon_bo_map(rscreen->rw, rpshader->bo);
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memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
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radeon_bo_unmap(rscreen->rw, rpshader->bo);
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rshader->flat_shade = rctx->flat_shade;
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switch (rshader->processor_type) {
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case TGSI_PROCESSOR_VERTEX:
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r = r600_pipe_shader_vs(ctx, rpshader);
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case TGSI_PROCESSOR_FRAGMENT:
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r = r600_pipe_shader_ps(ctx, rpshader);
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int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
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struct r600_context *rctx = r600_context(ctx);
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if (rpshader == NULL)
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/* there should be enough input */
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if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
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R600_ERR("%d resources provided, expecting %d\n",
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rctx->vertex_elements->count, rpshader->shader.bc.nresource);
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r = r600_shader_update(ctx, &rpshader->shader);
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return r600_pipe_shader(ctx, rpshader);
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static int tgsi_is_supported(struct r600_shader_ctx *ctx)
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struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
213
if (i->Instruction.NumDstRegs > 1) {
214
R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
217
if (i->Instruction.Predicate) {
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R600_ERR("predicate unsupported\n");
222
if (i->Instruction.Label) {
223
R600_ERR("label unsupported\n");
227
for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
228
if (i->Src[j].Register.Dimension ||
229
i->Src[j].Register.Absolute) {
230
R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
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i->Src[j].Register.Dimension,
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i->Src[j].Register.Absolute);
236
for (j = 0; j < i->Instruction.NumDstRegs; j++) {
237
if (i->Dst[j].Register.Dimension) {
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R600_ERR("unsupported dst (dimension)\n");
245
static int tgsi_declaration(struct r600_shader_ctx *ctx)
247
struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
248
struct r600_bc_vtx vtx;
252
switch (d->Declaration.File) {
253
case TGSI_FILE_INPUT:
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i = ctx->shader->ninput++;
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ctx->shader->input[i].name = d->Semantic.Name;
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ctx->shader->input[i].sid = d->Semantic.Index;
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ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
258
ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
259
if (ctx->type == TGSI_PROCESSOR_VERTEX) {
260
/* turn input into fetch */
261
memset(&vtx, 0, sizeof(struct r600_bc_vtx));
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/* register containing the index into the buffer */
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vtx.mega_fetch_count = 0x1F;
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vtx.dst_gpr = ctx->shader->input[i].gpr;
274
r = r600_bc_add_vtx(ctx->bc, &vtx);
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case TGSI_FILE_OUTPUT:
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i = ctx->shader->noutput++;
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ctx->shader->output[i].name = d->Semantic.Name;
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ctx->shader->output[i].sid = d->Semantic.Index;
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ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
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ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
286
case TGSI_FILE_CONSTANT:
287
case TGSI_FILE_TEMPORARY:
288
case TGSI_FILE_SAMPLER:
289
case TGSI_FILE_ADDRESS:
292
R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
298
static int r600_get_temp(struct r600_shader_ctx *ctx)
300
return ctx->temp_reg + ctx->max_driver_temp_used++;
303
int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
305
struct tgsi_full_immediate *immediate;
306
struct r600_shader_ctx ctx;
307
struct r600_bc_output output[32];
308
unsigned output_done, noutput;
312
ctx.bc = &shader->bc;
314
r = r600_bc_init(ctx.bc, shader->family);
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ctx.bc->use_mem_constant = shader->use_mem_constant;
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tgsi_scan_shader(tokens, &ctx.info);
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tgsi_parse_init(&ctx.parse, tokens);
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ctx.type = ctx.parse.FullHeader.Processor.Processor;
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shader->processor_type = ctx.type;
324
/* register allocations */
325
/* Values [0,127] correspond to GPR[0..127].
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* Values [128,159] correspond to constant buffer bank 0
327
* Values [160,191] correspond to constant buffer bank 1
328
* Values [256,511] correspond to cfile constants c[0..255].
329
* Other special values are shown in the list below.
330
* 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
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* 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
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* 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
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* 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
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* 248 SQ_ALU_SRC_0: special constant 0.0.
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* 249 SQ_ALU_SRC_1: special constant 1.0 float.
336
* 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
337
* 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
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* 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
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* 253 SQ_ALU_SRC_LITERAL: literal constant.
340
* 254 SQ_ALU_SRC_PV: previous vector result.
341
* 255 SQ_ALU_SRC_PS: previous scalar result.
343
for (i = 0; i < TGSI_FILE_COUNT; i++) {
344
ctx.file_offset[i] = 0;
346
if (ctx.type == TGSI_PROCESSOR_VERTEX) {
347
ctx.file_offset[TGSI_FILE_INPUT] = 1;
349
ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
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ctx.info.file_count[TGSI_FILE_INPUT];
351
ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
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ctx.info.file_count[TGSI_FILE_OUTPUT];
353
if (ctx.shader->use_mem_constant)
354
ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
356
ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
358
ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
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ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
360
ctx.info.file_count[TGSI_FILE_TEMPORARY];
365
while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
366
tgsi_parse_token(&ctx.parse);
367
switch (ctx.parse.FullToken.Token.Type) {
368
case TGSI_TOKEN_TYPE_IMMEDIATE:
369
immediate = &ctx.parse.FullToken.FullImmediate;
370
ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
371
if(ctx.literals == NULL) {
375
ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
376
ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
377
ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
378
ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
381
case TGSI_TOKEN_TYPE_DECLARATION:
382
r = tgsi_declaration(&ctx);
386
case TGSI_TOKEN_TYPE_INSTRUCTION:
387
r = tgsi_is_supported(&ctx);
390
ctx.max_driver_temp_used = 0;
391
/* reserve first tmp for everyone */
393
opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
394
ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
395
r = ctx.inst_info->process(&ctx);
398
r = r600_bc_add_literal(ctx.bc, ctx.value);
403
R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
409
noutput = shader->noutput;
410
for (i = 0, pos0 = 0; i < noutput; i++) {
411
memset(&output[i], 0, sizeof(struct r600_bc_output));
412
output[i].gpr = shader->output[i].gpr;
413
output[i].elem_size = 3;
414
output[i].swizzle_x = 0;
415
output[i].swizzle_y = 1;
416
output[i].swizzle_z = 2;
417
output[i].swizzle_w = 3;
418
output[i].barrier = 1;
419
output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
420
output[i].array_base = i - pos0;
421
output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
423
case TGSI_PROCESSOR_VERTEX:
424
if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
425
output[i].array_base = 60;
426
output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
427
/* position doesn't count in array_base */
430
if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
431
output[i].array_base = 61;
432
output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
433
/* position doesn't count in array_base */
437
case TGSI_PROCESSOR_FRAGMENT:
438
if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
439
output[i].array_base = shader->output[i].sid;
440
output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
441
} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
442
output[i].array_base = 61;
443
output[i].swizzle_x = 2;
444
output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
445
output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
447
R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
453
R600_ERR("unsupported processor type %d\n", ctx.type);
458
/* add fake param output for vertex shader if no param is exported */
459
if (ctx.type == TGSI_PROCESSOR_VERTEX) {
460
for (i = 0, pos0 = 0; i < noutput; i++) {
461
if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
467
memset(&output[i], 0, sizeof(struct r600_bc_output));
469
output[i].elem_size = 3;
470
output[i].swizzle_x = 0;
471
output[i].swizzle_y = 1;
472
output[i].swizzle_z = 2;
473
output[i].swizzle_w = 3;
474
output[i].barrier = 1;
475
output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
476
output[i].array_base = 0;
477
output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
481
/* add fake pixel export */
482
if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
483
memset(&output[0], 0, sizeof(struct r600_bc_output));
485
output[0].elem_size = 3;
486
output[0].swizzle_x = 7;
487
output[0].swizzle_y = 7;
488
output[0].swizzle_z = 7;
489
output[0].swizzle_w = 7;
490
output[0].barrier = 1;
491
output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
492
output[0].array_base = 0;
493
output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
496
/* set export done on last export of each type */
497
for (i = noutput - 1, output_done = 0; i >= 0; i--) {
498
if (i == (noutput - 1)) {
499
output[i].end_of_program = 1;
501
if (!(output_done & (1 << output[i].type))) {
502
output_done |= (1 << output[i].type);
503
output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
506
/* add output to bytecode */
507
for (i = 0; i < noutput; i++) {
508
r = r600_bc_add_output(ctx.bc, &output[i]);
513
tgsi_parse_free(&ctx.parse);
517
tgsi_parse_free(&ctx.parse);
521
static int tgsi_unsupported(struct r600_shader_ctx *ctx)
523
R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
527
static int tgsi_end(struct r600_shader_ctx *ctx)
532
static int tgsi_src(struct r600_shader_ctx *ctx,
533
const struct tgsi_full_src_register *tgsi_src,
534
struct r600_bc_alu_src *r600_src)
537
memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
538
r600_src->sel = tgsi_src->Register.Index;
539
if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
541
index = tgsi_src->Register.Index;
542
ctx->value[0] = ctx->literals[index * 4 + 0];
543
ctx->value[1] = ctx->literals[index * 4 + 1];
544
ctx->value[2] = ctx->literals[index * 4 + 2];
545
ctx->value[3] = ctx->literals[index * 4 + 3];
547
if (tgsi_src->Register.Indirect)
548
r600_src->rel = V_SQ_REL_RELATIVE;
549
r600_src->neg = tgsi_src->Register.Negate;
550
r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
554
static int tgsi_dst(struct r600_shader_ctx *ctx,
555
const struct tgsi_full_dst_register *tgsi_dst,
557
struct r600_bc_alu_dst *r600_dst)
559
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
561
r600_dst->sel = tgsi_dst->Register.Index;
562
r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
563
r600_dst->chan = swizzle;
565
if (tgsi_dst->Register.Indirect)
566
r600_dst->rel = V_SQ_REL_RELATIVE;
567
if (inst->Instruction.Saturate) {
573
static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
577
return tgsi_src->Register.SwizzleX;
579
return tgsi_src->Register.SwizzleY;
581
return tgsi_src->Register.SwizzleZ;
583
return tgsi_src->Register.SwizzleW;
589
static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
591
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
592
struct r600_bc_alu alu;
593
int i, j, k, nconst, r;
595
for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
596
if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
599
r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
604
for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
605
if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
606
int treg = r600_get_temp(ctx);
607
for (k = 0; k < 4; k++) {
608
memset(&alu, 0, sizeof(struct r600_bc_alu));
609
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
610
alu.src[0].sel = r600_src[j].sel;
617
r = r600_bc_add_alu(ctx->bc, &alu);
621
r600_src[j].sel = treg;
628
/* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
629
static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
631
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
632
struct r600_bc_alu alu;
633
int i, j, k, nliteral, r;
635
for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
636
if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
640
for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
641
if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
642
int treg = r600_get_temp(ctx);
643
for (k = 0; k < 4; k++) {
644
memset(&alu, 0, sizeof(struct r600_bc_alu));
645
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
646
alu.src[0].sel = r600_src[j].sel;
653
r = r600_bc_add_alu(ctx->bc, &alu);
657
r = r600_bc_add_literal(ctx->bc, ctx->value);
660
r600_src[j].sel = treg;
667
static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
669
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
670
struct r600_bc_alu_src r600_src[3];
671
struct r600_bc_alu alu;
675
for (i = 0; i < 4; i++) {
676
if (inst->Dst[0].Register.WriteMask & (1 << i)) {
681
r = tgsi_split_constant(ctx, r600_src);
684
for (i = 0; i < lasti + 1; i++) {
685
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
688
memset(&alu, 0, sizeof(struct r600_bc_alu));
689
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
693
alu.inst = ctx->inst_info->r600_opcode;
695
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
696
alu.src[j] = r600_src[j];
697
alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
700
alu.src[0] = r600_src[1];
701
alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
703
alu.src[1] = r600_src[0];
704
alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
706
/* handle some special cases */
707
switch (ctx->inst_info->tgsi_opcode) {
708
case TGSI_OPCODE_SUB:
711
case TGSI_OPCODE_ABS:
720
r = r600_bc_add_alu(ctx->bc, &alu);
727
static int tgsi_op2(struct r600_shader_ctx *ctx)
729
return tgsi_op2_s(ctx, 0);
732
static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
734
return tgsi_op2_s(ctx, 1);
738
* r600 - trunc to -PI..PI range
739
* r700 - normalize by dividing by 2PI
742
static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
743
struct r600_bc_alu_src r600_src[3])
745
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
747
uint32_t lit_vals[4];
748
struct r600_bc_alu alu;
750
memset(lit_vals, 0, 4*4);
751
r = tgsi_split_constant(ctx, r600_src);
755
r = tgsi_split_literal_constant(ctx, r600_src);
759
lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
760
lit_vals[1] = fui(0.5f);
762
memset(&alu, 0, sizeof(struct r600_bc_alu));
763
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
767
alu.dst.sel = ctx->temp_reg;
770
alu.src[0] = r600_src[0];
771
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
773
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
775
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
778
r = r600_bc_add_alu(ctx->bc, &alu);
781
r = r600_bc_add_literal(ctx->bc, lit_vals);
785
memset(&alu, 0, sizeof(struct r600_bc_alu));
786
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
789
alu.dst.sel = ctx->temp_reg;
792
alu.src[0].sel = ctx->temp_reg;
795
r = r600_bc_add_alu(ctx->bc, &alu);
799
if (ctx->bc->chiprev == 0) {
800
lit_vals[0] = fui(3.1415926535897f * 2.0f);
801
lit_vals[1] = fui(-3.1415926535897f);
803
lit_vals[0] = fui(1.0f);
804
lit_vals[1] = fui(-0.5f);
807
memset(&alu, 0, sizeof(struct r600_bc_alu));
808
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
812
alu.dst.sel = ctx->temp_reg;
815
alu.src[0].sel = ctx->temp_reg;
818
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
820
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
823
r = r600_bc_add_alu(ctx->bc, &alu);
826
r = r600_bc_add_literal(ctx->bc, lit_vals);
832
static int tgsi_trig(struct r600_shader_ctx *ctx)
834
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
835
struct r600_bc_alu_src r600_src[3];
836
struct r600_bc_alu alu;
840
r = tgsi_setup_trig(ctx, r600_src);
844
memset(&alu, 0, sizeof(struct r600_bc_alu));
845
alu.inst = ctx->inst_info->r600_opcode;
847
alu.dst.sel = ctx->temp_reg;
850
alu.src[0].sel = ctx->temp_reg;
853
r = r600_bc_add_alu(ctx->bc, &alu);
857
/* replicate result */
858
for (i = 0; i < 4; i++) {
859
if (inst->Dst[0].Register.WriteMask & (1 << i))
862
for (i = 0; i < lasti + 1; i++) {
863
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
866
memset(&alu, 0, sizeof(struct r600_bc_alu));
867
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
869
alu.src[0].sel = ctx->temp_reg;
870
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
875
r = r600_bc_add_alu(ctx->bc, &alu);
882
static int tgsi_scs(struct r600_shader_ctx *ctx)
884
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
885
struct r600_bc_alu_src r600_src[3];
886
struct r600_bc_alu alu;
889
r = tgsi_setup_trig(ctx, r600_src);
895
memset(&alu, 0, sizeof(struct r600_bc_alu));
896
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
897
r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
901
alu.src[0].sel = ctx->temp_reg;
904
r = r600_bc_add_alu(ctx->bc, &alu);
909
memset(&alu, 0, sizeof(struct r600_bc_alu));
910
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
911
r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
915
alu.src[0].sel = ctx->temp_reg;
918
r = r600_bc_add_alu(ctx->bc, &alu);
924
static int tgsi_kill(struct r600_shader_ctx *ctx)
926
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
927
struct r600_bc_alu alu;
930
for (i = 0; i < 4; i++) {
931
memset(&alu, 0, sizeof(struct r600_bc_alu));
932
alu.inst = ctx->inst_info->r600_opcode;
936
alu.src[0].sel = V_SQ_ALU_SRC_0;
938
if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
939
alu.src[1].sel = V_SQ_ALU_SRC_1;
942
r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
945
alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
950
r = r600_bc_add_alu(ctx->bc, &alu);
954
r = r600_bc_add_literal(ctx->bc, ctx->value);
958
/* kill must be last in ALU */
959
ctx->bc->force_add_cf = 1;
960
ctx->shader->uses_kill = TRUE;
964
static int tgsi_lit(struct r600_shader_ctx *ctx)
966
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
967
struct r600_bc_alu alu;
968
struct r600_bc_alu_src r600_src[3];
971
r = tgsi_split_constant(ctx, r600_src);
974
r = tgsi_split_literal_constant(ctx, r600_src);
979
memset(&alu, 0, sizeof(struct r600_bc_alu));
980
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
981
alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
983
r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
986
alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
987
r = r600_bc_add_alu(ctx->bc, &alu);
991
/* dst.y = max(src.x, 0.0) */
992
memset(&alu, 0, sizeof(struct r600_bc_alu));
993
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
994
alu.src[0] = r600_src[0];
995
alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
997
r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1000
alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1001
r = r600_bc_add_alu(ctx->bc, &alu);
1006
memset(&alu, 0, sizeof(struct r600_bc_alu));
1007
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1008
alu.src[0].sel = V_SQ_ALU_SRC_1;
1009
alu.src[0].chan = 0;
1010
r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1013
alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1015
r = r600_bc_add_alu(ctx->bc, &alu);
1019
r = r600_bc_add_literal(ctx->bc, ctx->value);
1023
if (inst->Dst[0].Register.WriteMask & (1 << 2))
1028
/* dst.z = log(src.y) */
1029
memset(&alu, 0, sizeof(struct r600_bc_alu));
1030
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1031
alu.src[0] = r600_src[0];
1032
alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1033
r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1037
r = r600_bc_add_alu(ctx->bc, &alu);
1041
r = r600_bc_add_literal(ctx->bc, ctx->value);
1045
chan = alu.dst.chan;
1048
/* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1049
memset(&alu, 0, sizeof(struct r600_bc_alu));
1050
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1051
alu.src[0] = r600_src[0];
1052
alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1053
alu.src[1].sel = sel;
1054
alu.src[1].chan = chan;
1056
alu.src[2] = r600_src[0];
1057
alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1058
alu.dst.sel = ctx->temp_reg;
1063
r = r600_bc_add_alu(ctx->bc, &alu);
1067
r = r600_bc_add_literal(ctx->bc, ctx->value);
1070
/* dst.z = exp(tmp.x) */
1071
memset(&alu, 0, sizeof(struct r600_bc_alu));
1072
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1073
alu.src[0].sel = ctx->temp_reg;
1074
alu.src[0].chan = 0;
1075
r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1079
r = r600_bc_add_alu(ctx->bc, &alu);
1086
static int tgsi_rsq(struct r600_shader_ctx *ctx)
1088
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1089
struct r600_bc_alu alu;
1092
memset(&alu, 0, sizeof(struct r600_bc_alu));
1093
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE);
1094
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1095
r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1098
alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1101
alu.dst.sel = ctx->temp_reg;
1104
r = r600_bc_add_alu(ctx->bc, &alu);
1107
r = r600_bc_add_literal(ctx->bc, ctx->value);
1110
/* replicate result */
1111
return tgsi_helper_tempx_replicate(ctx);
1114
static int tgsi_trans(struct r600_shader_ctx *ctx)
1116
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1117
struct r600_bc_alu alu;
1120
for (i = 0; i < 4; i++) {
1121
memset(&alu, 0, sizeof(struct r600_bc_alu));
1122
if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1123
alu.inst = ctx->inst_info->r600_opcode;
1124
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1125
r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
1128
alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1130
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1134
r = r600_bc_add_alu(ctx->bc, &alu);
1142
static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1144
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1145
struct r600_bc_alu alu;
1148
for (i = 0; i < 4; i++) {
1149
memset(&alu, 0, sizeof(struct r600_bc_alu));
1150
alu.src[0].sel = ctx->temp_reg;
1151
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1153
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1156
alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1159
r = r600_bc_add_alu(ctx->bc, &alu);
1166
static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1168
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1169
struct r600_bc_alu alu;
1172
memset(&alu, 0, sizeof(struct r600_bc_alu));
1173
alu.inst = ctx->inst_info->r600_opcode;
1174
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1175
r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1178
alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1180
alu.dst.sel = ctx->temp_reg;
1183
r = r600_bc_add_alu(ctx->bc, &alu);
1186
r = r600_bc_add_literal(ctx->bc, ctx->value);
1189
/* replicate result */
1190
return tgsi_helper_tempx_replicate(ctx);
1193
static int tgsi_pow(struct r600_shader_ctx *ctx)
1195
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1196
struct r600_bc_alu alu;
1200
memset(&alu, 0, sizeof(struct r600_bc_alu));
1201
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1202
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1205
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1206
alu.dst.sel = ctx->temp_reg;
1209
r = r600_bc_add_alu(ctx->bc, &alu);
1212
r = r600_bc_add_literal(ctx->bc,ctx->value);
1216
memset(&alu, 0, sizeof(struct r600_bc_alu));
1217
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1218
r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1221
alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1222
alu.src[1].sel = ctx->temp_reg;
1223
alu.dst.sel = ctx->temp_reg;
1226
r = r600_bc_add_alu(ctx->bc, &alu);
1229
r = r600_bc_add_literal(ctx->bc,ctx->value);
1232
/* POW(a,b) = EXP2(b * LOG2(a))*/
1233
memset(&alu, 0, sizeof(struct r600_bc_alu));
1234
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1235
alu.src[0].sel = ctx->temp_reg;
1236
alu.dst.sel = ctx->temp_reg;
1239
r = r600_bc_add_alu(ctx->bc, &alu);
1242
r = r600_bc_add_literal(ctx->bc,ctx->value);
1245
return tgsi_helper_tempx_replicate(ctx);
1248
static int tgsi_ssg(struct r600_shader_ctx *ctx)
1250
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1251
struct r600_bc_alu alu;
1252
struct r600_bc_alu_src r600_src[3];
1255
r = tgsi_split_constant(ctx, r600_src);
1259
/* tmp = (src > 0 ? 1 : src) */
1260
for (i = 0; i < 4; i++) {
1261
memset(&alu, 0, sizeof(struct r600_bc_alu));
1262
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1265
alu.dst.sel = ctx->temp_reg;
1268
alu.src[0] = r600_src[0];
1269
alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1271
alu.src[1].sel = V_SQ_ALU_SRC_1;
1273
alu.src[2] = r600_src[0];
1274
alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1277
r = r600_bc_add_alu(ctx->bc, &alu);
1281
r = r600_bc_add_literal(ctx->bc, ctx->value);
1285
/* dst = (-tmp > 0 ? -1 : tmp) */
1286
for (i = 0; i < 4; i++) {
1287
memset(&alu, 0, sizeof(struct r600_bc_alu));
1288
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1290
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1294
alu.src[0].sel = ctx->temp_reg;
1295
alu.src[0].chan = i;
1298
alu.src[1].sel = V_SQ_ALU_SRC_1;
1301
alu.src[2].sel = ctx->temp_reg;
1302
alu.src[2].chan = i;
1306
r = r600_bc_add_alu(ctx->bc, &alu);
1313
static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1315
struct r600_bc_alu alu;
1318
r = r600_bc_add_literal(ctx->bc, ctx->value);
1321
for (i = 0; i < 4; i++) {
1322
memset(&alu, 0, sizeof(struct r600_bc_alu));
1323
if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1324
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1327
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1328
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1331
alu.src[0].sel = ctx->temp_reg;
1332
alu.src[0].chan = i;
1337
r = r600_bc_add_alu(ctx->bc, &alu);
1344
static int tgsi_op3(struct r600_shader_ctx *ctx)
1346
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1347
struct r600_bc_alu_src r600_src[3];
1348
struct r600_bc_alu alu;
1351
r = tgsi_split_constant(ctx, r600_src);
1354
/* do it in 2 step as op3 doesn't support writemask */
1355
for (i = 0; i < 4; i++) {
1356
memset(&alu, 0, sizeof(struct r600_bc_alu));
1357
alu.inst = ctx->inst_info->r600_opcode;
1358
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1359
alu.src[j] = r600_src[j];
1360
alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1362
alu.dst.sel = ctx->temp_reg;
1369
r = r600_bc_add_alu(ctx->bc, &alu);
1373
return tgsi_helper_copy(ctx, inst);
1376
static int tgsi_dp(struct r600_shader_ctx *ctx)
1378
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1379
struct r600_bc_alu_src r600_src[3];
1380
struct r600_bc_alu alu;
1383
r = tgsi_split_constant(ctx, r600_src);
1386
for (i = 0; i < 4; i++) {
1387
memset(&alu, 0, sizeof(struct r600_bc_alu));
1388
alu.inst = ctx->inst_info->r600_opcode;
1389
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1390
alu.src[j] = r600_src[j];
1391
alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1393
alu.dst.sel = ctx->temp_reg;
1396
/* handle some special cases */
1397
switch (ctx->inst_info->tgsi_opcode) {
1398
case TGSI_OPCODE_DP2:
1400
alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1401
alu.src[0].chan = alu.src[1].chan = 0;
1404
case TGSI_OPCODE_DP3:
1406
alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1407
alu.src[0].chan = alu.src[1].chan = 0;
1410
case TGSI_OPCODE_DPH:
1412
alu.src[0].sel = V_SQ_ALU_SRC_1;
1413
alu.src[0].chan = 0;
1423
r = r600_bc_add_alu(ctx->bc, &alu);
1427
return tgsi_helper_copy(ctx, inst);
1430
static int tgsi_tex(struct r600_shader_ctx *ctx)
1432
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1433
struct r600_bc_tex tex;
1434
struct r600_bc_alu alu;
1438
boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1439
uint32_t lit_vals[4];
1441
src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1443
if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1444
/* Add perspective divide */
1445
memset(&alu, 0, sizeof(struct r600_bc_alu));
1446
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1447
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1451
alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1452
alu.dst.sel = ctx->temp_reg;
1456
r = r600_bc_add_alu(ctx->bc, &alu);
1460
for (i = 0; i < 3; i++) {
1461
memset(&alu, 0, sizeof(struct r600_bc_alu));
1462
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1463
alu.src[0].sel = ctx->temp_reg;
1464
alu.src[0].chan = 3;
1465
r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1468
alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1469
alu.dst.sel = ctx->temp_reg;
1472
r = r600_bc_add_alu(ctx->bc, &alu);
1476
memset(&alu, 0, sizeof(struct r600_bc_alu));
1477
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1478
alu.src[0].sel = V_SQ_ALU_SRC_1;
1479
alu.src[0].chan = 0;
1480
alu.dst.sel = ctx->temp_reg;
1484
r = r600_bc_add_alu(ctx->bc, &alu);
1487
src_not_temp = false;
1488
src_gpr = ctx->temp_reg;
1491
if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1492
int src_chan, src2_chan;
1494
/* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1495
for (i = 0; i < 4; i++) {
1496
memset(&alu, 0, sizeof(struct r600_bc_alu));
1497
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1516
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1519
alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1520
r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1523
alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1524
alu.dst.sel = ctx->temp_reg;
1529
r = r600_bc_add_alu(ctx->bc, &alu);
1534
/* tmp1.z = RCP_e(|tmp1.z|) */
1535
memset(&alu, 0, sizeof(struct r600_bc_alu));
1536
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1537
alu.src[0].sel = ctx->temp_reg;
1538
alu.src[0].chan = 2;
1540
alu.dst.sel = ctx->temp_reg;
1544
r = r600_bc_add_alu(ctx->bc, &alu);
1548
/* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1549
* MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1550
* muladd has no writemask, have to use another temp
1552
memset(&alu, 0, sizeof(struct r600_bc_alu));
1553
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1556
alu.src[0].sel = ctx->temp_reg;
1557
alu.src[0].chan = 0;
1558
alu.src[1].sel = ctx->temp_reg;
1559
alu.src[1].chan = 2;
1561
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1562
alu.src[2].chan = 0;
1564
alu.dst.sel = ctx->temp_reg;
1568
r = r600_bc_add_alu(ctx->bc, &alu);
1572
memset(&alu, 0, sizeof(struct r600_bc_alu));
1573
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1576
alu.src[0].sel = ctx->temp_reg;
1577
alu.src[0].chan = 1;
1578
alu.src[1].sel = ctx->temp_reg;
1579
alu.src[1].chan = 2;
1581
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1582
alu.src[2].chan = 0;
1584
alu.dst.sel = ctx->temp_reg;
1589
r = r600_bc_add_alu(ctx->bc, &alu);
1593
lit_vals[0] = fui(1.5f);
1595
r = r600_bc_add_literal(ctx->bc, lit_vals);
1598
src_not_temp = false;
1599
src_gpr = ctx->temp_reg;
1603
for (i = 0; i < 4; i++) {
1604
memset(&alu, 0, sizeof(struct r600_bc_alu));
1605
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1606
alu.src[0].sel = src_gpr;
1607
alu.src[0].chan = i;
1608
alu.dst.sel = ctx->temp_reg;
1613
r = r600_bc_add_alu(ctx->bc, &alu);
1617
src_gpr = ctx->temp_reg;
1620
opcode = ctx->inst_info->r600_opcode;
1621
if (opcode == SQ_TEX_INST_SAMPLE &&
1622
(inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1623
opcode = SQ_TEX_INST_SAMPLE_C;
1625
memset(&tex, 0, sizeof(struct r600_bc_tex));
1627
tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1628
tex.sampler_id = tex.resource_id;
1629
tex.src_gpr = src_gpr;
1630
tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1640
if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1647
if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1648
tex.coord_type_x = 1;
1649
tex.coord_type_y = 1;
1650
tex.coord_type_z = 1;
1651
tex.coord_type_w = 1;
1654
if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1657
r = r600_bc_add_tex(ctx->bc, &tex);
1661
/* add shadow ambient support - gallium doesn't do it yet */
1666
static int tgsi_lrp(struct r600_shader_ctx *ctx)
1668
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1669
struct r600_bc_alu_src r600_src[3];
1670
struct r600_bc_alu alu;
1674
r = tgsi_split_constant(ctx, r600_src);
1678
for (i = 0; i < 4; i++) {
1679
memset(&alu, 0, sizeof(struct r600_bc_alu));
1680
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1681
alu.src[0].sel = V_SQ_ALU_SRC_1;
1682
alu.src[0].chan = 0;
1683
alu.src[1] = r600_src[0];
1684
alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1686
alu.dst.sel = ctx->temp_reg;
1692
r = r600_bc_add_alu(ctx->bc, &alu);
1696
r = r600_bc_add_literal(ctx->bc, ctx->value);
1700
/* (1 - src0) * src2 */
1701
for (i = 0; i < 4; i++) {
1702
memset(&alu, 0, sizeof(struct r600_bc_alu));
1703
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1704
alu.src[0].sel = ctx->temp_reg;
1705
alu.src[0].chan = i;
1706
alu.src[1] = r600_src[2];
1707
alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1708
alu.dst.sel = ctx->temp_reg;
1714
r = r600_bc_add_alu(ctx->bc, &alu);
1718
r = r600_bc_add_literal(ctx->bc, ctx->value);
1722
/* src0 * src1 + (1 - src0) * src2 */
1723
for (i = 0; i < 4; i++) {
1724
memset(&alu, 0, sizeof(struct r600_bc_alu));
1725
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1727
alu.src[0] = r600_src[0];
1728
alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1729
alu.src[1] = r600_src[1];
1730
alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1731
alu.src[2].sel = ctx->temp_reg;
1732
alu.src[2].chan = i;
1733
alu.dst.sel = ctx->temp_reg;
1738
r = r600_bc_add_alu(ctx->bc, &alu);
1742
return tgsi_helper_copy(ctx, inst);
1745
static int tgsi_cmp(struct r600_shader_ctx *ctx)
1747
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1748
struct r600_bc_alu_src r600_src[3];
1749
struct r600_bc_alu alu;
1753
r = tgsi_split_constant(ctx, r600_src);
1757
if (inst->Dst[0].Register.WriteMask != 0xf)
1760
for (i = 0; i < 4; i++) {
1761
memset(&alu, 0, sizeof(struct r600_bc_alu));
1762
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1763
alu.src[0] = r600_src[0];
1764
alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1766
alu.src[1] = r600_src[2];
1767
alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1769
alu.src[2] = r600_src[1];
1770
alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1773
alu.dst.sel = ctx->temp_reg;
1775
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1784
r = r600_bc_add_alu(ctx->bc, &alu);
1789
return tgsi_helper_copy(ctx, inst);
1793
static int tgsi_xpd(struct r600_shader_ctx *ctx)
1795
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1796
struct r600_bc_alu_src r600_src[3];
1797
struct r600_bc_alu alu;
1798
uint32_t use_temp = 0;
1801
if (inst->Dst[0].Register.WriteMask != 0xf)
1804
r = tgsi_split_constant(ctx, r600_src);
1808
for (i = 0; i < 4; i++) {
1809
memset(&alu, 0, sizeof(struct r600_bc_alu));
1810
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1812
alu.src[0] = r600_src[0];
1815
alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1818
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1821
alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1824
alu.src[0].sel = V_SQ_ALU_SRC_0;
1825
alu.src[0].chan = i;
1828
alu.src[1] = r600_src[1];
1831
alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1834
alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1837
alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1840
alu.src[1].sel = V_SQ_ALU_SRC_0;
1841
alu.src[1].chan = i;
1844
alu.dst.sel = ctx->temp_reg;
1850
r = r600_bc_add_alu(ctx->bc, &alu);
1854
r = r600_bc_add_literal(ctx->bc, ctx->value);
1859
for (i = 0; i < 4; i++) {
1860
memset(&alu, 0, sizeof(struct r600_bc_alu));
1861
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1863
alu.src[0] = r600_src[0];
1866
alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1869
alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1872
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1875
alu.src[0].sel = V_SQ_ALU_SRC_0;
1876
alu.src[0].chan = i;
1879
alu.src[1] = r600_src[1];
1882
alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1885
alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1888
alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1891
alu.src[1].sel = V_SQ_ALU_SRC_0;
1892
alu.src[1].chan = i;
1895
alu.src[2].sel = ctx->temp_reg;
1897
alu.src[2].chan = i;
1900
alu.dst.sel = ctx->temp_reg;
1902
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1911
r = r600_bc_add_alu(ctx->bc, &alu);
1915
r = r600_bc_add_literal(ctx->bc, ctx->value);
1920
return tgsi_helper_copy(ctx, inst);
1924
static int tgsi_exp(struct r600_shader_ctx *ctx)
1926
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1927
struct r600_bc_alu_src r600_src[3];
1928
struct r600_bc_alu alu;
1931
/* result.x = 2^floor(src); */
1932
if (inst->Dst[0].Register.WriteMask & 1) {
1933
memset(&alu, 0, sizeof(struct r600_bc_alu));
1935
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
1936
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1940
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1942
alu.dst.sel = ctx->temp_reg;
1946
r = r600_bc_add_alu(ctx->bc, &alu);
1950
r = r600_bc_add_literal(ctx->bc, ctx->value);
1954
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1955
alu.src[0].sel = ctx->temp_reg;
1956
alu.src[0].chan = 0;
1958
alu.dst.sel = ctx->temp_reg;
1962
r = r600_bc_add_alu(ctx->bc, &alu);
1966
r = r600_bc_add_literal(ctx->bc, ctx->value);
1971
/* result.y = tmp - floor(tmp); */
1972
if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
1973
memset(&alu, 0, sizeof(struct r600_bc_alu));
1975
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1976
alu.src[0] = r600_src[0];
1977
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1980
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1982
alu.dst.sel = ctx->temp_reg;
1983
// r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1991
r = r600_bc_add_alu(ctx->bc, &alu);
1994
r = r600_bc_add_literal(ctx->bc, ctx->value);
1999
/* result.z = RoughApprox2ToX(tmp);*/
2000
if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2001
memset(&alu, 0, sizeof(struct r600_bc_alu));
2002
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2003
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2006
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2008
alu.dst.sel = ctx->temp_reg;
2014
r = r600_bc_add_alu(ctx->bc, &alu);
2017
r = r600_bc_add_literal(ctx->bc, ctx->value);
2022
/* result.w = 1.0;*/
2023
if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2024
memset(&alu, 0, sizeof(struct r600_bc_alu));
2026
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2027
alu.src[0].sel = V_SQ_ALU_SRC_1;
2028
alu.src[0].chan = 0;
2030
alu.dst.sel = ctx->temp_reg;
2034
r = r600_bc_add_alu(ctx->bc, &alu);
2037
r = r600_bc_add_literal(ctx->bc, ctx->value);
2041
return tgsi_helper_copy(ctx, inst);
2044
static int tgsi_log(struct r600_shader_ctx *ctx)
2046
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2047
struct r600_bc_alu_src r600_src[3];
2048
struct r600_bc_alu alu;
2051
/* result.x = floor(log2(src)); */
2052
if (inst->Dst[0].Register.WriteMask & 1) {
2053
memset(&alu, 0, sizeof(struct r600_bc_alu));
2055
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2056
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2060
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2062
alu.dst.sel = ctx->temp_reg;
2066
r = r600_bc_add_alu(ctx->bc, &alu);
2070
r = r600_bc_add_literal(ctx->bc, ctx->value);
2074
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2075
alu.src[0].sel = ctx->temp_reg;
2076
alu.src[0].chan = 0;
2078
alu.dst.sel = ctx->temp_reg;
2083
r = r600_bc_add_alu(ctx->bc, &alu);
2087
r = r600_bc_add_literal(ctx->bc, ctx->value);
2092
/* result.y = FIXME; */
2093
if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2094
memset(&alu, 0, sizeof(struct r600_bc_alu));
2096
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2097
alu.src[0].sel = V_SQ_ALU_SRC_1;
2098
alu.src[0].chan = 0;
2100
alu.dst.sel = ctx->temp_reg;
2105
r = r600_bc_add_alu(ctx->bc, &alu);
2109
r = r600_bc_add_literal(ctx->bc, ctx->value);
2114
/* result.z = log2(src);*/
2115
if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2116
memset(&alu, 0, sizeof(struct r600_bc_alu));
2118
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2119
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2123
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2125
alu.dst.sel = ctx->temp_reg;
2130
r = r600_bc_add_alu(ctx->bc, &alu);
2134
r = r600_bc_add_literal(ctx->bc, ctx->value);
2139
/* result.w = 1.0; */
2140
if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2141
memset(&alu, 0, sizeof(struct r600_bc_alu));
2143
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2144
alu.src[0].sel = V_SQ_ALU_SRC_1;
2145
alu.src[0].chan = 0;
2147
alu.dst.sel = ctx->temp_reg;
2152
r = r600_bc_add_alu(ctx->bc, &alu);
2156
r = r600_bc_add_literal(ctx->bc, ctx->value);
2161
return tgsi_helper_copy(ctx, inst);
2164
static int tgsi_arl(struct r600_shader_ctx *ctx)
2166
/* TODO from r600c, ar values don't persist between clauses */
2167
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2168
struct r600_bc_alu alu;
2170
memset(&alu, 0, sizeof(struct r600_bc_alu));
2172
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2174
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2177
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2181
r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2187
static int tgsi_opdst(struct r600_shader_ctx *ctx)
2189
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2190
struct r600_bc_alu alu;
2193
for (i = 0; i < 4; i++) {
2194
memset(&alu, 0, sizeof(struct r600_bc_alu));
2196
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2197
r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2201
if (i == 0 || i == 3) {
2202
alu.src[0].sel = V_SQ_ALU_SRC_1;
2204
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2207
alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2210
if (i == 0 || i == 2) {
2211
alu.src[1].sel = V_SQ_ALU_SRC_1;
2213
r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2216
alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2220
r = r600_bc_add_alu(ctx->bc, &alu);
2227
static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2229
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2230
struct r600_bc_alu alu;
2233
memset(&alu, 0, sizeof(struct r600_bc_alu));
2237
alu.dst.sel = ctx->temp_reg;
2241
r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2244
alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2245
alu.src[1].sel = V_SQ_ALU_SRC_0;
2246
alu.src[1].chan = 0;
2250
r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2256
static int pops(struct r600_shader_ctx *ctx, int pops)
2258
r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2259
ctx->bc->cf_last->pop_count = pops;
2263
static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2267
ctx->bc->callstack[ctx->bc->call_sp].current--;
2271
ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2274
/* TOODO : for 16 vp asic should -= 2; */
2275
ctx->bc->callstack[ctx->bc->call_sp].current --;
2280
static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2282
if (check_max_only) {
2292
if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2293
ctx->bc->callstack[ctx->bc->call_sp].max) {
2294
ctx->bc->callstack[ctx->bc->call_sp].max =
2295
ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2301
ctx->bc->callstack[ctx->bc->call_sp].current++;
2305
ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2308
ctx->bc->callstack[ctx->bc->call_sp].current++;
2312
if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2313
ctx->bc->callstack[ctx->bc->call_sp].max) {
2314
ctx->bc->callstack[ctx->bc->call_sp].max =
2315
ctx->bc->callstack[ctx->bc->call_sp].current;
2319
static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2321
struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2323
sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2324
sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2325
sp->mid[sp->num_mid] = ctx->bc->cf_last;
2329
static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2332
ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2333
ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2336
static void fc_poplevel(struct r600_shader_ctx *ctx)
2338
struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2350
static int emit_return(struct r600_shader_ctx *ctx)
2352
r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2356
static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2359
r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2360
ctx->bc->cf_last->pop_count = pops;
2361
/* TODO work out offset */
2365
static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2370
static void emit_testflag(struct r600_shader_ctx *ctx)
2375
static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2378
emit_jump_to_offset(ctx, 1, 4);
2379
emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2380
pops(ctx, ifidx + 1);
2384
static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2388
r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2389
ctx->bc->cf_last->pop_count = 1;
2391
fc_set_mid(ctx, fc_sp);
2397
static int tgsi_if(struct r600_shader_ctx *ctx)
2399
emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2401
r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2403
fc_pushlevel(ctx, FC_IF);
2405
callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2409
static int tgsi_else(struct r600_shader_ctx *ctx)
2411
r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2412
ctx->bc->cf_last->pop_count = 1;
2414
fc_set_mid(ctx, ctx->bc->fc_sp);
2415
ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2419
static int tgsi_endif(struct r600_shader_ctx *ctx)
2422
if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2423
R600_ERR("if/endif unbalanced in shader\n");
2427
if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2428
ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2429
ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2431
ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2435
callstack_decrease_current(ctx, FC_PUSH_VPM);
2439
static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2441
r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2443
fc_pushlevel(ctx, FC_LOOP);
2445
/* check stack depth */
2446
callstack_check_depth(ctx, FC_LOOP, 0);
2450
static int tgsi_endloop(struct r600_shader_ctx *ctx)
2454
r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2456
if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2457
R600_ERR("loop/endloop in shader code are not paired.\n");
2461
/* fixup loop pointers - from r600isa
2462
LOOP END points to CF after LOOP START,
2463
LOOP START point to CF after LOOP END
2464
BRK/CONT point to LOOP END CF
2466
ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2468
ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2470
for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2471
ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2473
/* TODO add LOOPRET support */
2475
callstack_decrease_current(ctx, FC_LOOP);
2479
static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2483
for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2485
if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2490
R600_ERR("Break not inside loop/endloop pair\n");
2494
r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2495
ctx->bc->cf_last->pop_count = 1;
2497
fc_set_mid(ctx, fscp);
2500
callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2504
static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2505
{TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2506
{TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2507
{TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2508
{TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2509
{TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2510
{TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2511
{TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2512
{TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2513
{TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2514
{TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2515
{TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2516
{TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2517
{TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2518
{TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2519
{TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2520
{TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2521
{TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2522
{TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2523
{TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2524
{TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2526
{20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2527
{TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2529
{22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2530
{23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2531
{TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2532
{TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2533
{TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2534
{TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2535
{TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2536
{TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2537
{TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2538
{TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2540
{32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2541
{TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2542
{TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2543
{TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2544
{TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2545
{TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2546
{TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2547
{TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2548
{TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2549
{TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2550
{TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2551
{TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2552
{TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2553
{TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2554
{TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2555
{TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2556
{TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2557
{TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2558
{TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2559
{TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2560
{TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2561
{TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2562
{TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2563
{TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2564
{TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2565
{TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2566
{TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2567
{TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2568
{TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2569
{TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2570
{TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2571
{TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2572
{TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2573
{TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2574
{TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2575
{TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2576
{TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2577
{TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2578
{TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2579
{TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2580
{TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2581
{TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2582
{TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2584
{75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2585
{76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2586
{TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2587
{TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2589
{79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2590
{80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2591
{TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2592
{TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2593
{TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2594
{TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2595
{TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2596
{TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2597
{TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2599
{88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2600
{TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2601
{TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2602
{TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2603
{TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2604
{TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2605
{TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2606
{TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2607
{TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2608
{TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2609
{TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2610
{TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2611
{TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2612
{TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2613
{TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2615
{103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2616
{104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2617
{105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2618
{106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2619
{TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2621
{108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2622
{109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2623
{110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2624
{111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2625
{TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2626
{TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2627
{TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2628
{TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2629
{TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2630
{TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2632
{118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2633
{TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2634
{TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2635
{TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2636
{TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2637
{TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2638
{TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2639
{TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2640
{TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2641
{TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2642
{TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2643
{TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2644
{TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2645
{TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2646
{TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2647
{TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2648
{TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2649
{TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2650
{TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2651
{TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2652
{TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2653
{TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2654
{TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2655
{TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2656
{TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2657
{TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2658
{TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2659
{TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
added
removed
src/gallium/drivers/r600/r600_shader.c
