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Viewing changes to src/gallium/drivers/r600/r600_blit.c

  • Committer: Bazaar Package Importer
  • Author(s): Robert Hooker, Robert Hooker, Christopher James Halse Rogers
  • Date: 2010-09-14 08:55:40 UTC
  • mfrom: (1.2.28 upstream)
  • Revision ID: james.westby@ubuntu.com-20100914085540-m4fpl0hdjlfd4jgz
Tags: 7.9~git20100909-0ubuntu1
https://launchpad.net/bugs/631413
https://launchpad.net/bugs/628930
https://launchpad.net/bugs/628727
https://launchpad.net/bugs/596292
https://launchpad.net/bugs/599741
https://launchpad.net/bugs/630315
https://launchpad.net/bugs/613694
https://launchpad.net/bugs/599741
https://launchpad.net/bugs/578619
https://launchpad.net/bugs/626943
https://launchpad.net/bugs/610541
https://launchpad.net/bugs/601052
[ Robert Hooker ]
* New upstream git snapshot up to commit 94118fe2d4b1e5 (LP: #631413)
* New features include ATI HD5xxx series support in r600, and a vastly
  improved glsl compiler.
* Remove pre-generated .pc's, use the ones generated at build time
  instead.
* Remove all references to mesa-utils now that its no longer shipped
  with the mesa source.
* Disable the experimental ARB_fragment_shader option by default on
  i915, it exposes incomplete functionality that breaks KDE compositing
  among other things. It can be enabled via driconf still. (LP: #628930).

[ Christopher James Halse Rogers ]
* debian/patches/04_osmesa_version.diff:
  - Refresh for new upstream
* Bugs fixed in this release:
  - Fixes severe rendering corruption in Unity on radeon (LP: #628727,
    LP: #596292, LP: #599741, LP: #630315, LP: #613694, LP: #599741).
  - Also fixes rendering in gnome-shell (LP: #578619).
  - Flickering in OpenGL apps on radeon (LP: #626943, LP: #610541).
  - Provides preliminary support for new intel chips (LP: #601052).
* debian/rules:
  - Update configure flags to match upstream reshuffling.
  - Explicitly remove gallium DRI drivers that we don't want to ship.
* Update debian/gbp.conf for this Maverick-specific packaging
* libegl1-mesa-dri-x11,kms: There are no longer separate kms or x11 drivers
  for EGL, libegl1-mesa-drivers now contains a single driver that provides
  both backends.

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src/gallium/drivers/r600/r600_blit.c
 
1
/*
 
2
 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
 
3
 *
 
4
 * Permission is hereby granted, free of charge, to any person obtaining a
 
5
 * copy of this software and associated documentation files (the "Software"),
 
6
 * to deal in the Software without restriction, including without limitation
 
7
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 
8
 * license, and/or sell copies of the Software, and to permit persons to whom
 
9
 * the Software is furnished to do so, subject to the following conditions:
 
10
 *
 
11
 * The above copyright notice and this permission notice (including the next
 
12
 * paragraph) shall be included in all copies or substantial portions of the
 
13
 * Software.
 
14
 *
 
15
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 
16
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 
17
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 
18
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
 
19
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 
20
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 
21
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 
22
 *
 
23
 * Authors:
 
24
 *      Jerome Glisse
 
25
 *      Marek Olšák
 
26
 */
 
27
#include <errno.h>
 
28
#include <pipe/p_screen.h>
 
29
#include <util/u_blitter.h>
 
30
#include <util/u_inlines.h>
 
31
#include <util/u_memory.h>
 
32
#include "util/u_surface.h"
 
33
#include "r600_screen.h"
 
34
#include "r600_context.h"
 
35
#include "r600d.h"
 
36
 
 
37
static void r600_blitter_save_states(struct pipe_context *ctx)
 
38
{
 
39
        struct r600_context *rctx = r600_context(ctx);
 
40
 
 
41
        util_blitter_save_blend(rctx->blitter, rctx->blend);
 
42
        util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
 
43
        if (rctx->stencil_ref) {
 
44
                util_blitter_save_stencil_ref(rctx->blitter,
 
45
                                        &rctx->stencil_ref->state.stencil_ref);
 
46
        }
 
47
        util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer);
 
48
        util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
 
49
        util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
 
50
        util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
 
51
        if (rctx->viewport) {
 
52
                util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
 
53
        }
 
54
        if (rctx->clip) {
 
55
                util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
 
56
        }
 
57
        util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
 
58
                                        rctx->vertex_buffer);
 
59
 
 
60
        /* remove ptr so they don't get deleted */
 
61
        rctx->blend = NULL;
 
62
        rctx->clip = NULL;
 
63
        rctx->vs_shader = NULL;
 
64
        rctx->ps_shader = NULL;
 
65
        rctx->rasterizer = NULL;
 
66
        rctx->dsa = NULL;
 
67
        rctx->vertex_elements = NULL;
 
68
 
 
69
        /* suspend queries */
 
70
        r600_queries_suspend(ctx);
 
71
}
 
72
 
 
73
static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 
74
                        const float *rgba, double depth, unsigned stencil)
 
75
{
 
76
        struct r600_context *rctx = r600_context(ctx);
 
77
        struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
78
 
 
79
        r600_blitter_save_states(ctx);
 
80
        util_blitter_clear(rctx->blitter, fb->width, fb->height,
 
81
                                fb->nr_cbufs, buffers, rgba, depth,
 
82
                                stencil);
 
83
        /* resume queries */
 
84
        r600_queries_resume(ctx);
 
85
}
 
86
 
 
87
static void r600_clear_render_target(struct pipe_context *ctx,
 
88
                                     struct pipe_surface *dst,
 
89
                                     const float *rgba,
 
90
                                     unsigned dstx, unsigned dsty,
 
91
                                     unsigned width, unsigned height)
 
92
{
 
93
        struct r600_context *rctx = r600_context(ctx);
 
94
        struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
95
 
 
96
        r600_blitter_save_states(ctx);
 
97
        util_blitter_save_framebuffer(rctx->blitter, fb);
 
98
 
 
99
        util_blitter_clear_render_target(rctx->blitter, dst, rgba,
 
100
                                         dstx, dsty, width, height);
 
101
        /* resume queries */
 
102
        r600_queries_resume(ctx);
 
103
}
 
104
 
 
105
static void r600_clear_depth_stencil(struct pipe_context *ctx,
 
106
                                     struct pipe_surface *dst,
 
107
                                     unsigned clear_flags,
 
108
                                     double depth,
 
109
                                     unsigned stencil,
 
110
                                     unsigned dstx, unsigned dsty,
 
111
                                     unsigned width, unsigned height)
 
112
{
 
113
        struct r600_context *rctx = r600_context(ctx);
 
114
        struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
115
 
 
116
        r600_blitter_save_states(ctx);
 
117
        util_blitter_save_framebuffer(rctx->blitter, fb);
 
118
 
 
119
        util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
 
120
                                         dstx, dsty, width, height);
 
121
        /* resume queries */
 
122
        r600_queries_resume(ctx);
 
123
}
 
124
 
 
125
 
 
126
static void r600_resource_copy_region(struct pipe_context *ctx,
 
127
                                      struct pipe_resource *dst,
 
128
                                      struct pipe_subresource subdst,
 
129
                                      unsigned dstx, unsigned dsty, unsigned dstz,
 
130
                                      struct pipe_resource *src,
 
131
                                      struct pipe_subresource subsrc,
 
132
                                      unsigned srcx, unsigned srcy, unsigned srcz,
 
133
                                      unsigned width, unsigned height)
 
134
{
 
135
        util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
 
136
                                  src, subsrc, srcx, srcy, srcz, width, height);
 
137
}
 
138
 
 
139
void r600_init_blit_functions(struct r600_context *rctx)
 
140
{
 
141
        rctx->context.clear = r600_clear;
 
142
        rctx->context.clear_render_target = r600_clear_render_target;
 
143
        rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
 
144
        rctx->context.resource_copy_region = r600_resource_copy_region;
 
145
}
 
146
 
 
147
 
 
148
struct r600_blit_states {
 
149
        struct radeon_state     rasterizer;
 
150
        struct radeon_state     dsa;
 
151
        struct radeon_state     blend;
 
152
        struct radeon_state     cb_cntl;
 
153
        struct radeon_state     vgt;
 
154
        struct radeon_state     draw;
 
155
        struct radeon_state     vs_constant0;
 
156
        struct radeon_state     vs_constant1;
 
157
        struct radeon_state     vs_constant2;
 
158
        struct radeon_state     vs_constant3;
 
159
        struct radeon_state     ps_shader;
 
160
        struct radeon_state     vs_shader;
 
161
        struct radeon_state     vs_resource0;
 
162
        struct radeon_state     vs_resource1;
 
163
};
 
164
 
 
165
static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates)
 
166
{
 
167
        struct radeon_state *rstate;
 
168
        struct radeon_bo *bo;
 
169
        u32 vbo[] = {
 
170
                0xBF800000, 0xBF800000, 0x3F800000, 0x3F800000,
 
171
                0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
 
172
                0x3F800000, 0xBF800000, 0x3F800000, 0x3F800000,
 
173
                0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
 
174
                0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000,
 
175
                0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
 
176
                0xBF800000, 0x3F800000, 0x3F800000, 0x3F800000,
 
177
                0x3F000000, 0x3F000000, 0x3F000000, 0x00000000
 
178
        };
 
179
 
 
180
        /* simple shader */
 
181
        bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
 
182
        if (bo == NULL) {
 
183
                return -ENOMEM;
 
184
        }
 
185
        if (radeon_bo_map(rscreen->rw, bo)) {
 
186
                radeon_bo_decref(rscreen->rw, bo);
 
187
                return -ENOMEM;
 
188
        }
 
189
        memcpy(bo->data, vbo, 128);
 
190
        radeon_bo_unmap(rscreen->rw, bo);
 
191
 
 
192
        rstate = &bstates->vs_resource0;
 
193
        radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
 
194
 
 
195
        /* set states (most default value are 0 and struct already
 
196
         * initialized to 0, thus avoid resetting them)
 
197
         */
 
198
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
 
199
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
 
200
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
 
201
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
 
202
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
 
203
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
 
204
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
 
205
        rstate->bo[0] = bo;
 
206
        rstate->nbo = 1;
 
207
        rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 
208
        if (radeon_state_pm4(rstate)) {
 
209
                radeon_state_fini(rstate);
 
210
                return -ENOMEM;
 
211
        }
 
212
 
 
213
        rstate = &bstates->vs_resource1;
 
214
        radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
 
215
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
 
216
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
 
217
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
 
218
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
 
219
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
 
220
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
 
221
        rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
 
222
        rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
 
223
        rstate->nbo = 1;
 
224
        rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 
225
        if (radeon_state_pm4(rstate)) {
 
226
                radeon_state_fini(rstate);
 
227
                return -ENOMEM;
 
228
        }
 
229
 
 
230
        return 0;
 
231
}
 
232
 
 
233
static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
 
234
{
 
235
        struct radeon_bo *bo;
 
236
        u32 shader_bc_r600[] = {
 
237
                0x00000004, 0x81000400,
 
238
                0x00000008, 0xA01C0000,
 
239
                0xC001A03C, 0x94000688,
 
240
                0xC0024000, 0x94200688,
 
241
                0x7C000000, 0x002D1001,
 
242
                0x00080000, 0x00000000,
 
243
                0x7C000100, 0x002D1002,
 
244
                0x00080000, 0x00000000,
 
245
                0x00000001, 0x00601910,
 
246
                0x00000401, 0x20601910,
 
247
                0x00000801, 0x40601910,
 
248
                0x80000C01, 0x60601910,
 
249
                0x00000002, 0x00801910,
 
250
                0x00000402, 0x20801910,
 
251
                0x00000802, 0x40801910,
 
252
                0x80000C02, 0x60801910
 
253
        };
 
254
        u32 shader_bc_r700[] = {
 
255
                0x00000004, 0x81000400,
 
256
                0x00000008, 0xA01C0000,
 
257
                0xC001A03C, 0x94000688,
 
258
                0xC0024000, 0x94200688,
 
259
                0x7C000000, 0x002D1001,
 
260
                0x00080000, 0x00000000,
 
261
                0x7C000100, 0x002D1002,
 
262
                0x00080000, 0x00000000,
 
263
                0x00000001, 0x00600C90,
 
264
                0x00000401, 0x20600C90,
 
265
                0x00000801, 0x40600C90,
 
266
                0x80000C01, 0x60600C90,
 
267
                0x00000002, 0x00800C90,
 
268
                0x00000402, 0x20800C90,
 
269
                0x00000802, 0x40800C90,
 
270
                0x80000C02, 0x60800C90
 
271
        };
 
272
 
 
273
        /* simple shader */
 
274
        bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
 
275
        if (bo == NULL) {
 
276
                return;
 
277
        }
 
278
        if (radeon_bo_map(rscreen->rw, bo)) {
 
279
                radeon_bo_decref(rscreen->rw, bo);
 
280
                return;
 
281
        }
 
282
        switch (rscreen->chip_class) {
 
283
        case R600:
 
284
                memcpy(bo->data, shader_bc_r600, 128);
 
285
                break;
 
286
        case R700:
 
287
                memcpy(bo->data, shader_bc_r700, 128);
 
288
                break;
 
289
        default:
 
290
                R600_ERR("unsupported chip family\n");
 
291
                radeon_bo_unmap(rscreen->rw, bo);
 
292
                radeon_bo_decref(rscreen->rw, bo);
 
293
                return;
 
294
        }
 
295
        radeon_bo_unmap(rscreen->rw, bo);
 
296
 
 
297
        radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 
298
 
 
299
        /* set states (most default value are 0 and struct already
 
300
         * initialized to 0, thus avoid resetting them)
 
301
         */
 
302
        rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_0] = 0x03020100;
 
303
        rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_1] = 0x07060504;
 
304
        rstate->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = 0x00000005;
 
305
 
 
306
        rstate->bo[0] = bo;
 
307
        rstate->bo[1] = radeon_bo_incref(rscreen->rw, bo);
 
308
        rstate->nbo = 2;
 
309
        rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 
310
        rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 
311
 
 
312
        radeon_state_pm4(rstate);
 
313
}
 
314
 
 
315
static void r600_blit_state_ps_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
 
316
{
 
317
        struct radeon_bo *bo;
 
318
        u32 shader_bc_r600[] = {
 
319
                0x00000002, 0xA00C0000,
 
320
                0xC0008000, 0x94200688,
 
321
                0x00000000, 0x00201910,
 
322
                0x00000400, 0x20201910,
 
323
                0x00000800, 0x40201910,
 
324
                0x80000C00, 0x60201910
 
325
        };
 
326
        u32 shader_bc_r700[] = {
 
327
                0x00000002, 0xA00C0000,
 
328
                0xC0008000, 0x94200688,
 
329
                0x00000000, 0x00200C90,
 
330
                0x00000400, 0x20200C90,
 
331
                0x00000800, 0x40200C90,
 
332
                0x80000C00, 0x60200C90
 
333
        };
 
334
 
 
335
        /* simple shader */
 
336
        bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
 
337
        if (bo == NULL) {
 
338
                radeon_bo_decref(rscreen->rw, bo);
 
339
                return;
 
340
        }
 
341
        if (radeon_bo_map(rscreen->rw, bo)) {
 
342
                return;
 
343
        }
 
344
        switch (rscreen->chip_class) {
 
345
        case R600:
 
346
                memcpy(bo->data, shader_bc_r600, 48);
 
347
                break;
 
348
        case R700:
 
349
                memcpy(bo->data, shader_bc_r700, 48);
 
350
                break;
 
351
        default:
 
352
                R600_ERR("unsupported chip family\n");
 
353
                radeon_bo_unmap(rscreen->rw, bo);
 
354
                radeon_bo_decref(rscreen->rw, bo);
 
355
                return;
 
356
        }
 
357
        radeon_bo_unmap(rscreen->rw, bo);
 
358
 
 
359
        radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
 
360
 
 
361
        /* set states (most default value are 0 and struct already
 
362
         * initialized to 0, thus avoid resetting them)
 
363
         */
 
364
        rstate->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0] = 0x00000C00;
 
365
        rstate->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = 0x10000001;
 
366
        rstate->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
 
367
        rstate->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = 0x00000002;
 
368
 
 
369
        rstate->bo[0] = bo;
 
370
        rstate->nbo = 1;
 
371
        rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 
372
 
 
373
        radeon_state_pm4(rstate);
 
374
}
 
375
 
 
376
static void r600_blit_state_vgt(struct r600_screen *rscreen, struct radeon_state *rstate)
 
377
{
 
378
        radeon_state_init(rstate, rscreen->rw, R600_STATE_VGT, 0, 0);
 
379
 
 
380
        /* set states (most default value are 0 and struct already
 
381
         * initialized to 0, thus avoid resetting them)
 
382
         */
 
383
        rstate->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
 
384
        rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
 
385
        rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005;
 
386
 
 
387
        radeon_state_pm4(rstate);
 
388
}
 
389
 
 
390
static void r600_blit_state_draw(struct r600_screen *rscreen, struct radeon_state *rstate)
 
391
{
 
392
        radeon_state_init(rstate, rscreen->rw, R600_STATE_DRAW, 0, 0);
 
393
 
 
394
        /* set states (most default value are 0 and struct already
 
395
         * initialized to 0, thus avoid resetting them)
 
396
         */
 
397
        rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002;
 
398
        rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004;
 
399
 
 
400
        radeon_state_pm4(rstate);
 
401
}
 
402
 
 
403
static void r600_blit_state_vs_constant(struct r600_screen *rscreen, struct radeon_state *rstate,
 
404
                                        unsigned id, float c0, float c1, float c2, float c3)
 
405
{
 
406
        radeon_state_init(rstate, rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
 
407
 
 
408
        /* set states (most default value are 0 and struct already
 
409
         * initialized to 0, thus avoid resetting them)
 
410
         */
 
411
        rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256] = fui(c0);
 
412
        rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256] = fui(c1);
 
413
        rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2);
 
414
        rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3);
 
415
 
 
416
        radeon_state_pm4(rstate);
 
417
}
 
418
 
 
419
static void r600_blit_state_rasterizer(struct r600_screen *rscreen, struct radeon_state *rstate)
 
420
{
 
421
        radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
 
422
 
 
423
        /* set states (most default value are 0 and struct already
 
424
         * initialized to 0, thus avoid resetting them)
 
425
         */
 
426
        rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
 
427
        rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
 
428
        rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
 
429
        rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
 
430
        rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
 
431
        rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
 
432
        rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
 
433
        rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
 
434
        rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004;
 
435
        rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 
436
 
 
437
        radeon_state_pm4(rstate);
 
438
}
 
439
 
 
440
static void r600_blit_state_dsa(struct r600_screen *rscreen, struct radeon_state *rstate)
 
441
{
 
442
        radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
443
 
 
444
        /* set states (most default value are 0 and struct already
 
445
         * initialized to 0, thus avoid resetting them)
 
446
         */
 
447
        rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
 
448
        rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
 
449
        rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
 
450
        rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 
451
        rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
 
452
 
 
453
        radeon_state_pm4(rstate);
 
454
}
 
455
 
 
456
static void r600_blit_state_blend(struct r600_screen *rscreen, struct radeon_state *rstate)
 
457
{
 
458
        radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
 
459
        radeon_state_pm4(rstate);
 
460
}
 
461
 
 
462
static void r600_blit_state_cb_cntl(struct r600_screen *rscreen, struct radeon_state *rstate)
 
463
{
 
464
        radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
 
465
        rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
 
466
        rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 
467
        rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
 
468
        rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0080;
 
469
        rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
 
470
        rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
 
471
        rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
 
472
        radeon_state_pm4(rstate);
 
473
}
 
474
 
 
475
static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates)
 
476
{
 
477
        struct r600_screen *rscreen = r600_screen(ctx->screen);
 
478
 
 
479
        r600_blit_state_ps_shader(rscreen, &bstates->ps_shader);
 
480
        r600_blit_state_vs_shader(rscreen, &bstates->vs_shader);
 
481
        r600_blit_state_vgt(rscreen, &bstates->vgt);
 
482
        r600_blit_state_draw(rscreen, &bstates->draw);
 
483
        r600_blit_state_vs_constant(rscreen, &bstates->vs_constant0, 0, 1.0, 0.0, 0.0, 0.0);
 
484
        r600_blit_state_vs_constant(rscreen, &bstates->vs_constant1, 1, 0.0, 1.0, 0.0, 0.0);
 
485
        r600_blit_state_vs_constant(rscreen, &bstates->vs_constant2, 2, 0.0, 0.0, -0.00199900055, 0.0);
 
486
        r600_blit_state_vs_constant(rscreen, &bstates->vs_constant3, 3, 0.0, 0.0, -0.99900049, 1.0);
 
487
        r600_blit_state_rasterizer(rscreen, &bstates->rasterizer);
 
488
        r600_blit_state_dsa(rscreen, &bstates->dsa);
 
489
        r600_blit_state_blend(rscreen, &bstates->blend);
 
490
        r600_blit_state_cb_cntl(rscreen, &bstates->cb_cntl);
 
491
        r600_blit_state_vs_resources(rscreen, bstates);
 
492
        return 0;
 
493
}
 
494
 
 
495
static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates)
 
496
{
 
497
        radeon_state_fini(&bstates->ps_shader);
 
498
        radeon_state_fini(&bstates->vs_shader);
 
499
        radeon_state_fini(&bstates->vs_resource0);
 
500
        radeon_state_fini(&bstates->vs_resource1);
 
501
}
 
502
 
 
503
int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 
504
{
 
505
        struct r600_screen *rscreen = r600_screen(ctx->screen);
 
506
        struct r600_context *rctx = r600_context(ctx);
 
507
        struct radeon_draw draw;
 
508
        struct r600_blit_states bstates;
 
509
        int r;
 
510
 
 
511
        r = r600_texture_scissor(ctx, rtexture, level);
 
512
        if (r) {
 
513
                return r;
 
514
        }
 
515
        r = r600_texture_cb(ctx, rtexture, 0, level);
 
516
        if (r) {
 
517
                return r;
 
518
        }
 
519
        r = r600_texture_db(ctx, rtexture, level);
 
520
        if (r) {
 
521
                return r;
 
522
        }
 
523
        r = r600_texture_viewport(ctx, rtexture, level);
 
524
        if (r) {
 
525
                return r;
 
526
        }
 
527
 
 
528
        r = r600_blit_states_init(ctx, &bstates);
 
529
        if (r) {
 
530
                return r;
 
531
        }
 
532
        bstates.dsa.states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
 
533
        bstates.cb_cntl.states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
 
534
        /* force rebuild */
 
535
        bstates.dsa.cpm4 = bstates.cb_cntl.cpm4 = 0;
 
536
        if (radeon_state_pm4(&bstates.dsa)) {
 
537
                goto out;
 
538
        }
 
539
        if (radeon_state_pm4(&bstates.cb_cntl)) {
 
540
                goto out;
 
541
        }
 
542
 
 
543
        r = radeon_draw_init(&draw, rscreen->rw);
 
544
        if (r) {
 
545
                R600_ERR("failed creating draw for uncompressing textures\n");
 
546
                goto out;
 
547
        }
 
548
 
 
549
        radeon_draw_bind(&draw, &bstates.vs_shader);
 
550
        radeon_draw_bind(&draw, &bstates.ps_shader);
 
551
        radeon_draw_bind(&draw, &bstates.rasterizer);
 
552
        radeon_draw_bind(&draw, &bstates.dsa);
 
553
        radeon_draw_bind(&draw, &bstates.blend);
 
554
        radeon_draw_bind(&draw, &bstates.cb_cntl);
 
555
        radeon_draw_bind(&draw, &rctx->config);
 
556
        radeon_draw_bind(&draw, &bstates.vgt);
 
557
        radeon_draw_bind(&draw, &bstates.draw);
 
558
        radeon_draw_bind(&draw, &bstates.vs_resource0);
 
559
        radeon_draw_bind(&draw, &bstates.vs_resource1);
 
560
        radeon_draw_bind(&draw, &bstates.vs_constant0);
 
561
        radeon_draw_bind(&draw, &bstates.vs_constant1);
 
562
        radeon_draw_bind(&draw, &bstates.vs_constant2);
 
563
        radeon_draw_bind(&draw, &bstates.vs_constant3);
 
564
        radeon_draw_bind(&draw, &rtexture->viewport[level]);
 
565
        radeon_draw_bind(&draw, &rtexture->scissor[level]);
 
566
        radeon_draw_bind(&draw, &rtexture->cb[0][level]);
 
567
        radeon_draw_bind(&draw, &rtexture->db[level]);
 
568
 
 
569
        /* suspend queries */
 
570
        r600_queries_suspend(ctx);
 
571
 
 
572
        /* schedule draw*/
 
573
        r = radeon_ctx_set_draw(&rctx->ctx, &draw);
 
574
        if (r == -EBUSY) {
 
575
                r600_flush(ctx, 0, NULL);
 
576
                r = radeon_ctx_set_draw(&rctx->ctx, &draw);
 
577
        }
 
578
        if (r) {
 
579
                goto out;
 
580
        }
 
581
 
 
582
        /* resume queries */
 
583
        r600_queries_resume(ctx);
 
584
 
 
585
out:
 
586
        r600_blit_states_destroy(ctx, &bstates);
 
587
        return r;
 
588
}