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Viewing changes to src/mesa/drivers/dri/i965/gen6_wm_state.c

  • Committer: Bazaar Package Importer
  • Author(s): Robert Hooker, Robert Hooker, Christopher James Halse Rogers
  • Date: 2010-09-14 08:55:40 UTC
  • mfrom: (1.2.28 upstream)
  • Revision ID: james.westby@ubuntu.com-20100914085540-m4fpl0hdjlfd4jgz
Tags: 7.9~git20100909-0ubuntu1
https://launchpad.net/bugs/631413
https://launchpad.net/bugs/628930
https://launchpad.net/bugs/628727
https://launchpad.net/bugs/596292
https://launchpad.net/bugs/599741
https://launchpad.net/bugs/630315
https://launchpad.net/bugs/613694
https://launchpad.net/bugs/599741
https://launchpad.net/bugs/578619
https://launchpad.net/bugs/626943
https://launchpad.net/bugs/610541
https://launchpad.net/bugs/601052
[ Robert Hooker ]
* New upstream git snapshot up to commit 94118fe2d4b1e5 (LP: #631413)
* New features include ATI HD5xxx series support in r600, and a vastly
  improved glsl compiler.
* Remove pre-generated .pc's, use the ones generated at build time
  instead.
* Remove all references to mesa-utils now that its no longer shipped
  with the mesa source.
* Disable the experimental ARB_fragment_shader option by default on
  i915, it exposes incomplete functionality that breaks KDE compositing
  among other things. It can be enabled via driconf still. (LP: #628930).

[ Christopher James Halse Rogers ]
* debian/patches/04_osmesa_version.diff:
  - Refresh for new upstream
* Bugs fixed in this release:
  - Fixes severe rendering corruption in Unity on radeon (LP: #628727,
    LP: #596292, LP: #599741, LP: #630315, LP: #613694, LP: #599741).
  - Also fixes rendering in gnome-shell (LP: #578619).
  - Flickering in OpenGL apps on radeon (LP: #626943, LP: #610541).
  - Provides preliminary support for new intel chips (LP: #601052).
* debian/rules:
  - Update configure flags to match upstream reshuffling.
  - Explicitly remove gallium DRI drivers that we don't want to ship.
* Update debian/gbp.conf for this Maverick-specific packaging
* libegl1-mesa-dri-x11,kms: There are no longer separate kms or x11 drivers
  for EGL, libegl1-mesa-drivers now contains a single driver that provides
  both backends.

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Lines of Context:
src/mesa/drivers/dri/i965/gen6_wm_state.c
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#include "brw_state.h"
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#include "brw_defines.h"
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#include "brw_util.h"
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#include "shader/prog_parameter.h"
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#include "shader/prog_statevars.h"
 
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#include "program/prog_parameter.h"
 
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#include "program/prog_statevars.h"
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#include "intel_batchbuffer.h"
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static void
 
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prepare_wm_constants(struct brw_context *brw)
 
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{
 
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   struct intel_context *intel = &brw->intel;
 
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   GLcontext *ctx = &intel->ctx;
 
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   const struct brw_fragment_program *fp =
 
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      brw_fragment_program_const(brw->fragment_program);
 
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   drm_intel_bo_unreference(brw->wm.push_const_bo);
 
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   brw->wm.push_const_bo = NULL;
 
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   /* Updates the ParamaterValues[i] pointers for all parameters of the
 
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    * basic type of PROGRAM_STATE_VAR.
 
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    */
 
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   /* XXX: Should this happen somewhere before to get our state flag set? */
 
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   _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 
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   if (brw->wm.prog_data->nr_params != 0) {
 
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      float *constants;
 
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      unsigned int i;
 
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      brw->wm.push_const_bo = drm_intel_bo_alloc(intel->bufmgr,
 
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                                                 "WM constant_bo",
 
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                                                 brw->wm.prog_data->nr_params *
 
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                                                 sizeof(float),
 
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                                                 4096);
 
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      drm_intel_gem_bo_map_gtt(brw->wm.push_const_bo);
 
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      constants = brw->wm.push_const_bo->virtual;
 
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      for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
 
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         constants[i] = *brw->wm.prog_data->param[i];
 
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      }
 
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      drm_intel_gem_bo_unmap_gtt(brw->wm.push_const_bo);
 
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   }
 
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}
 
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const struct brw_tracked_state gen6_wm_constants = {
 
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   .dirty = {
 
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      .mesa  = _NEW_PROGRAM_CONSTANTS,
 
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      .brw   = 0,
 
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      .cache = 0,
 
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   },
 
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   .prepare = prepare_wm_constants,
 
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};
 
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static void
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upload_wm_state(struct brw_context *brw)
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{
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   struct intel_context *intel = &brw->intel;
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   GLcontext *ctx = &intel->ctx;
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   const struct brw_fragment_program *fp =
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      brw_fragment_program_const(brw->fragment_program);
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   unsigned int nr_params = fp->program.Base.Parameters->NumParameters;
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   drm_intel_bo *constant_bo;
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   int i;
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   uint32_t dw2, dw4, dw5, dw6;
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   if (fp->use_const_buffer || nr_params == 0) {
 
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   if (fp->use_const_buffer || brw->wm.prog_data->nr_params == 0) {
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      /* Disable the push constant buffers. */
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      BEGIN_BATCH(5);
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      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
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      OUT_BATCH(0);
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      ADVANCE_BATCH();
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   } else {
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      /* Updates the ParamaterValues[i] pointers for all parameters of the
59
 
       * basic type of PROGRAM_STATE_VAR.
60
 
       */
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      _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
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      constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
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                                       nr_params * 4 * sizeof(float),
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                                       4096);
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      drm_intel_gem_bo_map_gtt(constant_bo);
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      for (i = 0; i < nr_params; i++) {
68
 
         memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
69
 
                fp->program.Base.Parameters->ParameterValues[i],
70
 
                4 * sizeof(float));
71
 
      }
72
 
      drm_intel_gem_bo_unmap_gtt(constant_bo);
73
 
 
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      BEGIN_BATCH(5);
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      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
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                GEN6_CONSTANT_BUFFER_0_ENABLE |
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                (5 - 2));
78
 
      OUT_RELOC(constant_bo,
 
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      OUT_RELOC(brw->wm.push_const_bo,
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                I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
80
 
                ALIGN(nr_params, 2) / 2 - 1);
 
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                ALIGN(brw->wm.prog_data->nr_params, 8) / 8 - 1);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      OUT_BATCH(0);
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      ADVANCE_BATCH();
85
 
 
86
 
      drm_intel_bo_unreference(constant_bo);
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   }
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   intel_batchbuffer_emit_mi_flush(intel->batch);
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   /* CACHE_NEW_SAMPLER */
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   dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
101
 
   dw4 |= (1 << GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 
124
   dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 
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           GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
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   dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
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   dw5 |= GEN6_WM_DISPATCH_ENABLE;