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/**********************************************************
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* Copyright 2009 VMware, Inc. All rights reserved.
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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**********************************************************/
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* Wrappers for DRM ioctl functionlaity used by the rest of the vmw
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* Based on svgaicd_escape.c
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#include "util/u_memory.h"
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#include "util/u_math.h"
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#include "svgadump/svga_dump.h"
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#include "vmw_screen.h"
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#include "vmw_context.h"
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#include "vmwgfx_drm.h"
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/* XXX: This isn't a real hardware flag, but just a hack for kernel to
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* know about primary surfaces. In newer versions of the kernel
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* interface the driver uses a special field.
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#define SVGA3D_SURFACE_HINT_SCANOUT (1 << 9)
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vmw_check_last_cmd(struct vmw_winsys_screen *vws)
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static uint32_t buffer[16384];
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struct drm_vmw_fifo_debug_arg arg;
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memset(&arg, 0, sizeof(arg));
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arg.debug_buffer = (unsigned long)buffer;
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arg.debug_buffer_size = 65536;
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ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FIFO_DEBUG,
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debug_printf("%s Ioctl error: \"%s\".\n", __FUNCTION__, strerror(-ret));
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if (arg.did_not_fit) {
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debug_printf("%s Command did not fit completely.\n", __FUNCTION__);
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svga_dump_commands(buffer, arg.used_size);
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vmw_ioctl_fifo_unmap(struct vmw_winsys_screen *vws, void *mapping)
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(void)munmap(mapping, getpagesize());
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vmw_ioctl_fifo_map(struct vmw_winsys_screen *vws,
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uint32_t fifo_offset )
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map = mmap(NULL, getpagesize(), PROT_READ, MAP_SHARED,
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vws->ioctl.drm_fd, fifo_offset);
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if (map == MAP_FAILED) {
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debug_printf("Map failed %s\n", strerror(errno));
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vmw_printf("Fifo (min) is 0x%08x\n", ((uint32_t *) map)[SVGA_FIFO_MIN]);
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vmw_ioctl_context_create(struct vmw_winsys_screen *vws)
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struct drm_vmw_context_arg c_arg;
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ret = drmCommandRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_CONTEXT,
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&c_arg, sizeof(c_arg));
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vmw_check_last_cmd(vws);
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vmw_printf("Context id is %d\n", c_arg.cid);
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vmw_ioctl_context_destroy(struct vmw_winsys_screen *vws, uint32 cid)
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struct drm_vmw_context_arg c_arg;
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memset(&c_arg, 0, sizeof(c_arg));
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(void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_CONTEXT,
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&c_arg, sizeof(c_arg));
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vmw_check_last_cmd(vws);
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vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
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SVGA3dSurfaceFlags flags,
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SVGA3dSurfaceFormat format,
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uint32_t numFaces, uint32_t numMipLevels)
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union drm_vmw_surface_create_arg s_arg;
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struct drm_vmw_surface_create_req *req = &s_arg.req;
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struct drm_vmw_surface_arg *rep = &s_arg.rep;
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struct drm_vmw_size sizes[DRM_VMW_MAX_SURFACE_FACES*
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DRM_VMW_MAX_MIP_LEVELS];
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struct drm_vmw_size *cur_size;
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vmw_printf("%s flags %d format %d\n", __FUNCTION__, flags, format);
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memset(&s_arg, 0, sizeof(s_arg));
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if (vws->use_old_scanout_flag &&
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(flags & SVGA3D_SURFACE_HINT_SCANOUT)) {
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req->flags = (uint32_t) flags;
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req->scanout = false;
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} else if (flags & SVGA3D_SURFACE_HINT_SCANOUT) {
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req->flags = (uint32_t) (flags & ~SVGA3D_SURFACE_HINT_SCANOUT);
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req->flags = (uint32_t) flags;
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req->scanout = false;
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req->format = (uint32_t) format;
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assert(numFaces * numMipLevels < DRM_VMW_MAX_SURFACE_FACES*
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DRM_VMW_MAX_MIP_LEVELS);
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for (iFace = 0; iFace < numFaces; ++iFace) {
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SVGA3dSize mipSize = size;
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req->mip_levels[iFace] = numMipLevels;
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for (iMipLevel = 0; iMipLevel < numMipLevels; ++iMipLevel) {
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cur_size->width = mipSize.width;
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cur_size->height = mipSize.height;
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cur_size->depth = mipSize.depth;
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mipSize.width = MAX2(mipSize.width >> 1, 1);
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mipSize.height = MAX2(mipSize.height >> 1, 1);
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mipSize.depth = MAX2(mipSize.depth >> 1, 1);
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for (iFace = numFaces; iFace < SVGA3D_MAX_SURFACE_FACES; ++iFace) {
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req->mip_levels[iFace] = 0;
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req->size_addr = (unsigned long)&sizes;
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ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SURFACE,
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&s_arg, sizeof(s_arg));
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vmw_printf("Surface id is %d\n", rep->sid);
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vmw_check_last_cmd(vws);
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vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws, uint32 sid)
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struct drm_vmw_surface_arg s_arg;
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memset(&s_arg, 0, sizeof(s_arg));
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(void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_SURFACE,
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&s_arg, sizeof(s_arg));
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vmw_check_last_cmd(vws);
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vmw_ioctl_command(struct vmw_winsys_screen *vws, void *commands, uint32_t size,
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struct drm_vmw_execbuf_arg arg;
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struct drm_vmw_fence_rep rep;
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static boolean firsttime = TRUE;
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static boolean debug = FALSE;
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static boolean skip = FALSE;
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debug = debug_get_bool_option("SVGA_DUMP_CMD", FALSE);
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skip = debug_get_bool_option("SVGA_SKIP_CMD", FALSE);
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svga_dump_commands(commands, size);
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memset(&arg, 0, sizeof(arg));
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memset(&rep, 0, sizeof(rep));
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arg.fence_rep = (unsigned long)&rep;
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arg.commands = (unsigned long)commands;
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arg.command_size = size;
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ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_EXECBUF, &arg, sizeof(arg));
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} while(ret == -ERESTART);
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debug_printf("%s error %s.\n", __FUNCTION__, strerror(-ret));
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* Kernel has synced and put the last fence sequence in the FIFO
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if (rep.error == -EFAULT)
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rep.fence_seq = vws->ioctl.fifo_map[SVGA_FIFO_FENCE];
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debug_printf("%s Fence error %s.\n", __FUNCTION__,
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strerror(-rep.error));
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vws->ioctl.last_fence = rep.fence_seq;
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*pfence = rep.fence_seq;
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vmw_check_last_cmd(vws);
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vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size)
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struct vmw_region *region;
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union drm_vmw_alloc_dmabuf_arg arg;
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struct drm_vmw_alloc_dmabuf_req *req = &arg.req;
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struct drm_vmw_dmabuf_rep *rep = &arg.rep;
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vmw_printf("%s: size = %u\n", __FUNCTION__, size);
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region = CALLOC_STRUCT(vmw_region);
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memset(&arg, 0, sizeof(arg));
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ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_ALLOC_DMABUF, &arg,
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} while (ret == -ERESTART);
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debug_printf("IOCTL failed %d: %s\n", ret, strerror(-ret));
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region->ptr.gmrId = rep->cur_gmr_id;
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region->ptr.offset = rep->cur_gmr_offset;
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region->handle = rep->handle;
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region->map_handle = rep->map_handle;
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region->map_count = 0;
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region->drm_fd = vws->ioctl.drm_fd;
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vmw_printf(" gmrId = %u, offset = %u\n",
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region->ptr.gmrId, region->ptr.offset);
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vmw_ioctl_region_destroy(struct vmw_region *region)
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struct drm_vmw_unref_dmabuf_arg arg;
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vmw_printf("%s: gmrId = %u, offset = %u\n", __FUNCTION__,
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region->ptr.gmrId, region->ptr.offset);
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munmap(region->data, region->size);
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memset(&arg, 0, sizeof(arg));
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arg.handle = region->handle;
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drmCommandWrite(region->drm_fd, DRM_VMW_UNREF_DMABUF, &arg, sizeof(arg));
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vmw_ioctl_region_ptr(struct vmw_region *region)
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vmw_ioctl_region_map(struct vmw_region *region)
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vmw_printf("%s: gmrId = %u, offset = %u\n", __FUNCTION__,
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region->ptr.gmrId, region->ptr.offset);
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if (region->data == NULL) {
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map = mmap(NULL, region->size, PROT_READ | PROT_WRITE, MAP_SHARED,
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region->drm_fd, region->map_handle);
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if (map == MAP_FAILED) {
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debug_printf("%s: Map failed.\n", __FUNCTION__);
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vmw_ioctl_region_unmap(struct vmw_region *region)
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vmw_printf("%s: gmrId = %u, offset = %u\n", __FUNCTION__,
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region->ptr.gmrId, region->ptr.offset);
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vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
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current = vws->ioctl.fifo_map[SVGA_FIFO_FENCE];
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if ((int32)(current - expected) >= 0)
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return 0; /* fence passed */
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vmw_ioctl_sync(struct vmw_winsys_screen *vws,
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struct drm_vmw_fence_wait_arg arg;
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vmw_printf("%s: fence = %lu\n", __FUNCTION__,
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(unsigned long)fence);
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cur_fence = vws->ioctl.fifo_map[SVGA_FIFO_FENCE];
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vmw_printf("%s: Fence id read is 0x%08x\n", __FUNCTION__,
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(unsigned int)cur_fence);
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if ((cur_fence - fence) < (1 << 24))
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memset(&arg, 0, sizeof(arg));
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arg.sequence = fence;
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ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_WAIT, &arg,
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} while (ret == -ERESTART);
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vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
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if(vmw_ioctl_fence_signalled(vws, fence) != 0) {
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vmw_ioctl_sync(vws, fence);
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vmw_ioctl_init(struct vmw_winsys_screen *vws)
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struct drm_vmw_getparam_arg gp_arg;
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memset(&gp_arg, 0, sizeof(gp_arg));
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gp_arg.param = DRM_VMW_PARAM_3D;
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ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
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&gp_arg, sizeof(gp_arg));
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if (ret || gp_arg.value == 0) {
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debug_printf("No 3D enabled (%i, %s)\n", ret, strerror(-ret));
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memset(&gp_arg, 0, sizeof(gp_arg));
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gp_arg.param = DRM_VMW_PARAM_FIFO_OFFSET;
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ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
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&gp_arg, sizeof(gp_arg));
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debug_printf("GET_PARAM on %d returned %d: %s\n",
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vws->ioctl.drm_fd, ret, strerror(-ret));
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vmw_printf("Offset to map is 0x%08llx\n",
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(unsigned long long)gp_arg.value);
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vws->ioctl.fifo_map = vmw_ioctl_fifo_map(vws, gp_arg.value);
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if (vws->ioctl.fifo_map == NULL)
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vmw_printf("%s OK\n", __FUNCTION__);
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debug_printf("%s Failed\n", __FUNCTION__);
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vmw_ioctl_cleanup(struct vmw_winsys_screen *vws)
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vmw_ioctl_fifo_unmap(vws, (void *)vws->ioctl.fifo_map);