2
#include "exec/gdbstub.h"
4
#include "qemu/host-utils.h"
5
#include "sysemu/sysemu.h"
6
#include "qemu/bitops.h"
8
#ifndef CONFIG_USER_ONLY
9
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10
int access_type, int is_user,
11
hwaddr *phys_ptr, int *prot,
12
target_ulong *page_size);
15
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
19
/* VFP data registers are always little-endian. */
20
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
22
stfq_le_p(buf, env->vfp.regs[reg]);
25
if (arm_feature(env, ARM_FEATURE_NEON)) {
26
/* Aliases for Q regs. */
29
stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
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stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
34
switch (reg - nregs) {
35
case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36
case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37
case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
42
static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
46
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
48
env->vfp.regs[reg] = ldfq_le_p(buf);
51
if (arm_feature(env, ARM_FEATURE_NEON)) {
54
env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55
env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
59
switch (reg - nregs) {
60
case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61
case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
62
case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
67
static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
70
*value = CPREG_FIELD32(env, ri);
74
static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
77
CPREG_FIELD32(env, ri) = value;
81
static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
84
/* Raw read of a coprocessor register (as needed for migration, etc)
85
* return true on success, false if the read is impossible for some reason.
87
if (ri->type & ARM_CP_CONST) {
89
} else if (ri->raw_readfn) {
90
return (ri->raw_readfn(env, ri, v) == 0);
91
} else if (ri->readfn) {
92
return (ri->readfn(env, ri, v) == 0);
94
if (ri->type & ARM_CP_64BIT) {
95
*v = CPREG_FIELD64(env, ri);
97
*v = CPREG_FIELD32(env, ri);
103
static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
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/* Raw write of a coprocessor register (as needed for migration, etc).
107
* Return true on success, false if the write is impossible for some reason.
108
* Note that constant registers are treated as write-ignored; the
109
* caller should check for success by whether a readback gives the
112
if (ri->type & ARM_CP_CONST) {
114
} else if (ri->raw_writefn) {
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return (ri->raw_writefn(env, ri, v) == 0);
116
} else if (ri->writefn) {
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return (ri->writefn(env, ri, v) == 0);
119
if (ri->type & ARM_CP_64BIT) {
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CPREG_FIELD64(env, ri) = v;
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CPREG_FIELD32(env, ri) = v;
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bool write_cpustate_to_list(ARMCPU *cpu)
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/* Write the coprocessor state from cpu->env to the (index,value) list. */
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for (i = 0; i < cpu->cpreg_array_len; i++) {
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uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
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const ARMCPRegInfo *ri;
138
ri = get_arm_cp_reginfo(cpu, regidx);
143
if (ri->type & ARM_CP_NO_MIGRATE) {
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if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
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cpu->cpreg_values[i] = v;
155
bool write_list_to_cpustate(ARMCPU *cpu)
160
for (i = 0; i < cpu->cpreg_array_len; i++) {
161
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
162
uint64_t v = cpu->cpreg_values[i];
164
const ARMCPRegInfo *ri;
166
ri = get_arm_cp_reginfo(cpu, regidx);
171
if (ri->type & ARM_CP_NO_MIGRATE) {
174
/* Write value and confirm it reads back as written
175
* (to catch read-only registers and partially read-only
176
* registers where the incoming migration value doesn't match)
178
if (!write_raw_cp_reg(&cpu->env, ri, v) ||
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!read_raw_cp_reg(&cpu->env, ri, &readback) ||
187
static void add_cpreg_to_list(gpointer key, gpointer opaque)
189
ARMCPU *cpu = opaque;
191
const ARMCPRegInfo *ri;
193
regidx = *(uint32_t *)key;
194
ri = get_arm_cp_reginfo(cpu, regidx);
196
if (!(ri->type & ARM_CP_NO_MIGRATE)) {
197
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
198
/* The value array need not be initialized at this point */
199
cpu->cpreg_array_len++;
203
static void count_cpreg(gpointer key, gpointer opaque)
205
ARMCPU *cpu = opaque;
207
const ARMCPRegInfo *ri;
209
regidx = *(uint32_t *)key;
210
ri = get_arm_cp_reginfo(cpu, regidx);
212
if (!(ri->type & ARM_CP_NO_MIGRATE)) {
213
cpu->cpreg_array_len++;
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static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
219
uint32_t aidx = *(uint32_t *)a;
220
uint32_t bidx = *(uint32_t *)b;
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static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
227
GList **plist = udata;
229
*plist = g_list_prepend(*plist, key);
232
void init_cpreg_list(ARMCPU *cpu)
234
/* Initialise the cpreg_tuples[] array based on the cp_regs hash.
235
* Note that we require cpreg_tuples[] to be sorted by key ID.
240
g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
242
keys = g_list_sort(keys, cpreg_key_compare);
244
cpu->cpreg_array_len = 0;
246
g_list_foreach(keys, count_cpreg, cpu);
248
arraylen = cpu->cpreg_array_len;
249
cpu->cpreg_indexes = g_new(uint64_t, arraylen);
250
cpu->cpreg_values = g_new(uint64_t, arraylen);
251
cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
252
cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
253
cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
254
cpu->cpreg_array_len = 0;
256
g_list_foreach(keys, add_cpreg_to_list, cpu);
258
assert(cpu->cpreg_array_len == arraylen);
263
static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
265
env->cp15.c3 = value;
266
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
270
static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
272
if (env->cp15.c13_fcse != value) {
273
/* Unlike real hardware the qemu TLB uses virtual addresses,
274
* not modified virtual addresses, so this causes a TLB flush.
277
env->cp15.c13_fcse = value;
281
static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
284
if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
285
/* For VMSA (when not using the LPAE long descriptor page table
286
* format) this register includes the ASID, so do a TLB flush.
287
* For PMSA it is purely a process ID and no action is needed.
291
env->cp15.c13_context = value;
295
static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
298
/* Invalidate all (TLBIALL) */
303
static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
306
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
307
tlb_flush_page(env, value & TARGET_PAGE_MASK);
311
static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
314
/* Invalidate by ASID (TLBIASID) */
315
tlb_flush(env, value == 0);
319
static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
322
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
323
tlb_flush_page(env, value & TARGET_PAGE_MASK);
327
static const ARMCPRegInfo cp_reginfo[] = {
328
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
329
* version" bits will read as a reserved value, which should cause
330
* Linux to not try to use the debug hardware.
332
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
333
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
334
/* MMU Domain access control / MPU write buffer control */
335
{ .name = "DACR", .cp = 15,
336
.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
337
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
338
.resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
339
{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
340
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
341
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
342
{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
345
/* ??? This covers not just the impdef TLB lockdown registers but also
346
* some v7VMSA registers relating to TEX remap, so it is overly broad.
348
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
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/* MMU TLB control. Note that the wildcarding means we cover not just
351
* the unified TLB ops but also the dside/iside/inner-shareable variants.
353
{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
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.type = ARM_CP_NO_MIGRATE },
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{ .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
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.type = ARM_CP_NO_MIGRATE },
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{ .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
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.type = ARM_CP_NO_MIGRATE },
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{ .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
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.type = ARM_CP_NO_MIGRATE },
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/* Cache maintenance ops; some of this space may be overridden later. */
366
{ .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
367
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
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.type = ARM_CP_NOP | ARM_CP_OVERRIDE },
372
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
373
/* Not all pre-v6 cores implemented this WFI, so this is slightly
376
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_WFI },
381
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
382
/* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
383
* is UNPREDICTABLE; we choose to NOP as most implementations do).
385
{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
386
.access = PL1_W, .type = ARM_CP_WFI },
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/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
388
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
389
* OMAPCP will override this space.
391
{ .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
392
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
394
{ .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
395
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
397
/* v6 doesn't have the cache ID registers but Linux reads them anyway */
398
{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
399
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
404
static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
406
if (env->cp15.c1_coproc != value) {
407
env->cp15.c1_coproc = value;
408
/* ??? Is this safe when called from within a TB? */
414
static const ARMCPRegInfo v6_cp_reginfo[] = {
415
/* prefetch by MVA in v6, NOP in v7 */
416
{ .name = "MVA_prefetch",
417
.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
418
.access = PL1_W, .type = ARM_CP_NOP },
419
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
420
.access = PL0_W, .type = ARM_CP_NOP },
421
{ .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
422
.access = PL0_W, .type = ARM_CP_NOP },
423
{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
424
.access = PL0_W, .type = ARM_CP_NOP },
425
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
426
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
428
/* Watchpoint Fault Address Register : should actually only be present
429
* for 1136, 1176, 11MPCore.
431
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
432
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
433
{ .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
434
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
435
.resetvalue = 0, .writefn = cpacr_write },
440
static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
443
/* Generic performance monitor register read function for where
444
* user access may be allowed by PMUSERENR.
446
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
449
*value = CPREG_FIELD32(env, ri);
453
static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
456
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
459
/* only the DP, X, D and E bits are writable */
460
env->cp15.c9_pmcr &= ~0x39;
461
env->cp15.c9_pmcr |= (value & 0x39);
465
static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
468
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
472
env->cp15.c9_pmcnten |= value;
476
static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
479
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
483
env->cp15.c9_pmcnten &= ~value;
487
static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
490
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
493
env->cp15.c9_pmovsr &= ~value;
497
static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
500
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
503
env->cp15.c9_pmxevtyper = value & 0xff;
507
static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
510
env->cp15.c9_pmuserenr = value & 1;
514
static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
517
/* We have no event counters so only the C bit can be changed */
519
env->cp15.c9_pminten |= value;
523
static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
527
env->cp15.c9_pminten &= ~value;
531
static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
534
ARMCPU *cpu = arm_env_get_cpu(env);
535
*value = cpu->ccsidr[env->cp15.c0_cssel];
539
static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
542
env->cp15.c0_cssel = value & 0xf;
546
static const ARMCPRegInfo v7_cp_reginfo[] = {
547
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
550
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
551
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
552
{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
553
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
554
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
555
{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
556
.access = PL1_W, .type = ARM_CP_NOP },
557
/* Performance monitors are implementation defined in v7,
558
* but with an ARM recommended set of registers, which we
559
* follow (although we don't actually implement any counters)
561
* Performance registers fall into three categories:
562
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
563
* (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
564
* (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
565
* For the cases controlled by PMUSERENR we must set .access to PL0_RW
566
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
568
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
569
.access = PL0_RW, .resetvalue = 0,
570
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
571
.readfn = pmreg_read, .writefn = pmcntenset_write,
572
.raw_readfn = raw_read, .raw_writefn = raw_write },
573
{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
574
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
575
.readfn = pmreg_read, .writefn = pmcntenclr_write,
576
.type = ARM_CP_NO_MIGRATE },
577
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
578
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
579
.readfn = pmreg_read, .writefn = pmovsr_write,
580
.raw_readfn = raw_read, .raw_writefn = raw_write },
581
/* Unimplemented so WI. Strictly speaking write accesses in PL0 should
584
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
585
.access = PL0_W, .type = ARM_CP_NOP },
586
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
587
* We choose to RAZ/WI. XXX should respect PMUSERENR.
589
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
590
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
591
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
592
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
593
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
594
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
596
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
597
.readfn = pmreg_read, .writefn = pmxevtyper_write,
598
.raw_readfn = raw_read, .raw_writefn = raw_write },
599
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
600
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
601
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
602
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
603
.access = PL0_R | PL1_RW,
604
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
606
.writefn = pmuserenr_write, .raw_writefn = raw_write },
607
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
609
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
611
.writefn = pmintenset_write, .raw_writefn = raw_write },
612
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
613
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
614
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
615
.resetvalue = 0, .writefn = pmintenclr_write, },
616
{ .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
617
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
618
{ .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
619
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
620
.writefn = csselr_write, .resetvalue = 0 },
621
/* Auxiliary ID register: this actually has an IMPDEF value but for now
622
* just RAZ for all cores:
624
{ .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
625
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
629
static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
636
static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
639
/* This is a helper function because the user access rights
640
* depend on the value of the TEECR.
642
if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
645
*value = env->teehbr;
649
static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
652
if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
659
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
660
{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
661
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
663
.writefn = teecr_write },
664
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
665
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
666
.resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
667
.readfn = teehbr_read, .writefn = teehbr_write },
671
static const ARMCPRegInfo v6k_cp_reginfo[] = {
672
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
674
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
676
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
677
.access = PL0_R|PL1_W,
678
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
680
{ .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
682
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
687
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
688
/* Dummy implementation: RAZ/WI the whole crn=14 space */
689
{ .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
690
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
691
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
696
static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
698
if (arm_feature(env, ARM_FEATURE_LPAE)) {
699
env->cp15.c7_par = value;
700
} else if (arm_feature(env, ARM_FEATURE_V7)) {
701
env->cp15.c7_par = value & 0xfffff6ff;
703
env->cp15.c7_par = value & 0xfffff1ff;
708
#ifndef CONFIG_USER_ONLY
709
/* get_phys_addr() isn't present for user-mode-only targets */
711
/* Return true if extended addresses are enabled, ie this is an
712
* LPAE implementation and we are using the long-descriptor translation
713
* table format because the TTBCR EAE bit is set.
715
static inline bool extended_addresses_enabled(CPUARMState *env)
717
return arm_feature(env, ARM_FEATURE_LPAE)
718
&& (env->cp15.c2_control & (1 << 31));
721
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
724
target_ulong page_size;
726
int ret, is_user = ri->opc2 & 2;
727
int access_type = ri->opc2 & 1;
730
/* Other states are only available with TrustZone */
733
ret = get_phys_addr(env, value, access_type, is_user,
734
&phys_addr, &prot, &page_size);
735
if (extended_addresses_enabled(env)) {
736
/* ret is a DFSR/IFSR value for the long descriptor
737
* translation table format, but with WnR always clear.
738
* Convert it to a 64-bit PAR.
740
uint64_t par64 = (1 << 11); /* LPAE bit always set */
742
par64 |= phys_addr & ~0xfffULL;
743
/* We don't set the ATTR or SH fields in the PAR. */
746
par64 |= (ret & 0x3f) << 1; /* FS */
747
/* Note that S2WLK and FSTAGE are always zero, because we don't
748
* implement virtualization and therefore there can't be a stage 2
752
env->cp15.c7_par = par64;
753
env->cp15.c7_par_hi = par64 >> 32;
755
/* ret is a DFSR/IFSR value for the short descriptor
756
* translation table format (with WnR always clear).
757
* Convert it to a 32-bit PAR.
760
/* We do not set any attribute bits in the PAR */
761
if (page_size == (1 << 24)
762
&& arm_feature(env, ARM_FEATURE_V7)) {
763
env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
765
env->cp15.c7_par = phys_addr & 0xfffff000;
768
env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
769
((ret & (12 << 1)) >> 6) |
770
((ret & 0xf) << 1) | 1;
772
env->cp15.c7_par_hi = 0;
778
static const ARMCPRegInfo vapa_cp_reginfo[] = {
779
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
780
.access = PL1_RW, .resetvalue = 0,
781
.fieldoffset = offsetof(CPUARMState, cp15.c7_par),
782
.writefn = par_write },
783
#ifndef CONFIG_USER_ONLY
784
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
785
.access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
790
/* Return basic MPU access permission bits. */
791
static uint32_t simple_mpu_ap_bits(uint32_t val)
798
for (i = 0; i < 16; i += 2) {
799
ret |= (val >> i) & mask;
805
/* Pad basic MPU access permission bits to extended format. */
806
static uint32_t extended_mpu_ap_bits(uint32_t val)
813
for (i = 0; i < 16; i += 2) {
814
ret |= (val & mask) << i;
820
static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
823
env->cp15.c5_data = extended_mpu_ap_bits(value);
827
static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
830
*value = simple_mpu_ap_bits(env->cp15.c5_data);
834
static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
837
env->cp15.c5_insn = extended_mpu_ap_bits(value);
841
static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
844
*value = simple_mpu_ap_bits(env->cp15.c5_insn);
848
static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
854
*value = env->cp15.c6_region[ri->crm];
858
static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
864
env->cp15.c6_region[ri->crm] = value;
868
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
869
{ .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
870
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
871
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
872
.readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
873
{ .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
874
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
875
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
876
.readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
877
{ .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
879
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
880
{ .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
882
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
883
{ .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
885
.fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
886
{ .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
888
.fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
889
/* Protection region base and size registers */
890
{ .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
891
.opc2 = CP_ANY, .access = PL1_RW,
892
.readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
896
static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
899
int maskshift = extract32(value, 0, 3);
901
if (arm_feature(env, ARM_FEATURE_LPAE)) {
902
value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
906
/* Note that we always calculate c2_mask and c2_base_mask, but
907
* they are only used for short-descriptor tables (ie if EAE is 0);
908
* for long-descriptor tables the TTBCR fields are used differently
909
* and the c2_mask and c2_base_mask values are meaningless.
911
env->cp15.c2_control = value;
912
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
913
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
917
static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
920
if (arm_feature(env, ARM_FEATURE_LPAE)) {
921
/* With LPAE the TTBCR could result in a change of ASID
922
* via the TTBCR.A1 bit, so do a TLB flush.
926
return vmsa_ttbcr_raw_write(env, ri, value);
929
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
931
env->cp15.c2_base_mask = 0xffffc000u;
932
env->cp15.c2_control = 0;
933
env->cp15.c2_mask = 0;
936
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
937
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
939
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
940
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
942
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
943
{ .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
945
.fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
946
{ .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
948
.fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
949
{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
950
.access = PL1_RW, .writefn = vmsa_ttbcr_write,
951
.resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
952
.fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
953
{ .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
954
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
959
static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
962
env->cp15.c15_ticonfig = value & 0xe7;
963
/* The OS_TYPE bit in this register changes the reported CPUID! */
964
env->cp15.c0_cpuid = (value & (1 << 5)) ?
965
ARM_CPUID_TI915T : ARM_CPUID_TI925T;
969
static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
972
env->cp15.c15_threadid = value & 0xffff;
976
static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
979
/* Wait-for-interrupt (deprecated) */
980
cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
984
static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
987
/* On OMAP there are registers indicating the max/min index of dcache lines
988
* containing a dirty line; cache flush operations have to reset these.
990
env->cp15.c15_i_max = 0x000;
991
env->cp15.c15_i_min = 0xff0;
995
static const ARMCPRegInfo omap_cp_reginfo[] = {
996
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
997
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
998
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
999
{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1000
.access = PL1_RW, .type = ARM_CP_NOP },
1001
{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1003
.fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1004
.writefn = omap_ticonfig_write },
1005
{ .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1007
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1008
{ .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1009
.access = PL1_RW, .resetvalue = 0xff0,
1010
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1011
{ .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1013
.fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1014
.writefn = omap_threadid_write },
1015
{ .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1016
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1017
.type = ARM_CP_NO_MIGRATE,
1018
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1019
/* TODO: Peripheral port remap register:
1020
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1021
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1024
{ .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1025
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1026
.type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1027
.writefn = omap_cachemaint_write },
1028
{ .name = "C9", .cp = 15, .crn = 9,
1029
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1030
.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1034
static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1038
if (env->cp15.c15_cpar != value) {
1039
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
1041
env->cp15.c15_cpar = value;
1046
static const ARMCPRegInfo xscale_cp_reginfo[] = {
1047
{ .name = "XSCALE_CPAR",
1048
.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1049
.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1050
.writefn = xscale_cpar_write, },
1051
{ .name = "XSCALE_AUXCR",
1052
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1053
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1058
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1059
/* RAZ/WI the whole crn=15 space, when we don't have a more specific
1060
* implementation of this implementation-defined space.
1061
* Ideally this should eventually disappear in favour of actually
1062
* implementing the correct behaviour for all cores.
1064
{ .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1065
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1066
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1071
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1072
/* Cache status: RAZ because we have no cache so it's always clean */
1073
{ .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1074
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1079
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1080
/* We never have a a block transfer operation in progress */
1081
{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1082
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1084
/* The cache ops themselves: these all NOP for QEMU */
1085
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1086
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1087
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1088
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1089
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1090
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1091
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1092
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1093
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1094
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1095
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1096
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1100
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1101
/* The cache test-and-clean instructions always return (1 << 30)
1102
* to indicate that there are no dirty cache lines.
1104
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1105
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1106
.resetvalue = (1 << 30) },
1107
{ .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1108
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1109
.resetvalue = (1 << 30) },
1113
static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1114
/* Ignore ReadBuffer accesses */
1115
{ .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1116
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1117
.access = PL1_RW, .resetvalue = 0,
1118
.type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1122
static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1125
CPUState *cs = CPU(arm_env_get_cpu(env));
1126
uint32_t mpidr = cs->cpu_index;
1127
/* We don't support setting cluster ID ([8..11])
1128
* so these bits always RAZ.
1130
if (arm_feature(env, ARM_FEATURE_V7MP)) {
1132
/* Cores which are uniprocessor (non-coherent)
1133
* but still implement the MP extensions set
1134
* bit 30. (For instance, A9UP.) However we do
1135
* not currently model any of those cores.
1142
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1143
{ .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1144
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1148
static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1150
*value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1154
static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1156
env->cp15.c7_par_hi = value >> 32;
1157
env->cp15.c7_par = value;
1161
static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1163
env->cp15.c7_par_hi = 0;
1164
env->cp15.c7_par = 0;
1167
static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1170
*value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1174
static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1177
env->cp15.c2_base0_hi = value >> 32;
1178
env->cp15.c2_base0 = value;
1182
static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1185
/* Writes to the 64 bit format TTBRs may change the ASID */
1187
return ttbr064_raw_write(env, ri, value);
1190
static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1192
env->cp15.c2_base0_hi = 0;
1193
env->cp15.c2_base0 = 0;
1196
static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1199
*value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1203
static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1206
env->cp15.c2_base1_hi = value >> 32;
1207
env->cp15.c2_base1 = value;
1211
static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1213
env->cp15.c2_base1_hi = 0;
1214
env->cp15.c2_base1 = 0;
1217
static const ARMCPRegInfo lpae_cp_reginfo[] = {
1218
/* NOP AMAIR0/1: the override is because these clash with the rather
1219
* broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1221
{ .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1222
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1224
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1225
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1227
/* 64 bit access versions of the (dummy) debug registers */
1228
{ .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1229
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1230
{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1231
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1232
{ .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1233
.access = PL1_RW, .type = ARM_CP_64BIT,
1234
.readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1235
{ .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1236
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1237
.writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1238
.resetfn = ttbr064_reset },
1239
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1240
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1241
.writefn = ttbr164_write, .resetfn = ttbr164_reset },
1245
static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1247
CPREG_FIELD32(env, ri) = value & ~0x1f;
1251
static const ARMCPRegInfo trustzone_cp_reginfo[] = {
1252
/* Dummy implementations of registers; we don't enforce the
1253
* 'secure mode only' access checks. TODO: revisit as part of
1254
* proper fake-trustzone support.
1256
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
1257
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
1259
{ .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
1260
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sedbg),
1262
{ .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
1263
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_nseac),
1265
{ .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1266
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
1267
.writefn = vbar_write, .resetvalue = 0 },
1268
{ .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
1269
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c12_mvbar),
1270
.writefn = vbar_write, .resetvalue = 0 },
1274
static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1276
env->cp15.c1_sys = value;
1277
/* ??? Lots of these bits are not implemented. */
1278
/* This may enable/disable the MMU, so do a TLB flush. */
1283
void register_cp_regs_for_features(ARMCPU *cpu)
1285
/* Register all the coprocessor registers based on feature bits */
1286
CPUARMState *env = &cpu->env;
1287
if (arm_feature(env, ARM_FEATURE_M)) {
1288
/* M profile has no coprocessor registers */
1292
define_arm_cp_regs(cpu, cp_reginfo);
1293
if (arm_feature(env, ARM_FEATURE_V6)) {
1294
/* The ID registers all have impdef reset values */
1295
ARMCPRegInfo v6_idregs[] = {
1296
{ .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1297
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1298
.resetvalue = cpu->id_pfr0 },
1299
{ .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1300
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1301
.resetvalue = cpu->id_pfr1 },
1302
{ .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1303
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1304
.resetvalue = cpu->id_dfr0 },
1305
{ .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1306
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1307
.resetvalue = cpu->id_afr0 },
1308
{ .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1309
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1310
.resetvalue = cpu->id_mmfr0 },
1311
{ .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1312
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1313
.resetvalue = cpu->id_mmfr1 },
1314
{ .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1315
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1316
.resetvalue = cpu->id_mmfr2 },
1317
{ .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1318
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1319
.resetvalue = cpu->id_mmfr3 },
1320
{ .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1321
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1322
.resetvalue = cpu->id_isar0 },
1323
{ .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1324
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1325
.resetvalue = cpu->id_isar1 },
1326
{ .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1327
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1328
.resetvalue = cpu->id_isar2 },
1329
{ .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1330
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1331
.resetvalue = cpu->id_isar3 },
1332
{ .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1333
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1334
.resetvalue = cpu->id_isar4 },
1335
{ .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1336
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1337
.resetvalue = cpu->id_isar5 },
1338
/* 6..7 are as yet unallocated and must RAZ */
1339
{ .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1340
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1342
{ .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1343
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1347
define_arm_cp_regs(cpu, v6_idregs);
1348
define_arm_cp_regs(cpu, v6_cp_reginfo);
1350
define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1352
if (arm_feature(env, ARM_FEATURE_V6K)) {
1353
define_arm_cp_regs(cpu, v6k_cp_reginfo);
1355
if (arm_feature(env, ARM_FEATURE_V7)) {
1356
/* v7 performance monitor control register: same implementor
1357
* field as main ID register, and we implement no event counters.
1359
ARMCPRegInfo pmcr = {
1360
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1361
.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1362
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1363
.readfn = pmreg_read, .writefn = pmcr_write,
1364
.raw_readfn = raw_read, .raw_writefn = raw_write,
1366
ARMCPRegInfo clidr = {
1367
.name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1368
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1370
define_one_arm_cp_reg(cpu, &pmcr);
1371
define_one_arm_cp_reg(cpu, &clidr);
1372
define_arm_cp_regs(cpu, v7_cp_reginfo);
1374
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1376
if (arm_feature(env, ARM_FEATURE_MPU)) {
1377
/* These are the MPU registers prior to PMSAv6. Any new
1378
* PMSA core later than the ARM946 will require that we
1379
* implement the PMSAv6 or PMSAv7 registers, which are
1380
* completely different.
1382
assert(!arm_feature(env, ARM_FEATURE_V6));
1383
define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1385
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1387
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1388
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1390
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1391
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1393
if (arm_feature(env, ARM_FEATURE_VAPA)) {
1394
define_arm_cp_regs(cpu, vapa_cp_reginfo);
1396
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1397
define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1399
if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1400
define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1402
if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1403
define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1405
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1406
define_arm_cp_regs(cpu, omap_cp_reginfo);
1408
if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1409
define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1411
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1412
define_arm_cp_regs(cpu, xscale_cp_reginfo);
1414
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1415
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1417
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1418
define_arm_cp_regs(cpu, lpae_cp_reginfo);
1420
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
1421
define_arm_cp_regs(cpu, trustzone_cp_reginfo);
1423
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
1424
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
1425
* be read-only (ie write causes UNDEF exception).
1428
ARMCPRegInfo id_cp_reginfo[] = {
1429
/* Note that the MIDR isn't a simple constant register because
1430
* of the TI925 behaviour where writes to another register can
1431
* cause the MIDR value to change.
1433
* Unimplemented registers in the c15 0 0 0 space default to
1434
* MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1435
* and friends override accordingly.
1438
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
1439
.access = PL1_R, .resetvalue = cpu->midr,
1440
.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
1441
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1442
.type = ARM_CP_OVERRIDE },
1444
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1445
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1447
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1448
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1450
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1451
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1452
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1454
.cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1455
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1457
.cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1458
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1460
.cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1461
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1463
.cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1464
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1466
.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1467
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1470
ARMCPRegInfo crn0_wi_reginfo = {
1471
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1472
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1473
.type = ARM_CP_NOP | ARM_CP_OVERRIDE
1475
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1476
arm_feature(env, ARM_FEATURE_STRONGARM)) {
1478
/* Register the blanket "writes ignored" value first to cover the
1479
* whole space. Then update the specific ID registers to allow write
1480
* access, so that they ignore writes rather than causing them to
1483
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1484
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1488
define_arm_cp_regs(cpu, id_cp_reginfo);
1491
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1492
define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1495
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1496
ARMCPRegInfo auxcr = {
1497
.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1498
.access = PL1_RW, .type = ARM_CP_CONST,
1499
.resetvalue = cpu->reset_auxcr
1501
define_one_arm_cp_reg(cpu, &auxcr);
1504
/* Generic registers whose values depend on the implementation */
1506
ARMCPRegInfo sctlr = {
1507
.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1508
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1509
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1510
.raw_writefn = raw_write,
1512
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1513
/* Normally we would always end the TB on an SCTLR write, but Linux
1514
* arch/arm/mach-pxa/sleep.S expects two instructions following
1515
* an MMU enable to execute from cache. Imitate this behaviour.
1517
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1519
define_one_arm_cp_reg(cpu, &sctlr);
1523
ARMCPU *cpu_arm_init(const char *cpu_model)
1529
oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1533
cpu = ARM_CPU(object_new(object_class_get_name(oc)));
1535
env->cpu_model_str = cpu_model;
1537
/* TODO this should be set centrally, once possible */
1538
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1543
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1545
CPUState *cs = CPU(cpu);
1546
CPUARMState *env = &cpu->env;
1548
if (arm_feature(env, ARM_FEATURE_NEON)) {
1549
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1550
51, "arm-neon.xml", 0);
1551
} else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1552
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1553
35, "arm-vfp3.xml", 0);
1554
} else if (arm_feature(env, ARM_FEATURE_VFP)) {
1555
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1556
19, "arm-vfp.xml", 0);
1560
/* Sort alphabetically by type name, except for "any". */
1561
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1563
ObjectClass *class_a = (ObjectClass *)a;
1564
ObjectClass *class_b = (ObjectClass *)b;
1565
const char *name_a, *name_b;
1567
name_a = object_class_get_name(class_a);
1568
name_b = object_class_get_name(class_b);
1569
if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
1571
} else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
1574
return strcmp(name_a, name_b);
1578
static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1580
ObjectClass *oc = data;
1581
CPUListState *s = user_data;
1582
const char *typename;
1585
typename = object_class_get_name(oc);
1586
name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
1587
(*s->cpu_fprintf)(s->file, " %s\n",
1592
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1596
.cpu_fprintf = cpu_fprintf,
1600
list = object_class_get_list(TYPE_ARM_CPU, false);
1601
list = g_slist_sort(list, arm_cpu_list_compare);
1602
(*cpu_fprintf)(f, "Available CPUs:\n");
1603
g_slist_foreach(list, arm_cpu_list_entry, &s);
1607
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1608
const ARMCPRegInfo *r, void *opaque)
1610
/* Define implementations of coprocessor registers.
1611
* We store these in a hashtable because typically
1612
* there are less than 150 registers in a space which
1613
* is 16*16*16*8*8 = 262144 in size.
1614
* Wildcarding is supported for the crm, opc1 and opc2 fields.
1615
* If a register is defined twice then the second definition is
1616
* used, so this can be used to define some generic registers and
1617
* then override them with implementation specific variations.
1618
* At least one of the original and the second definition should
1619
* include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1620
* against accidental use.
1622
int crm, opc1, opc2;
1623
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1624
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1625
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1626
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1627
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1628
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1629
/* 64 bit registers have only CRm and Opc1 fields */
1630
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1631
/* Check that the register definition has enough info to handle
1632
* reads and writes if they are permitted.
1634
if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1635
if (r->access & PL3_R) {
1636
assert(r->fieldoffset || r->readfn);
1638
if (r->access & PL3_W) {
1639
assert(r->fieldoffset || r->writefn);
1642
/* Bad type field probably means missing sentinel at end of reg list */
1643
assert(cptype_valid(r->type));
1644
for (crm = crmmin; crm <= crmmax; crm++) {
1645
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1646
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1647
uint32_t *key = g_new(uint32_t, 1);
1648
ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1649
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1650
*key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1652
r2->opaque = opaque;
1654
/* Make sure reginfo passed to helpers for wildcarded regs
1655
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1660
/* By convention, for wildcarded registers only the first
1661
* entry is used for migration; the others are marked as
1662
* NO_MIGRATE so we don't try to transfer the register
1663
* multiple times. Special registers (ie NOP/WFI) are
1666
if ((r->type & ARM_CP_SPECIAL) ||
1667
((r->crm == CP_ANY) && crm != 0) ||
1668
((r->opc1 == CP_ANY) && opc1 != 0) ||
1669
((r->opc2 == CP_ANY) && opc2 != 0)) {
1670
r2->type |= ARM_CP_NO_MIGRATE;
1673
/* Overriding of an existing definition must be explicitly
1676
if (!(r->type & ARM_CP_OVERRIDE)) {
1677
ARMCPRegInfo *oldreg;
1678
oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1679
if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1680
fprintf(stderr, "Register redefined: cp=%d %d bit "
1681
"crn=%d crm=%d opc1=%d opc2=%d, "
1682
"was %s, now %s\n", r2->cp, 32 + 32 * is64,
1683
r2->crn, r2->crm, r2->opc1, r2->opc2,
1684
oldreg->name, r2->name);
1685
g_assert_not_reached();
1688
g_hash_table_insert(cpu->cp_regs, key, r2);
1694
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1695
const ARMCPRegInfo *regs, void *opaque)
1697
/* Define a whole list of registers */
1698
const ARMCPRegInfo *r;
1699
for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1700
define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1704
const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1706
return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1709
int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1712
/* Helper coprocessor write function for write-ignore registers */
1716
int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1718
/* Helper coprocessor write function for read-as-zero registers */
1723
static int bad_mode_switch(CPUARMState *env, int mode)
1725
/* Return true if it is not valid for us to switch to
1726
* this CPU mode (ie all the UNPREDICTABLE cases in
1727
* the ARM ARM CPSRWriteByInstr pseudocode).
1730
case ARM_CPU_MODE_USR:
1731
case ARM_CPU_MODE_SYS:
1732
case ARM_CPU_MODE_SVC:
1733
case ARM_CPU_MODE_ABT:
1734
case ARM_CPU_MODE_UND:
1735
case ARM_CPU_MODE_IRQ:
1736
case ARM_CPU_MODE_FIQ:
1743
uint32_t cpsr_read(CPUARMState *env)
1746
ZF = (env->ZF == 0);
1747
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
1748
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1749
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1750
| ((env->condexec_bits & 0xfc) << 8)
1754
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1756
if (mask & CPSR_NZCV) {
1757
env->ZF = (~val) & CPSR_Z;
1759
env->CF = (val >> 29) & 1;
1760
env->VF = (val << 3) & 0x80000000;
1763
env->QF = ((val & CPSR_Q) != 0);
1765
env->thumb = ((val & CPSR_T) != 0);
1766
if (mask & CPSR_IT_0_1) {
1767
env->condexec_bits &= ~3;
1768
env->condexec_bits |= (val >> 25) & 3;
1770
if (mask & CPSR_IT_2_7) {
1771
env->condexec_bits &= 3;
1772
env->condexec_bits |= (val >> 8) & 0xfc;
1774
if (mask & CPSR_GE) {
1775
env->GE = (val >> 16) & 0xf;
1778
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
1779
if (bad_mode_switch(env, val & CPSR_M)) {
1780
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1781
* We choose to ignore the attempt and leave the CPSR M field
1786
switch_mode(env, val & CPSR_M);
1789
mask &= ~CACHED_CPSR_BITS;
1790
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1793
/* Sign/zero extend */
1794
uint32_t HELPER(sxtb16)(uint32_t x)
1797
res = (uint16_t)(int8_t)x;
1798
res |= (uint32_t)(int8_t)(x >> 16) << 16;
1802
uint32_t HELPER(uxtb16)(uint32_t x)
1805
res = (uint16_t)(uint8_t)x;
1806
res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1810
uint32_t HELPER(clz)(uint32_t x)
1815
int32_t HELPER(sdiv)(int32_t num, int32_t den)
1819
if (num == INT_MIN && den == -1)
1824
uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1831
uint32_t HELPER(rbit)(uint32_t x)
1833
x = ((x & 0xff000000) >> 24)
1834
| ((x & 0x00ff0000) >> 8)
1835
| ((x & 0x0000ff00) << 8)
1836
| ((x & 0x000000ff) << 24);
1837
x = ((x & 0xf0f0f0f0) >> 4)
1838
| ((x & 0x0f0f0f0f) << 4);
1839
x = ((x & 0x88888888) >> 3)
1840
| ((x & 0x44444444) >> 1)
1841
| ((x & 0x22222222) << 1)
1842
| ((x & 0x11111111) << 3);
1846
#if defined(CONFIG_USER_ONLY)
1848
void arm_cpu_do_interrupt(CPUState *cs)
1850
ARMCPU *cpu = ARM_CPU(cs);
1851
CPUARMState *env = &cpu->env;
1853
env->exception_index = -1;
1856
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
1860
env->exception_index = EXCP_PREFETCH_ABORT;
1861
env->cp15.c6_insn = address;
1863
env->exception_index = EXCP_DATA_ABORT;
1864
env->cp15.c6_data = address;
1869
/* These should probably raise undefined insn exceptions. */
1870
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
1872
cpu_abort(env, "v7m_mrs %d\n", reg);
1875
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
1877
cpu_abort(env, "v7m_mrs %d\n", reg);
1881
void switch_mode(CPUARMState *env, int mode)
1883
if (mode != ARM_CPU_MODE_USR)
1884
cpu_abort(env, "Tried to switch out of user mode\n");
1887
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
1889
cpu_abort(env, "banked r13 write\n");
1892
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
1894
cpu_abort(env, "banked r13 read\n");
1900
/* Map CPU modes onto saved register banks. */
1901
int bank_number(int mode)
1904
case ARM_CPU_MODE_USR:
1905
case ARM_CPU_MODE_SYS:
1907
case ARM_CPU_MODE_SVC:
1909
case ARM_CPU_MODE_ABT:
1911
case ARM_CPU_MODE_UND:
1913
case ARM_CPU_MODE_IRQ:
1915
case ARM_CPU_MODE_FIQ:
1917
case ARM_CPU_MODE_SMC:
1920
hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
1923
void switch_mode(CPUARMState *env, int mode)
1928
old_mode = env->uncached_cpsr & CPSR_M;
1929
if (mode == old_mode)
1932
if (old_mode == ARM_CPU_MODE_FIQ) {
1933
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
1934
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
1935
} else if (mode == ARM_CPU_MODE_FIQ) {
1936
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
1937
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
1940
i = bank_number(old_mode);
1941
env->banked_r13[i] = env->regs[13];
1942
env->banked_r14[i] = env->regs[14];
1943
env->banked_spsr[i] = env->spsr;
1945
i = bank_number(mode);
1946
env->regs[13] = env->banked_r13[i];
1947
env->regs[14] = env->banked_r14[i];
1948
env->spsr = env->banked_spsr[i];
1951
static void v7m_push(CPUARMState *env, uint32_t val)
1954
stl_phys(env->regs[13], val);
1957
static uint32_t v7m_pop(CPUARMState *env)
1960
val = ldl_phys(env->regs[13]);
1965
/* Switch to V7M main or process stack pointer. */
1966
static void switch_v7m_sp(CPUARMState *env, int process)
1969
if (env->v7m.current_sp != process) {
1970
tmp = env->v7m.other_sp;
1971
env->v7m.other_sp = env->regs[13];
1972
env->regs[13] = tmp;
1973
env->v7m.current_sp = process;
1977
static void do_v7m_exception_exit(CPUARMState *env)
1982
type = env->regs[15];
1983
if (env->v7m.exception != 0)
1984
armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
1986
/* Switch to the target stack. */
1987
switch_v7m_sp(env, (type & 4) != 0);
1988
/* Pop registers. */
1989
env->regs[0] = v7m_pop(env);
1990
env->regs[1] = v7m_pop(env);
1991
env->regs[2] = v7m_pop(env);
1992
env->regs[3] = v7m_pop(env);
1993
env->regs[12] = v7m_pop(env);
1994
env->regs[14] = v7m_pop(env);
1995
env->regs[15] = v7m_pop(env);
1996
xpsr = v7m_pop(env);
1997
xpsr_write(env, xpsr, 0xfffffdff);
1998
/* Undo stack alignment. */
2001
/* ??? The exception return type specifies Thread/Handler mode. However
2002
this is also implied by the xPSR value. Not sure what to do
2003
if there is a mismatch. */
2004
/* ??? Likewise for mismatches between the CONTROL register and the stack
2008
void arm_v7m_cpu_do_interrupt(CPUState *cs)
2010
ARMCPU *cpu = ARM_CPU(cs);
2011
CPUARMState *env = &cpu->env;
2012
uint32_t xpsr = xpsr_read(env);
2017
if (env->v7m.current_sp)
2019
if (env->v7m.exception == 0)
2022
/* For exceptions we just mark as pending on the NVIC, and let that
2024
/* TODO: Need to escalate if the current priority is higher than the
2025
one we're raising. */
2026
switch (env->exception_index) {
2028
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2031
/* The PC already points to the next instruction. */
2032
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2034
case EXCP_PREFETCH_ABORT:
2035
case EXCP_DATA_ABORT:
2036
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2039
if (semihosting_enabled) {
2041
nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2044
env->regs[0] = do_arm_semihosting(env);
2048
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2051
env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2053
case EXCP_EXCEPTION_EXIT:
2054
do_v7m_exception_exit(env);
2057
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2058
return; /* Never happens. Keep compiler happy. */
2061
/* Align stack pointer. */
2062
/* ??? Should only do this if Configuration Control Register
2063
STACKALIGN bit is set. */
2064
if (env->regs[13] & 4) {
2068
/* Switch to the handler mode. */
2069
v7m_push(env, xpsr);
2070
v7m_push(env, env->regs[15]);
2071
v7m_push(env, env->regs[14]);
2072
v7m_push(env, env->regs[12]);
2073
v7m_push(env, env->regs[3]);
2074
v7m_push(env, env->regs[2]);
2075
v7m_push(env, env->regs[1]);
2076
v7m_push(env, env->regs[0]);
2077
switch_v7m_sp(env, 0);
2079
env->condexec_bits = 0;
2081
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2082
env->regs[15] = addr & 0xfffffffe;
2083
env->thumb = addr & 1;
2086
/* Handle a CPU exception. */
2087
void arm_cpu_do_interrupt(CPUState *cs)
2089
ARMCPU *cpu = ARM_CPU(cs);
2090
CPUARMState *env = &cpu->env;
2098
/* TODO: Vectored interrupt controller. */
2099
switch (env->exception_index) {
2101
new_mode = ARM_CPU_MODE_UND;
2110
if (semihosting_enabled) {
2111
/* Check for semihosting interrupt. */
2113
mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2116
mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
2119
/* Only intercept calls from privileged modes, to provide some
2120
semblance of security. */
2121
if (((mask == 0x123456 && !env->thumb)
2122
|| (mask == 0xab && env->thumb))
2123
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2124
env->regs[0] = do_arm_semihosting(env);
2128
new_mode = ARM_CPU_MODE_SVC;
2131
/* The PC already points to the next instruction. */
2135
/* See if this is a semihosting syscall. */
2136
if (env->thumb && semihosting_enabled) {
2137
mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2139
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2141
env->regs[0] = do_arm_semihosting(env);
2145
env->cp15.c5_insn = 2;
2146
/* Fall through to prefetch abort. */
2147
case EXCP_PREFETCH_ABORT:
2148
new_mode = ARM_CPU_MODE_ABT;
2150
mask = CPSR_A | CPSR_I;
2153
case EXCP_DATA_ABORT:
2154
new_mode = ARM_CPU_MODE_ABT;
2156
mask = CPSR_A | CPSR_I;
2160
new_mode = ARM_CPU_MODE_IRQ;
2162
/* Disable IRQ and imprecise data aborts. */
2163
mask = CPSR_A | CPSR_I;
2167
new_mode = ARM_CPU_MODE_FIQ;
2169
/* Disable FIQ, IRQ and imprecise data aborts. */
2170
mask = CPSR_A | CPSR_I | CPSR_F;
2174
if (semihosting_enabled) {
2175
cpu_abort(env, "SMC handling under semihosting not implemented\n");
2178
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
2179
env->cp15.c1_scr &= ~1;
2181
offset = env->thumb ? 2 : 0;
2182
new_mode = ARM_CPU_MODE_SMC;
2184
mask = CPSR_A | CPSR_I | CPSR_F;
2187
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2188
return; /* Never happens. Keep compiler happy. */
2190
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
2191
if (new_mode == ARM_CPU_MODE_SMC ||
2192
(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
2193
addr += env->cp15.c12_mvbar;
2195
if (env->cp15.c1_sys & (1 << 13)) {
2198
addr += env->cp15.c12_vbar;
2203
if (env->cp15.c1_sys & (1 << 13)) {
2207
switch_mode (env, new_mode);
2208
env->spsr = cpsr_read(env);
2209
/* Clear IT bits. */
2210
env->condexec_bits = 0;
2211
/* Switch to the new mode, and to the correct instruction set. */
2212
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
2213
env->uncached_cpsr |= mask;
2214
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2215
* and we should just guard the thumb mode on V4 */
2216
if (arm_feature(env, ARM_FEATURE_V4T)) {
2217
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2219
env->regs[14] = env->regs[15] + offset;
2220
env->regs[15] = addr;
2221
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
2224
/* Check section/page access permissions.
2225
Returns the page protection flags, or zero if the access is not
2227
static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
2228
int access_type, int is_user)
2232
if (domain_prot == 3) {
2233
return PAGE_READ | PAGE_WRITE;
2236
if (access_type == 1)
2239
prot_ro = PAGE_READ;
2243
if (access_type == 1)
2245
switch ((env->cp15.c1_sys >> 8) & 3) {
2247
return is_user ? 0 : PAGE_READ;
2254
return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2259
return PAGE_READ | PAGE_WRITE;
2261
return PAGE_READ | PAGE_WRITE;
2262
case 4: /* Reserved. */
2265
return is_user ? 0 : prot_ro;
2269
if (!arm_feature (env, ARM_FEATURE_V6K))
2277
static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
2281
if (address & env->cp15.c2_mask)
2282
table = env->cp15.c2_base1 & 0xffffc000;
2284
table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2286
table |= (address >> 18) & 0x3ffc;
2290
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
2291
int is_user, hwaddr *phys_ptr,
2292
int *prot, target_ulong *page_size)
2303
/* Pagetable walk. */
2304
/* Lookup l1 descriptor. */
2305
table = get_level1_table_address(env, address);
2306
desc = ldl_phys(table);
2308
domain = (desc >> 5) & 0x0f;
2309
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2311
/* Section translation fault. */
2315
if (domain_prot == 0 || domain_prot == 2) {
2317
code = 9; /* Section domain fault. */
2319
code = 11; /* Page domain fault. */
2324
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2325
ap = (desc >> 10) & 3;
2327
*page_size = 1024 * 1024;
2329
/* Lookup l2 entry. */
2331
/* Coarse pagetable. */
2332
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2334
/* Fine pagetable. */
2335
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2337
desc = ldl_phys(table);
2339
case 0: /* Page translation fault. */
2342
case 1: /* 64k page. */
2343
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2344
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2345
*page_size = 0x10000;
2347
case 2: /* 4k page. */
2348
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2349
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2350
*page_size = 0x1000;
2352
case 3: /* 1k page. */
2354
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2355
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2357
/* Page translation fault. */
2362
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2364
ap = (desc >> 4) & 3;
2368
/* Never happens, but compiler isn't smart enough to tell. */
2373
*prot = check_ap(env, ap, domain_prot, access_type, is_user);
2375
/* Access permission fault. */
2379
*phys_ptr = phys_addr;
2382
return code | (domain << 4);
2385
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2386
int is_user, hwaddr *phys_ptr,
2387
int *prot, target_ulong *page_size)
2400
/* Pagetable walk. */
2401
/* Lookup l1 descriptor. */
2402
table = get_level1_table_address(env, address);
2403
desc = ldl_phys(table);
2405
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2406
/* Section translation fault, or attempt to use the encoding
2407
* which is Reserved on implementations without PXN.
2412
if ((type == 1) || !(desc & (1 << 18))) {
2413
/* Page or Section. */
2414
domain = (desc >> 5) & 0x0f;
2416
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2417
if (domain_prot == 0 || domain_prot == 2) {
2419
code = 9; /* Section domain fault. */
2421
code = 11; /* Page domain fault. */
2426
if (desc & (1 << 18)) {
2428
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2429
*page_size = 0x1000000;
2432
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2433
*page_size = 0x100000;
2435
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2436
xn = desc & (1 << 4);
2440
if (arm_feature(env, ARM_FEATURE_PXN)) {
2441
pxn = (desc >> 2) & 1;
2443
/* Lookup l2 entry. */
2444
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2445
desc = ldl_phys(table);
2446
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2448
case 0: /* Page translation fault. */
2451
case 1: /* 64k page. */
2452
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2453
xn = desc & (1 << 15);
2454
*page_size = 0x10000;
2456
case 2: case 3: /* 4k page. */
2457
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2459
*page_size = 0x1000;
2462
/* Never happens, but compiler isn't smart enough to tell. */
2467
if (domain_prot == 3) {
2468
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2470
if (pxn && !is_user) {
2473
if (xn && access_type == 2)
2476
/* The simplified model uses AP[0] as an access control bit. */
2477
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2478
/* Access flag fault. */
2479
code = (code == 15) ? 6 : 3;
2482
*prot = check_ap(env, ap, domain_prot, access_type, is_user);
2484
/* Access permission fault. */
2491
*phys_ptr = phys_addr;
2494
return code | (domain << 4);
2497
/* Fault type for long-descriptor MMU fault reporting; this corresponds
2498
* to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2501
translation_fault = 1,
2503
permission_fault = 3,
2506
static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2507
int access_type, int is_user,
2508
hwaddr *phys_ptr, int *prot,
2509
target_ulong *page_size_ptr)
2511
/* Read an LPAE long-descriptor translation table. */
2512
MMUFaultType fault_type = translation_fault;
2520
uint32_t tableattrs;
2521
target_ulong page_size;
2524
/* Determine whether this address is in the region controlled by
2525
* TTBR0 or TTBR1 (or if it is in neither region and should fault).
2526
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
2527
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2529
uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2530
uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2531
if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2532
/* there is a ttbr0 region and we are in it (high bits all zero) */
2534
} else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2535
/* there is a ttbr1 region and we are in it (high bits all one) */
2538
/* ttbr0 region is "everything not in the ttbr1 region" */
2541
/* ttbr1 region is "everything not in the ttbr0 region" */
2544
/* in the gap between the two regions, this is a Translation fault */
2545
fault_type = translation_fault;
2549
/* Note that QEMU ignores shareability and cacheability attributes,
2550
* so we don't need to do anything with the SH, ORGN, IRGN fields
2551
* in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2552
* ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2553
* implement any ASID-like capability so we can ignore it (instead
2554
* we will always flush the TLB any time the ASID is changed).
2556
if (ttbr_select == 0) {
2557
ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2558
epd = extract32(env->cp15.c2_control, 7, 1);
2561
ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2562
epd = extract32(env->cp15.c2_control, 23, 1);
2567
/* Translation table walk disabled => Translation fault on TLB miss */
2571
/* If the region is small enough we will skip straight to a 2nd level
2572
* lookup. This affects the number of bits of the address used in
2573
* combination with the TTBR to find the first descriptor. ('n' here
2574
* matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2575
* from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2584
/* Clear the vaddr bits which aren't part of the within-region address,
2585
* so that we don't have to special case things when calculating the
2586
* first descriptor address.
2588
address &= (0xffffffffU >> tsz);
2590
/* Now we can extract the actual base address from the TTBR */
2591
descaddr = extract64(ttbr, 0, 40);
2592
descaddr &= ~((1ULL << n) - 1);
2596
uint64_t descriptor;
2598
descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2599
descriptor = ldq_phys(descaddr);
2600
if (!(descriptor & 1) ||
2601
(!(descriptor & 2) && (level == 3))) {
2602
/* Invalid, or the Reserved level 3 encoding */
2605
descaddr = descriptor & 0xfffffff000ULL;
2607
if ((descriptor & 2) && (level < 3)) {
2608
/* Table entry. The top five bits are attributes which may
2609
* propagate down through lower levels of the table (and
2610
* which are all arranged so that 0 means "no effect", so
2611
* we can gather them up by ORing in the bits at each level).
2613
tableattrs |= extract64(descriptor, 59, 5);
2617
/* Block entry at level 1 or 2, or page entry at level 3.
2618
* These are basically the same thing, although the number
2619
* of bits we pull in from the vaddr varies.
2621
page_size = (1 << (39 - (9 * level)));
2622
descaddr |= (address & (page_size - 1));
2623
/* Extract attributes from the descriptor and merge with table attrs */
2624
attrs = extract64(descriptor, 2, 10)
2625
| (extract64(descriptor, 52, 12) << 10);
2626
attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2627
attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2628
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2629
* means "force PL1 access only", which means forcing AP[1] to 0.
2631
if (extract32(tableattrs, 2, 1)) {
2634
/* Since we're always in the Non-secure state, NSTable is ignored. */
2637
/* Here descaddr is the final physical address, and attributes
2640
fault_type = access_fault;
2641
if ((attrs & (1 << 8)) == 0) {
2645
fault_type = permission_fault;
2646
if (is_user && !(attrs & (1 << 4))) {
2647
/* Unprivileged access not enabled */
2650
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2651
if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2653
if (access_type == 2) {
2656
*prot &= ~PAGE_EXEC;
2658
if (attrs & (1 << 5)) {
2659
/* Write access forbidden */
2660
if (access_type == 1) {
2663
*prot &= ~PAGE_WRITE;
2666
*phys_ptr = descaddr;
2667
*page_size_ptr = page_size;
2671
/* Long-descriptor format IFSR/DFSR value */
2672
return (1 << 9) | (fault_type << 2) | level;
2675
static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2676
int access_type, int is_user,
2677
hwaddr *phys_ptr, int *prot)
2683
*phys_ptr = address;
2684
for (n = 7; n >= 0; n--) {
2685
base = env->cp15.c6_region[n];
2686
if ((base & 1) == 0)
2688
mask = 1 << ((base >> 1) & 0x1f);
2689
/* Keep this shift separate from the above to avoid an
2690
(undefined) << 32. */
2691
mask = (mask << 1) - 1;
2692
if (((base ^ address) & ~mask) == 0)
2698
if (access_type == 2) {
2699
mask = env->cp15.c5_insn;
2701
mask = env->cp15.c5_data;
2703
mask = (mask >> (n * 4)) & 0xf;
2710
*prot = PAGE_READ | PAGE_WRITE;
2715
*prot |= PAGE_WRITE;
2718
*prot = PAGE_READ | PAGE_WRITE;
2729
/* Bad permission. */
2736
/* get_phys_addr - get the physical address for this virtual address
2738
* Find the physical address corresponding to the given virtual address,
2739
* by doing a translation table walk on MMU based systems or using the
2740
* MPU state on MPU based systems.
2742
* Returns 0 if the translation was successful. Otherwise, phys_ptr,
2743
* prot and page_size are not filled in, and the return value provides
2744
* information on why the translation aborted, in the format of a
2745
* DFSR/IFSR fault register, with the following caveats:
2746
* * we honour the short vs long DFSR format differences.
2747
* * the WnR bit is never set (the caller must do this).
2748
* * for MPU based systems we don't bother to return a full FSR format
2752
* @address: virtual address to get physical address for
2753
* @access_type: 0 for read, 1 for write, 2 for execute
2754
* @is_user: 0 for privileged access, 1 for user
2755
* @phys_ptr: set to the physical address corresponding to the virtual address
2756
* @prot: set to the permissions for the page containing phys_ptr
2757
* @page_size: set to the size of the page containing phys_ptr
2759
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
2760
int access_type, int is_user,
2761
hwaddr *phys_ptr, int *prot,
2762
target_ulong *page_size)
2764
/* Fast Context Switch Extension. */
2765
if (address < 0x02000000)
2766
address += env->cp15.c13_fcse;
2768
if ((env->cp15.c1_sys & 1) == 0) {
2769
/* MMU/MPU disabled. */
2770
*phys_ptr = address;
2771
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2772
*page_size = TARGET_PAGE_SIZE;
2774
} else if (arm_feature(env, ARM_FEATURE_MPU)) {
2775
*page_size = TARGET_PAGE_SIZE;
2776
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2778
} else if (extended_addresses_enabled(env)) {
2779
return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
2781
} else if (env->cp15.c1_sys & (1 << 23)) {
2782
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
2785
return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
2790
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
2791
int access_type, int mmu_idx)
2794
target_ulong page_size;
2798
is_user = mmu_idx == MMU_USER_IDX;
2799
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2802
/* Map a single [sub]page. */
2803
phys_addr &= ~(hwaddr)0x3ff;
2804
address &= ~(uint32_t)0x3ff;
2805
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
2809
if (access_type == 2) {
2810
env->cp15.c5_insn = ret;
2811
env->cp15.c6_insn = address;
2812
env->exception_index = EXCP_PREFETCH_ABORT;
2814
env->cp15.c5_data = ret;
2815
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2816
env->cp15.c5_data |= (1 << 11);
2817
env->cp15.c6_data = address;
2818
env->exception_index = EXCP_DATA_ABORT;
2823
hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
2825
ARMCPU *cpu = ARM_CPU(cs);
2827
target_ulong page_size;
2831
ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
2840
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2842
if ((env->uncached_cpsr & CPSR_M) == mode) {
2843
env->regs[13] = val;
2845
env->banked_r13[bank_number(mode)] = val;
2849
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2851
if ((env->uncached_cpsr & CPSR_M) == mode) {
2852
return env->regs[13];
2854
return env->banked_r13[bank_number(mode)];
2858
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2862
return xpsr_read(env) & 0xf8000000;
2864
return xpsr_read(env) & 0xf80001ff;
2866
return xpsr_read(env) & 0xff00fc00;
2868
return xpsr_read(env) & 0xff00fdff;
2870
return xpsr_read(env) & 0x000001ff;
2872
return xpsr_read(env) & 0x0700fc00;
2874
return xpsr_read(env) & 0x0700edff;
2876
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2878
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2879
case 16: /* PRIMASK */
2880
return (env->uncached_cpsr & CPSR_I) != 0;
2881
case 17: /* BASEPRI */
2882
case 18: /* BASEPRI_MAX */
2883
return env->v7m.basepri;
2884
case 19: /* FAULTMASK */
2885
return (env->uncached_cpsr & CPSR_F) != 0;
2886
case 20: /* CONTROL */
2887
return env->v7m.control;
2889
/* ??? For debugging only. */
2890
cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2895
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2899
xpsr_write(env, val, 0xf8000000);
2902
xpsr_write(env, val, 0xf8000000);
2905
xpsr_write(env, val, 0xfe00fc00);
2908
xpsr_write(env, val, 0xfe00fc00);
2911
/* IPSR bits are readonly. */
2914
xpsr_write(env, val, 0x0600fc00);
2917
xpsr_write(env, val, 0x0600fc00);
2920
if (env->v7m.current_sp)
2921
env->v7m.other_sp = val;
2923
env->regs[13] = val;
2926
if (env->v7m.current_sp)
2927
env->regs[13] = val;
2929
env->v7m.other_sp = val;
2931
case 16: /* PRIMASK */
2933
env->uncached_cpsr |= CPSR_I;
2935
env->uncached_cpsr &= ~CPSR_I;
2937
case 17: /* BASEPRI */
2938
env->v7m.basepri = val & 0xff;
2940
case 18: /* BASEPRI_MAX */
2942
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2943
env->v7m.basepri = val;
2945
case 19: /* FAULTMASK */
2947
env->uncached_cpsr |= CPSR_F;
2949
env->uncached_cpsr &= ~CPSR_F;
2951
case 20: /* CONTROL */
2952
env->v7m.control = val & 3;
2953
switch_v7m_sp(env, (val & 2) != 0);
2956
/* ??? For debugging only. */
2957
cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2964
/* Note that signed overflow is undefined in C. The following routines are
2965
careful to use unsigned types where modulo arithmetic is required.
2966
Failure to do so _will_ break on newer gcc. */
2968
/* Signed saturating arithmetic. */
2970
/* Perform 16-bit signed saturating addition. */
2971
static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2976
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2985
/* Perform 8-bit signed saturating addition. */
2986
static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2991
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3000
/* Perform 16-bit signed saturating subtraction. */
3001
static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3006
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3015
/* Perform 8-bit signed saturating subtraction. */
3016
static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3021
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3030
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3031
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3032
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3033
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3036
#include "op_addsub.h"
3038
/* Unsigned saturating arithmetic. */
3039
static inline uint16_t add16_usat(uint16_t a, uint16_t b)
3048
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
3056
static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3065
static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3073
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3074
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3075
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3076
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3079
#include "op_addsub.h"
3081
/* Signed modulo arithmetic. */
3082
#define SARITH16(a, b, n, op) do { \
3084
sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3085
RESULT(sum, n, 16); \
3087
ge |= 3 << (n * 2); \
3090
#define SARITH8(a, b, n, op) do { \
3092
sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3093
RESULT(sum, n, 8); \
3099
#define ADD16(a, b, n) SARITH16(a, b, n, +)
3100
#define SUB16(a, b, n) SARITH16(a, b, n, -)
3101
#define ADD8(a, b, n) SARITH8(a, b, n, +)
3102
#define SUB8(a, b, n) SARITH8(a, b, n, -)
3106
#include "op_addsub.h"
3108
/* Unsigned modulo arithmetic. */
3109
#define ADD16(a, b, n) do { \
3111
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3112
RESULT(sum, n, 16); \
3113
if ((sum >> 16) == 1) \
3114
ge |= 3 << (n * 2); \
3117
#define ADD8(a, b, n) do { \
3119
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3120
RESULT(sum, n, 8); \
3121
if ((sum >> 8) == 1) \
3125
#define SUB16(a, b, n) do { \
3127
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3128
RESULT(sum, n, 16); \
3129
if ((sum >> 16) == 0) \
3130
ge |= 3 << (n * 2); \
3133
#define SUB8(a, b, n) do { \
3135
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3136
RESULT(sum, n, 8); \
3137
if ((sum >> 8) == 0) \
3144
#include "op_addsub.h"
3146
/* Halved signed arithmetic. */
3147
#define ADD16(a, b, n) \
3148
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3149
#define SUB16(a, b, n) \
3150
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3151
#define ADD8(a, b, n) \
3152
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3153
#define SUB8(a, b, n) \
3154
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3157
#include "op_addsub.h"
3159
/* Halved unsigned arithmetic. */
3160
#define ADD16(a, b, n) \
3161
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3162
#define SUB16(a, b, n) \
3163
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3164
#define ADD8(a, b, n) \
3165
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3166
#define SUB8(a, b, n) \
3167
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3170
#include "op_addsub.h"
3172
static inline uint8_t do_usad(uint8_t a, uint8_t b)
3180
/* Unsigned sum of absolute byte differences. */
3181
uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3184
sum = do_usad(a, b);
3185
sum += do_usad(a >> 8, b >> 8);
3186
sum += do_usad(a >> 16, b >>16);
3187
sum += do_usad(a >> 24, b >> 24);
3191
/* For ARMv6 SEL instruction. */
3192
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3205
return (a & mask) | (b & ~mask);
3208
/* VFP support. We follow the convention used for VFP instructions:
3209
Single precision routines have a "s" suffix, double precision a
3212
/* Convert host exception flags to vfp form. */
3213
static inline int vfp_exceptbits_from_host(int host_bits)
3215
int target_bits = 0;
3217
if (host_bits & float_flag_invalid)
3219
if (host_bits & float_flag_divbyzero)
3221
if (host_bits & float_flag_overflow)
3223
if (host_bits & (float_flag_underflow | float_flag_output_denormal))
3225
if (host_bits & float_flag_inexact)
3226
target_bits |= 0x10;
3227
if (host_bits & float_flag_input_denormal)
3228
target_bits |= 0x80;
3232
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
3237
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3238
| (env->vfp.vec_len << 16)
3239
| (env->vfp.vec_stride << 20);
3240
i = get_float_exception_flags(&env->vfp.fp_status);
3241
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
3242
fpscr |= vfp_exceptbits_from_host(i);
3246
uint32_t vfp_get_fpscr(CPUARMState *env)
3248
return HELPER(vfp_get_fpscr)(env);
3251
/* Convert vfp exception flags to target form. */
3252
static inline int vfp_exceptbits_to_host(int target_bits)
3256
if (target_bits & 1)
3257
host_bits |= float_flag_invalid;
3258
if (target_bits & 2)
3259
host_bits |= float_flag_divbyzero;
3260
if (target_bits & 4)
3261
host_bits |= float_flag_overflow;
3262
if (target_bits & 8)
3263
host_bits |= float_flag_underflow;
3264
if (target_bits & 0x10)
3265
host_bits |= float_flag_inexact;
3266
if (target_bits & 0x80)
3267
host_bits |= float_flag_input_denormal;
3271
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
3276
changed = env->vfp.xregs[ARM_VFP_FPSCR];
3277
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3278
env->vfp.vec_len = (val >> 16) & 7;
3279
env->vfp.vec_stride = (val >> 20) & 3;
3282
if (changed & (3 << 22)) {
3283
i = (val >> 22) & 3;
3286
i = float_round_nearest_even;
3292
i = float_round_down;
3295
i = float_round_to_zero;
3298
set_float_rounding_mode(i, &env->vfp.fp_status);
3300
if (changed & (1 << 24)) {
3301
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3302
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3304
if (changed & (1 << 25))
3305
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
3307
i = vfp_exceptbits_to_host(val);
3308
set_float_exception_flags(i, &env->vfp.fp_status);
3309
set_float_exception_flags(0, &env->vfp.standard_fp_status);
3312
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
3314
HELPER(vfp_set_fpscr)(env, val);
3317
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3319
#define VFP_BINOP(name) \
3320
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3322
float_status *fpst = fpstp; \
3323
return float32_ ## name(a, b, fpst); \
3325
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3327
float_status *fpst = fpstp; \
3328
return float64_ ## name(a, b, fpst); \
3336
float32 VFP_HELPER(neg, s)(float32 a)
3338
return float32_chs(a);
3341
float64 VFP_HELPER(neg, d)(float64 a)
3343
return float64_chs(a);
3346
float32 VFP_HELPER(abs, s)(float32 a)
3348
return float32_abs(a);
3351
float64 VFP_HELPER(abs, d)(float64 a)
3353
return float64_abs(a);
3356
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
3358
return float32_sqrt(a, &env->vfp.fp_status);
3361
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
3363
return float64_sqrt(a, &env->vfp.fp_status);
3366
/* XXX: check quiet/signaling case */
3367
#define DO_VFP_cmp(p, type) \
3368
void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3371
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3372
case 0: flags = 0x6; break; \
3373
case -1: flags = 0x8; break; \
3374
case 1: flags = 0x2; break; \
3375
default: case 2: flags = 0x3; break; \
3377
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3378
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3380
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3383
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3384
case 0: flags = 0x6; break; \
3385
case -1: flags = 0x8; break; \
3386
case 1: flags = 0x2; break; \
3387
default: case 2: flags = 0x3; break; \
3389
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3390
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3392
DO_VFP_cmp(s, float32)
3393
DO_VFP_cmp(d, float64)
3396
/* Integer to float and float to integer conversions */
3398
#define CONV_ITOF(name, fsz, sign) \
3399
float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3401
float_status *fpst = fpstp; \
3402
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3405
#define CONV_FTOI(name, fsz, sign, round) \
3406
uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3408
float_status *fpst = fpstp; \
3409
if (float##fsz##_is_any_nan(x)) { \
3410
float_raise(float_flag_invalid, fpst); \
3413
return float##fsz##_to_##sign##int32##round(x, fpst); \
3416
#define FLOAT_CONVS(name, p, fsz, sign) \
3417
CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3418
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3419
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3421
FLOAT_CONVS(si, s, 32, )
3422
FLOAT_CONVS(si, d, 64, )
3423
FLOAT_CONVS(ui, s, 32, u)
3424
FLOAT_CONVS(ui, d, 64, u)
3430
/* floating point conversion */
3431
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
3433
float64 r = float32_to_float64(x, &env->vfp.fp_status);
3434
/* ARM requires that S<->D conversion of any kind of NaN generates
3435
* a quiet NaN by forcing the most significant frac bit to 1.
3437
return float64_maybe_silence_nan(r);
3440
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
3442
float32 r = float64_to_float32(x, &env->vfp.fp_status);
3443
/* ARM requires that S<->D conversion of any kind of NaN generates
3444
* a quiet NaN by forcing the most significant frac bit to 1.
3446
return float32_maybe_silence_nan(r);
3449
/* VFP3 fixed point conversion. */
3450
#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
3451
float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3454
float_status *fpst = fpstp; \
3456
tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3457
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3459
uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3462
float_status *fpst = fpstp; \
3464
if (float##fsz##_is_any_nan(x)) { \
3465
float_raise(float_flag_invalid, fpst); \
3468
tmp = float##fsz##_scalbn(x, shift, fpst); \
3469
return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
3472
VFP_CONV_FIX(sh, d, 64, int16, )
3473
VFP_CONV_FIX(sl, d, 64, int32, )
3474
VFP_CONV_FIX(uh, d, 64, uint16, u)
3475
VFP_CONV_FIX(ul, d, 64, uint32, u)
3476
VFP_CONV_FIX(sh, s, 32, int16, )
3477
VFP_CONV_FIX(sl, s, 32, int32, )
3478
VFP_CONV_FIX(uh, s, 32, uint16, u)
3479
VFP_CONV_FIX(ul, s, 32, uint32, u)
3482
/* Half precision conversions. */
3483
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
3485
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
3486
float32 r = float16_to_float32(make_float16(a), ieee, s);
3488
return float32_maybe_silence_nan(r);
3493
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
3495
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
3496
float16 r = float32_to_float16(a, ieee, s);
3498
r = float16_maybe_silence_nan(r);
3500
return float16_val(r);
3503
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
3505
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3508
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
3510
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3513
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
3515
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3518
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
3520
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3523
#define float32_two make_float32(0x40000000)
3524
#define float32_three make_float32(0x40400000)
3525
#define float32_one_point_five make_float32(0x3fc00000)
3527
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
3529
float_status *s = &env->vfp.standard_fp_status;
3530
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3531
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
3532
if (!(float32_is_zero(a) || float32_is_zero(b))) {
3533
float_raise(float_flag_input_denormal, s);
3537
return float32_sub(float32_two, float32_mul(a, b, s), s);
3540
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
3542
float_status *s = &env->vfp.standard_fp_status;
3544
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3545
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
3546
if (!(float32_is_zero(a) || float32_is_zero(b))) {
3547
float_raise(float_flag_input_denormal, s);
3549
return float32_one_point_five;
3551
product = float32_mul(a, b, s);
3552
return float32_div(float32_sub(float32_three, product, s), float32_two, s);
3557
/* Constants 256 and 512 are used in some helpers; we avoid relying on
3558
* int->float conversions at run-time. */
3559
#define float64_256 make_float64(0x4070000000000000LL)
3560
#define float64_512 make_float64(0x4080000000000000LL)
3562
/* The algorithm that must be used to calculate the estimate
3563
* is specified by the ARM ARM.
3565
static float64 recip_estimate(float64 a, CPUARMState *env)
3567
/* These calculations mustn't set any fp exception flags,
3568
* so we use a local copy of the fp_status.
3570
float_status dummy_status = env->vfp.standard_fp_status;
3571
float_status *s = &dummy_status;
3572
/* q = (int)(a * 512.0) */
3573
float64 q = float64_mul(float64_512, a, s);
3574
int64_t q_int = float64_to_int64_round_to_zero(q, s);
3576
/* r = 1.0 / (((double)q + 0.5) / 512.0) */
3577
q = int64_to_float64(q_int, s);
3578
q = float64_add(q, float64_half, s);
3579
q = float64_div(q, float64_512, s);
3580
q = float64_div(float64_one, q, s);
3582
/* s = (int)(256.0 * r + 0.5) */
3583
q = float64_mul(q, float64_256, s);
3584
q = float64_add(q, float64_half, s);
3585
q_int = float64_to_int64_round_to_zero(q, s);
3587
/* return (double)s / 256.0 */
3588
return float64_div(int64_to_float64(q_int, s), float64_256, s);
3591
float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
3593
float_status *s = &env->vfp.standard_fp_status;
3595
uint32_t val32 = float32_val(a);
3598
int a_exp = (val32 & 0x7f800000) >> 23;
3599
int sign = val32 & 0x80000000;
3601
if (float32_is_any_nan(a)) {
3602
if (float32_is_signaling_nan(a)) {
3603
float_raise(float_flag_invalid, s);
3605
return float32_default_nan;
3606
} else if (float32_is_infinity(a)) {
3607
return float32_set_sign(float32_zero, float32_is_neg(a));
3608
} else if (float32_is_zero_or_denormal(a)) {
3609
if (!float32_is_zero(a)) {
3610
float_raise(float_flag_input_denormal, s);
3612
float_raise(float_flag_divbyzero, s);
3613
return float32_set_sign(float32_infinity, float32_is_neg(a));
3614
} else if (a_exp >= 253) {
3615
float_raise(float_flag_underflow, s);
3616
return float32_set_sign(float32_zero, float32_is_neg(a));
3619
f64 = make_float64((0x3feULL << 52)
3620
| ((int64_t)(val32 & 0x7fffff) << 29));
3622
result_exp = 253 - a_exp;
3624
f64 = recip_estimate(f64, env);
3627
| ((result_exp & 0xff) << 23)
3628
| ((float64_val(f64) >> 29) & 0x7fffff);
3629
return make_float32(val32);
3632
/* The algorithm that must be used to calculate the estimate
3633
* is specified by the ARM ARM.
3635
static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
3637
/* These calculations mustn't set any fp exception flags,
3638
* so we use a local copy of the fp_status.
3640
float_status dummy_status = env->vfp.standard_fp_status;
3641
float_status *s = &dummy_status;
3645
if (float64_lt(a, float64_half, s)) {
3646
/* range 0.25 <= a < 0.5 */
3648
/* a in units of 1/512 rounded down */
3649
/* q0 = (int)(a * 512.0); */
3650
q = float64_mul(float64_512, a, s);
3651
q_int = float64_to_int64_round_to_zero(q, s);
3653
/* reciprocal root r */
3654
/* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3655
q = int64_to_float64(q_int, s);
3656
q = float64_add(q, float64_half, s);
3657
q = float64_div(q, float64_512, s);
3658
q = float64_sqrt(q, s);
3659
q = float64_div(float64_one, q, s);
3661
/* range 0.5 <= a < 1.0 */
3663
/* a in units of 1/256 rounded down */
3664
/* q1 = (int)(a * 256.0); */
3665
q = float64_mul(float64_256, a, s);
3666
int64_t q_int = float64_to_int64_round_to_zero(q, s);
3668
/* reciprocal root r */
3669
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3670
q = int64_to_float64(q_int, s);
3671
q = float64_add(q, float64_half, s);
3672
q = float64_div(q, float64_256, s);
3673
q = float64_sqrt(q, s);
3674
q = float64_div(float64_one, q, s);
3676
/* r in units of 1/256 rounded to nearest */
3677
/* s = (int)(256.0 * r + 0.5); */
3679
q = float64_mul(q, float64_256,s );
3680
q = float64_add(q, float64_half, s);
3681
q_int = float64_to_int64_round_to_zero(q, s);
3683
/* return (double)s / 256.0;*/
3684
return float64_div(int64_to_float64(q_int, s), float64_256, s);
3687
float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
3689
float_status *s = &env->vfp.standard_fp_status;
3695
val = float32_val(a);
3697
if (float32_is_any_nan(a)) {
3698
if (float32_is_signaling_nan(a)) {
3699
float_raise(float_flag_invalid, s);
3701
return float32_default_nan;
3702
} else if (float32_is_zero_or_denormal(a)) {
3703
if (!float32_is_zero(a)) {
3704
float_raise(float_flag_input_denormal, s);
3706
float_raise(float_flag_divbyzero, s);
3707
return float32_set_sign(float32_infinity, float32_is_neg(a));
3708
} else if (float32_is_neg(a)) {
3709
float_raise(float_flag_invalid, s);
3710
return float32_default_nan;
3711
} else if (float32_is_infinity(a)) {
3712
return float32_zero;
3715
/* Normalize to a double-precision value between 0.25 and 1.0,
3716
* preserving the parity of the exponent. */
3717
if ((val & 0x800000) == 0) {
3718
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3720
| ((uint64_t)(val & 0x7fffff) << 29));
3722
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3724
| ((uint64_t)(val & 0x7fffff) << 29));
3727
result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3729
f64 = recip_sqrt_estimate(f64, env);
3731
val64 = float64_val(f64);
3733
val = ((result_exp & 0xff) << 23)
3734
| ((val64 >> 29) & 0x7fffff);
3735
return make_float32(val);
3738
uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
3742
if ((a & 0x80000000) == 0) {
3746
f64 = make_float64((0x3feULL << 52)
3747
| ((int64_t)(a & 0x7fffffff) << 21));
3749
f64 = recip_estimate (f64, env);
3751
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
3754
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
3758
if ((a & 0xc0000000) == 0) {
3762
if (a & 0x80000000) {
3763
f64 = make_float64((0x3feULL << 52)
3764
| ((uint64_t)(a & 0x7fffffff) << 21));
3765
} else { /* bits 31-30 == '01' */
3766
f64 = make_float64((0x3fdULL << 52)
3767
| ((uint64_t)(a & 0x3fffffff) << 22));
3770
f64 = recip_sqrt_estimate(f64, env);
3772
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
3775
/* VFPv4 fused multiply-accumulate */
3776
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3778
float_status *fpst = fpstp;
3779
return float32_muladd(a, b, c, 0, fpst);
3782
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3784
float_status *fpst = fpstp;
3785
return float64_muladd(a, b, c, 0, fpst);
added
removed
.pc/arm-virt/0004-target-arm-implement-the-generic-timer/target-arm/helper.c
