275
278
uint32_t script_ram[2048];
281
#define TYPE_LSI53C895A "lsi53c895a"
283
#define LSI53C895A(obj) \
284
OBJECT_CHECK(LSIState, (obj), TYPE_LSI53C895A)
278
286
static inline int lsi_irq_on_rsl(LSIState *s)
280
288
return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE);
424
433
level, s->dstat, s->sist1, s->sist0);
425
434
last_level = level;
427
qemu_set_irq(s->dev.irq[0], level);
436
qemu_set_irq(d->irq[0], level);
429
438
if (!level && lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON)) {
430
439
DPRINTF("Handled IRQs & disconnected, looking for pending "
557
568
/* ??? Set SFBR to first data byte. */
559
pci_dma_read(&s->dev, addr, s->current->dma_buf, count);
570
pci_dma_read(pci_dev, addr, s->current->dma_buf, count);
561
pci_dma_write(&s->dev, addr, s->current->dma_buf, count);
572
pci_dma_write(pci_dev, addr, s->current->dma_buf, count);
563
574
s->current->dma_len -= count;
564
575
if (s->current->dma_len == 0) {
692
703
/* Callback to indicate that the SCSI layer has completed a command. */
693
704
static void lsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
695
LSIState *s = DO_UPCAST(LSIState, dev.qdev, req->bus->qbus.parent);
706
LSIState *s = LSI53C895A(req->bus->qbus.parent);
698
709
out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
717
728
/* Callback to indicate that the SCSI layer has completed a transfer. */
718
729
static void lsi_transfer_data(SCSIRequest *req, uint32_t len)
720
LSIState *s = DO_UPCAST(LSIState, dev.qdev, req->bus->qbus.parent);
731
LSIState *s = LSI53C895A(req->bus->qbus.parent);
723
734
assert(req->hba_private);
805
816
status = s->status;
806
817
s->sfbr = status;
807
pci_dma_write(&s->dev, s->dnad, &status, 1);
818
pci_dma_write(PCI_DEVICE(s), s->dnad, &status, 1);
808
819
lsi_set_phase(s, PHASE_MI);
809
820
s->msg_action = 1;
810
821
lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
818
829
len = s->msg_len;
819
830
if (len > s->dbc)
821
pci_dma_write(&s->dev, s->dnad, s->msg, len);
832
pci_dma_write(PCI_DEVICE(s), s->dnad, s->msg, len);
822
833
/* Linux drivers rely on the last byte being in the SIDL. */
823
834
s->sidl = s->msg[len - 1];
824
835
s->msg_len -= len;
996
1007
#define LSI_BUF_SIZE 4096
997
1008
static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
1010
PCIDevice *d = PCI_DEVICE(s);
1000
1012
uint8_t buf[LSI_BUF_SIZE];
1002
1014
DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
1003
1015
while (count) {
1004
1016
n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count;
1005
pci_dma_read(&s->dev, src, buf, n);
1006
pci_dma_write(&s->dev, dest, buf, n);
1017
pci_dma_read(d, src, buf, n);
1018
pci_dma_write(d, dest, buf, n);
1072
1085
/* 32-bit Table indirect */
1073
1086
offset = sxt24(addr);
1074
pci_dma_read(&s->dev, s->dsa + offset, buf, 8);
1087
pci_dma_read(pci_dev, s->dsa + offset, buf, 8);
1075
1088
/* byte count is stored in bits 0:23 only */
1076
1089
s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
1077
1090
s->rbc = s->dbc;
1430
1443
n = (insn & 7);
1431
1444
reg = (insn >> 16) & 0xff;
1432
1445
if (insn & (1 << 24)) {
1433
pci_dma_read(&s->dev, addr, data, n);
1446
pci_dma_read(pci_dev, addr, data, n);
1434
1447
DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1435
1448
addr, *(int *)data);
1436
1449
for (i = 0; i < n; i++) {
1441
1454
for (i = 0; i < n; i++) {
1442
1455
data[i] = lsi_reg_readb(s, reg + i);
1444
pci_dma_write(&s->dev, addr, data, n);
1457
pci_dma_write(pci_dev, addr, data, n);
1983
1996
.minimum_version_id_old = 0,
1984
1997
.pre_save = lsi_pre_save,
1985
1998
.fields = (VMStateField []) {
1986
VMSTATE_PCI_DEVICE(dev, LSIState),
1999
VMSTATE_PCI_DEVICE(parent_obj, LSIState),
1988
2001
VMSTATE_INT32(carry, LSIState),
1989
2002
VMSTATE_INT32(status, LSIState),
2081
2094
static int lsi_scsi_init(PCIDevice *dev)
2083
LSIState *s = DO_UPCAST(LSIState, dev, dev);
2096
LSIState *s = LSI53C895A(dev);
2097
DeviceState *d = DEVICE(dev);
2084
2098
uint8_t *pci_conf;
2086
pci_conf = s->dev.config;
2101
pci_conf = dev->config;
2088
2103
/* PCI latency timer = 255 */
2089
2104
pci_conf[PCI_LATENCY_TIMER] = 0xff;
2090
2105
/* Interrupt pin A */
2091
2106
pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2093
memory_region_init_io(&s->mmio_io, &lsi_mmio_ops, s, "lsi-mmio", 0x400);
2094
memory_region_init_io(&s->ram_io, &lsi_ram_ops, s, "lsi-ram", 0x2000);
2095
memory_region_init_io(&s->io_io, &lsi_io_ops, s, "lsi-io", 256);
2108
memory_region_init_io(&s->mmio_io, OBJECT(s), &lsi_mmio_ops, s,
2110
memory_region_init_io(&s->ram_io, OBJECT(s), &lsi_ram_ops, s,
2112
memory_region_init_io(&s->io_io, OBJECT(s), &lsi_io_ops, s,
2097
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io);
2098
pci_register_bar(&s->dev, 1, 0, &s->mmio_io);
2099
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
2115
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io);
2116
pci_register_bar(dev, 1, 0, &s->mmio_io);
2117
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
2100
2118
QTAILQ_INIT(&s->queue);
2102
scsi_bus_new(&s->bus, &dev->qdev, &lsi_scsi_info, NULL);
2103
if (!dev->qdev.hotplugged) {
2104
return scsi_bus_legacy_handle_cmdline(&s->bus);
2120
scsi_bus_new(&s->bus, d, &lsi_scsi_info, NULL);
2121
if (!d->hotplugged) {
2122
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2119
2141
k->subsystem_id = 0x1000;
2120
2142
dc->reset = lsi_scsi_reset;
2121
2143
dc->vmsd = &vmstate_lsi_scsi;
2144
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2124
2147
static const TypeInfo lsi_info = {
2125
.name = "lsi53c895a",
2148
.name = TYPE_LSI53C895A,
2126
2149
.parent = TYPE_PCI_DEVICE,
2127
2150
.instance_size = sizeof(LSIState),
2128
2151
.class_init = lsi_class_init,