87
88
MemoryRegion *ram = g_new(MemoryRegion, 1);
88
89
MemoryRegion *bios = g_new(MemoryRegion, 1);
90
MemoryRegion *isa = g_new(MemoryRegion, 1);
89
91
uint32_t kernel_base, initrd_base, cmdline_base = 0;
90
92
int32_t kernel_size, initrd_size;
116
118
/* Set time-base frequency to 16.6 Mhz */
117
cpu_ppc_tb_init(env, 16600000UL);
119
cpu_ppc_tb_init(env, TBFREQ);
118
120
qemu_register_reset(ppc_heathrow_reset, cpu);
129
memory_region_init_ram(ram, "ppc_heathrow.ram", ram_size);
131
memory_region_init_ram(ram, NULL, "ppc_heathrow.ram", ram_size);
130
132
vmstate_register_ram_global(ram);
131
133
memory_region_add_subregion(sysmem, 0, ram);
133
135
/* allocate and load BIOS */
134
memory_region_init_ram(bios, "ppc_heathrow.bios", BIOS_SIZE);
136
memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE);
135
137
vmstate_register_ram_global(bios);
136
138
if (bios_name == NULL)
137
139
bios_name = PROM_FILENAME;
226
228
/* Register 2 MB of ISA IO space */
227
isa_mmio_init(0xfe000000, 0x00200000);
229
memory_region_init_alias(isa, NULL, "isa_mmio",
230
get_system_io(), 0, 0x00200000);
231
memory_region_add_subregion(sysmem, 0xfe000000, isa);
229
233
/* XXX: we register only 1 output pin for heathrow PIC */
230
234
heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
256
260
escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
257
261
serial_hds[1], ESCC_CLOCK, 4);
258
memory_region_init_alias(escc_bar, "escc-bar",
262
memory_region_init_alias(escc_bar, NULL, "escc-bar",
259
263
escc_mem, 0, memory_region_size(escc_mem));
261
265
for(i = 0; i < nb_nics; i++)
262
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
266
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
265
269
ide_drive_get(hd, MAX_IDE_BUS);
267
271
macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
268
272
dev = DEVICE(macio);
269
273
qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
270
qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE */
271
qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
274
qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
275
qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
276
qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
277
qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
272
278
macio_init(macio, pic_mem, escc_bar);
274
/* First IDE channel is a MAC IDE on the MacIO bus */
275
280
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
277
282
macio_ide_init_drives(macio_ide, hd);
279
/* Second IDE channel is a CMD646 on the PCI bus */
280
hd[0] = hd[MAX_IDE_DEVS];
281
hd[1] = hd[MAX_IDE_DEVS + 1];
282
hd[3] = hd[2] = NULL;
283
pci_cmd646_ide_init(pci_bus, hd, 0);
284
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
286
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
285
288
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
286
289
adb_bus = qdev_get_child_bus(dev, "adb.0");
331
334
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
334
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
337
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ);
339
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
340
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 266000000);
337
342
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);