161
QemuOpts *machine_opts;
162
const char *dtb_file = NULL;
164
machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
166
dtb_file = qemu_opt_get(machine_opts, "dtb");
167
toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
160
QemuOpts *machine_opts = qemu_get_machine_opts();
161
const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
162
const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
472
466
mmubooke_create_initial_mapping(env);
469
static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
476
dev = qdev_create(NULL, TYPE_OPENPIC);
477
qdev_prop_set_uint32(dev, "model", params->mpic_version);
478
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
480
qdev_init_nofail(dev);
481
s = SYS_BUS_DEVICE(dev);
484
for (i = 0; i < smp_cpus; i++) {
485
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
486
sysbus_connect_irq(s, k++, irqs[i][j]);
493
static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
500
dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
501
qdev_prop_set_uint32(dev, "model", params->mpic_version);
508
for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) {
509
if (kvm_openpic_connect_vcpu(dev, cs)) {
510
fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
519
static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr,
523
DeviceState *dev = NULL;
527
mpic = g_new(qemu_irq, 256);
530
QemuOpts *machine_opts = qemu_get_machine_opts();
531
bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
532
"kernel_irqchip", true);
533
bool irqchip_required = qemu_opt_get_bool(machine_opts,
534
"kernel_irqchip", false);
536
if (irqchip_allowed) {
537
dev = ppce500_init_mpic_kvm(params, irqs);
540
if (irqchip_required && !dev) {
541
fprintf(stderr, "%s: irqchip requested but unavailable\n",
548
dev = ppce500_init_mpic_qemu(params, irqs);
551
for (i = 0; i < 256; i++) {
552
mpic[i] = qdev_get_gpio_in(dev, i);
555
s = SYS_BUS_DEVICE(dev);
556
memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
475
562
void ppce500_init(PPCE500Params *params)
477
564
MemoryRegion *address_space_mem = get_system_memory();
487
574
target_ulong initrd_base = 0;
488
575
target_long initrd_size = 0;
489
576
target_ulong cur_base = 0;
491
578
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
492
579
qemu_irq **irqs, *mpic;
493
580
DeviceState *dev;
550
637
params->ram_size = ram_size;
552
639
/* Register Memory */
553
memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
640
memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size);
554
641
vmstate_register_ram_global(ram);
555
642
memory_region_add_subregion(address_space_mem, 0, ram);
563
650
memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
564
651
ccsr_addr_space);
567
mpic = g_new(qemu_irq, 256);
568
dev = qdev_create(NULL, "openpic");
569
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
570
qdev_prop_set_uint32(dev, "model", params->mpic_version);
571
qdev_init_nofail(dev);
572
s = SYS_BUS_DEVICE(dev);
575
for (i = 0; i < smp_cpus; i++) {
576
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
577
sysbus_connect_irq(s, k++, irqs[i][j]);
581
for (i = 0; i < 256; i++) {
582
mpic[i] = qdev_get_gpio_in(dev, i);
585
memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
653
mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
589
656
if (serial_hds[0]) {
627
694
/* Register network interfaces. */
628
695
for (i = 0; i < nb_nics; i++) {
629
pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
696
pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL);