77
77
s<2n+1> maps to the most significant half of d<n>
80
/* CPU state for each instance of a generic timer (in cp15 c14) */
81
typedef struct ARMGenericTimer {
82
uint64_t cval; /* Timer CompareValue register */
83
uint32_t ctl; /* Timer Control register */
90
/* Scale factor for generic timers, ie number of ns per tick.
91
* This gives a 62.5MHz timer.
93
#define GTIMER_SCALE 16
80
95
typedef struct CPUARMState {
81
96
/* Regs for current mode. */
148
163
uint32_t c13_tls1; /* User RW Thread register. */
149
164
uint32_t c13_tls2; /* User RO Thread register. */
150
165
uint32_t c13_tls3; /* Privileged Thread register. */
166
uint32_t c14_cntfrq; /* Counter Frequency register */
167
uint32_t c14_cntkctl; /* Timer Control register */
168
ARMGenericTimer c14_timer[NUM_GTIMERS];
151
169
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
152
170
uint32_t c15_ticonfig; /* TI925T configuration byte. */
153
171
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
398
411
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
399
412
ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
400
413
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
401
415
ARM_FEATURE_TRUSTZONE, /* TrustZone Security Extensions. */
431
445
(((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \
432
446
((crm) << 7) | ((opc1) << 3) | (opc2))
448
/* Note that these must line up with the KVM/ARM register
449
* ID field definitions (kvm.c will check this, but we
450
* can't just use the KVM defines here as the kvm headers
451
* are unavailable to non-KVM-specific files)
453
#define CP_REG_SIZE_SHIFT 52
454
#define CP_REG_SIZE_MASK 0x00f0000000000000ULL
455
#define CP_REG_SIZE_U32 0x0020000000000000ULL
456
#define CP_REG_SIZE_U64 0x0030000000000000ULL
457
#define CP_REG_ARM 0x4000000000000000ULL
459
/* Convert a full 64 bit KVM register ID to the truncated 32 bit
460
* version used as a key for the coprocessor register hashtable
462
static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
464
uint32_t cpregid = kvmid;
465
if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
466
cpregid |= (1 << 15);
471
/* Convert a truncated 32 bit hashtable key into the full
472
* 64 bit KVM register ID.
474
static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
476
uint64_t kvmid = cpregid & ~(1 << 15);
477
if (cpregid & (1 << 15)) {
478
kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
480
kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
434
485
/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
435
486
* special-behaviour cp reg and bits [15..8] indicate what behaviour
436
487
* it has. Otherwise it is a simple cp reg, where CONST indicates that
441
492
* a register definition to override a previous definition for the
442
493
* same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
443
494
* old must have the OVERRIDE bit set.
495
* NO_MIGRATE indicates that this register should be ignored for migration;
496
* (eg because any state is accessed via some other coprocessor register).
497
* IO indicates that this register does I/O and therefore its accesses
498
* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
499
* registers which implement clocks or timers require this.
445
501
#define ARM_CP_SPECIAL 1
446
502
#define ARM_CP_CONST 2
447
503
#define ARM_CP_64BIT 4
448
504
#define ARM_CP_SUPPRESS_TB_END 8
449
505
#define ARM_CP_OVERRIDE 16
506
#define ARM_CP_NO_MIGRATE 32
450
508
#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
451
509
#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
452
510
#define ARM_LAST_SPECIAL ARM_CP_WFI
453
511
/* Used only as a terminator for ARMCPRegInfo lists */
454
512
#define ARM_CP_SENTINEL 0xffff
455
513
/* Mask of only the flag bits in a type field */
456
#define ARM_CP_FLAG_MASK 0x1f
514
#define ARM_CP_FLAG_MASK 0x7f
458
516
/* Return true if cptype is a valid type field. This is used to try to
459
517
* catch errors where the sentinel has been accidentally left off the end
569
627
* by fieldoffset.
571
629
CPWriteFn *writefn;
630
/* Function for doing a "raw" read; used when we need to copy
631
* coprocessor state to the kernel for KVM or out for
632
* migration. This only needs to be provided if there is also a
633
* readfn and it makes an access permission check.
635
CPReadFn *raw_readfn;
636
/* Function for doing a "raw" write; used when we need to copy KVM
637
* kernel coprocessor state into userspace, or for inbound
638
* migration. This only needs to be provided if there is also a
639
* writefn and it makes an access permission check or masks out
640
* "unwritable" bits or has write-one-to-clear or similar behaviour.
642
CPWriteFn *raw_writefn;
572
643
/* Function for resetting the register. If NULL, then reset will be done
573
644
* by writing resetvalue to the field specified in fieldoffset. If
574
645
* fieldoffset is 0 then no reset will be done.
612
683
return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
687
* write_list_to_cpustate
690
* For each register listed in the ARMCPU cpreg_indexes list, write
691
* its value from the cpreg_values list into the ARMCPUState structure.
692
* This updates TCG's working data structures from KVM data or
693
* from incoming migration state.
695
* Returns: true if all register values were updated correctly,
696
* false if some register was unknown or could not be written.
697
* Note that we do not stop early on failure -- we will attempt
698
* writing all registers in the list.
700
bool write_list_to_cpustate(ARMCPU *cpu);
703
* write_cpustate_to_list:
706
* For each register listed in the ARMCPU cpreg_indexes list, write
707
* its value from the ARMCPUState structure into the cpreg_values list.
708
* This is used to copy info from TCG's working data structures into
709
* KVM or for outbound migration.
711
* Returns: true if all register values were read correctly,
712
* false if some register was unknown or could not be read.
713
* Note that we do not stop early on failure -- we will attempt
714
* reading all registers in the list.
716
bool write_cpustate_to_list(ARMCPU *cpu);
615
718
/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
616
719
Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
617
720
conventional cores (ie. Application or Realtime profile). */
656
759
return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
659
#if defined(CONFIG_USER_ONLY)
660
static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
663
env->regs[13] = newsp;
668
762
#include "exec/cpu-all.h"
670
764
/* Bit usage in the TB flags field: */
733
827
#include "exec/exec-all.h"
735
static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
737
env->regs[15] = tb->pc;
740
829
/* Load an instruction and return it in the standard little-endian order */
741
830
static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,