29
29
/* predefined ops */
30
DEF(end, 0, 0, 0, 0) /* must be kept first */
35
DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
37
DEF(discard, 1, 0, 0, 0)
39
DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
40
DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
30
DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
31
DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
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DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
33
DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
34
DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)
36
/* variable number of parameters */
37
DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)
39
DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
40
DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
42
/* variable number of parameters */
43
DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER)
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45
DEF(br, 0, 0, 1, TCG_OPF_BB_END)
43
#define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
47
#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
44
48
#if TCG_TARGET_REG_BITS == 32
45
49
# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
66
70
DEF(mul_i32, 1, 2, 0, 0)
67
71
DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
68
72
DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
69
DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
70
DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
73
DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
74
DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
71
75
DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
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76
DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
73
77
DEF(and_i32, 1, 2, 0, 0)
126
130
DEF(mul_i64, 1, 2, 0, IMPL64)
127
131
DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
128
132
DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
129
DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
130
DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
133
DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
134
DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
131
135
DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
132
136
DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
133
137
DEF(and_i64, 1, 2, 0, IMPL64)
167
171
/* QEMU specific */
168
172
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
169
DEF(debug_insn_start, 0, 0, 2, 0)
173
DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
171
DEF(debug_insn_start, 0, 0, 1, 0)
175
DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
173
177
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
174
178
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)