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/* XXX SCSI and ethernet should have different read-only bit masks */
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#define DMA_CSR_RO_MASK 0xfe000007
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#define TYPE_SPARC32_DMA "sparc32_dma"
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#define SPARC32_DMA(obj) OBJECT_CHECK(DMAState, (obj), TYPE_SPARC32_DMA)
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typedef struct DMAState DMAState;
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t dmaregs[DMA_REGS];
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static void dma_reset(DeviceState *d)
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DMAState *s = container_of(d, DMAState, busdev.qdev);
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DMAState *s = SPARC32_DMA(d);
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memset(s->dmaregs, 0, DMA_SIZE);
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s->dmaregs[0] = DMA_VER;
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static int sparc32_dma_init1(SysBusDevice *dev)
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static int sparc32_dma_init1(SysBusDevice *sbd)
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DMAState *s = FROM_SYSBUS(DMAState, dev);
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DeviceState *dev = DEVICE(sbd);
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DMAState *s = SPARC32_DMA(dev);
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(sbd, &s->irq);
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reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
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memory_region_init_io(&s->iomem, &dma_mem_ops, s, "dma", reg_size);
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sysbus_init_mmio(dev, &s->iomem);
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memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
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sysbus_init_mmio(sbd, &s->iomem);
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qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
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qdev_init_gpio_in(dev, dma_set_irq, 1);
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qdev_init_gpio_out(dev, s->gpio, 2);
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static const TypeInfo sparc32_dma_info = {
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.name = "sparc32_dma",
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.name = TYPE_SPARC32_DMA,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(DMAState),
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.class_init = sparc32_dma_class_init,