73
77
.minimum_version_id = 1,
74
78
.fields = (VMStateField[]) {
75
VMSTATE_UINT8(tc_int, pl080_state),
76
VMSTATE_UINT8(tc_mask, pl080_state),
77
VMSTATE_UINT8(err_int, pl080_state),
78
VMSTATE_UINT8(err_mask, pl080_state),
79
VMSTATE_UINT32(conf, pl080_state),
80
VMSTATE_UINT32(sync, pl080_state),
81
VMSTATE_UINT32(req_single, pl080_state),
82
VMSTATE_UINT32(req_burst, pl080_state),
83
VMSTATE_UINT8(tc_int, pl080_state),
84
VMSTATE_UINT8(tc_int, pl080_state),
85
VMSTATE_UINT8(tc_int, pl080_state),
86
VMSTATE_STRUCT_ARRAY(chan, pl080_state, PL080_MAX_CHANNELS,
79
VMSTATE_UINT8(tc_int, PL080State),
80
VMSTATE_UINT8(tc_mask, PL080State),
81
VMSTATE_UINT8(err_int, PL080State),
82
VMSTATE_UINT8(err_mask, PL080State),
83
VMSTATE_UINT32(conf, PL080State),
84
VMSTATE_UINT32(sync, PL080State),
85
VMSTATE_UINT32(req_single, PL080State),
86
VMSTATE_UINT32(req_burst, PL080State),
87
VMSTATE_UINT8(tc_int, PL080State),
88
VMSTATE_UINT8(tc_int, PL080State),
89
VMSTATE_UINT8(tc_int, PL080State),
90
VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
87
91
1, vmstate_pl080_channel, pl080_channel),
88
VMSTATE_INT32(running, pl080_state),
92
VMSTATE_INT32(running, PL080State),
89
93
VMSTATE_END_OF_LIST()
96
100
static const unsigned char pl081_id[] =
97
101
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
99
static void pl080_update(pl080_state *s)
103
static void pl080_update(PL080State *s)
101
105
if ((s->tc_int & s->tc_mask)
102
106
|| (s->err_int & s->err_mask))
355
359
.endianness = DEVICE_NATIVE_ENDIAN,
358
static int pl08x_init(SysBusDevice *dev, int nchannels)
360
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
362
memory_region_init_io(&s->iomem, &pl080_ops, s, "pl080", 0x1000);
363
sysbus_init_mmio(dev, &s->iomem);
364
sysbus_init_irq(dev, &s->irq);
365
s->nchannels = nchannels;
369
static int pl080_init(SysBusDevice *dev)
371
return pl08x_init(dev, 8);
374
static int pl081_init(SysBusDevice *dev)
376
return pl08x_init(dev, 2);
379
static void pl080_class_init(ObjectClass *klass, void *data)
381
DeviceClass *dc = DEVICE_CLASS(klass);
382
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
384
k->init = pl080_init;
362
static void pl080_init(Object *obj)
364
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
365
PL080State *s = PL080(obj);
367
memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
368
sysbus_init_mmio(sbd, &s->iomem);
369
sysbus_init_irq(sbd, &s->irq);
373
static void pl081_init(Object *obj)
375
PL080State *s = PL080(obj);
380
static void pl080_class_init(ObjectClass *oc, void *data)
382
DeviceClass *dc = DEVICE_CLASS(oc);
386
385
dc->vmsd = &vmstate_pl080;
389
388
static const TypeInfo pl080_info = {
391
390
.parent = TYPE_SYS_BUS_DEVICE,
392
.instance_size = sizeof(pl080_state),
391
.instance_size = sizeof(PL080State),
392
.instance_init = pl080_init,
393
393
.class_init = pl080_class_init,
396
static void pl081_class_init(ObjectClass *klass, void *data)
398
DeviceClass *dc = DEVICE_CLASS(klass);
399
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
401
k->init = pl081_init;
403
dc->vmsd = &vmstate_pl080;
406
396
static const TypeInfo pl081_info = {
408
.parent = TYPE_SYS_BUS_DEVICE,
409
.instance_size = sizeof(pl080_state),
410
.class_init = pl081_class_init,
398
.parent = TYPE_PL080,
399
.instance_init = pl081_init,
413
402
/* The PL080 and PL081 are the same except for the number of channels