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From c834c1625195e6d20458013621bbaa5f573e3ec2 Mon Sep 17 00:00:00 2001
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From: Riku Voipio <riku.voipio@nokia.com>
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Date: Mon, 18 Feb 2013 16:58:23 +0000
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Subject: [PATCH 06/69] omap.h: Add OMAP3 interrupt and DMA defines
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Add defines for OMAP3 interrupt and DMA to omap.h
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include/hw/arm/omap.h | 188 ++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 188 insertions(+)
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diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
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index 188cda8..a24ac55 100644
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--- a/include/hw/arm/omap.h
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+++ b/include/hw/arm/omap.h
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# define OMAP2_L3_BASE 0x68000000
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# define OMAP2_Q2_BASE 0x80000000
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# define OMAP2_Q3_BASE 0xc0000000
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+# define OMAP3_Q1_BASE 0x40000000
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+# define OMAP3_L4_BASE 0x48000000
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+# define OMAP3_SRAM_BASE 0x40200000
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+# define OMAP3_L3_BASE 0x68000000
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+# define OMAP3_Q2_BASE 0x80000000
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+# define OMAP3_Q3_BASE 0xc0000000
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# define OMAP_MPUI_BASE 0xe1000000
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# define OMAP730_SRAM_SIZE 0x00032000
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# define OMAP1611_SRAM_SIZE 0x0003e800
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# define OMAP242X_SRAM_SIZE 0x000a0000
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# define OMAP243X_SRAM_SIZE 0x00010000
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+# define OMAP3XXX_SRAM_SIZE 0x00010000
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+# define OMAP3XXX_BOOTROM_SIZE 0x00008000
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# define OMAP_CS0_SIZE 0x04000000
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# define OMAP_CS1_SIZE 0x04000000
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# define OMAP_CS2_SIZE 0x04000000
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@@ -425,6 +433,106 @@ void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
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# define OMAP_INT_243X_CARKIT 94
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# define OMAP_INT_34XX_GPTIMER12 95
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+ * OMAP-3XXX common IRQ numbers
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+#define OMAP_INT_3XXX_EMUINT 0 /* MPU emulation */
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+#define OMAP_INT_3XXX_COMMTX 1 /* MPU emulation */
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+#define OMAP_INT_3XXX_COMMRX 2 /* MPU emulation */
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+#define OMAP_INT_3XXX_BENCH 3 /* MPU emulation */
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+#define OMAP_INT_3XXX_MCBSP2_ST_IRQ 4 /* Sidetone MCBSP2 overflow */
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+#define OMAP_INT_3XXX_MCBSP3_ST_IRQ 5 /* Sidetone MCBSP3 overflow */
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+#define OMAP_INT_3XXX_SSM_ABORT_IRQ 6
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+#define OMAP_INT_3XXX_SYS_NIRQ 7 /* External source (active low) */
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+#define OMAP_INT_3XXX_D2D_FW_IRQ 8
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+#define OMAP_INT_3XXX_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
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+#define OMAP_INT_3XXX_SMX_APP_IRQ 10 /* L3 interconnect error for application */
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+#define OMAP_INT_3XXX_PRCM_MPU_IRQ 11 /* PRCM module IRQ */
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+#define OMAP_INT_3XXX_SDMA_IRQ0 12 /* System DMA request 0 */
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+#define OMAP_INT_3XXX_SDMA_IRQ1 13 /* System DMA request 1 */
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+#define OMAP_INT_3XXX_SDMA_IRQ2 14 /* System DMA request 2 */
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+#define OMAP_INT_3XXX_SDMA_IRQ3 15 /* System DMA request 3 */
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+#define OMAP_INT_3XXX_MCBSP1_IRQ 16 /* MCBSP module 1 IRQ */
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+#define OMAP_INT_3XXX_MCBSP2_IRQ 17 /* MCBSP module 2 IRQ */
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+#define OMAP_INT_3XXX_SR1_IRQ 18 /* SmartReflex 1 */
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+#define OMAP_INT_3XXX_SR2_IRQ 19 /* SmartReflex 2 */
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+#define OMAP_INT_3XXX_GPMC_IRQ 20 /* General-purpose memory controller module */
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+#define OMAP_INT_3XXX_SGX_IRQ 21 /* 2D/3D graphics module */
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+#define OMAP_INT_3XXX_MCBSP3_IRQ 22 /* MCBSP module 3 */
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+#define OMAP_INT_3XXX_MCBSP4_IRQ 23 /* MCBSP module 4 */
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+#define OMAP_INT_3XXX_CAM_IRQ0 24 /* Camera interface request 0 */
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+#define OMAP_INT_3XXX_DSS_IRQ 25 /* Display subsystem module */
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+#define OMAP_INT_3XXX_MAIL_U0_MPU 26 /* Mailbox user 0 request */
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+#define OMAP_INT_3XXX_MCBSP5_IRQ 27 /* MCBSP module 5 */
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+#define OMAP_INT_3XXX_IVA2_MMU_IRQ 28 /* IVA2 MMU */
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+#define OMAP_INT_3XXX_GPIO1_MPU_IRQ 29 /* GPIO module 1 */
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+#define OMAP_INT_3XXX_GPIO2_MPU_IRQ 30 /* GPIO module 2 */
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+#define OMAP_INT_3XXX_GPIO3_MPU_IRQ 31 /* GPIO module 3 */
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+#define OMAP_INT_3XXX_GPIO4_MPU_IRQ 32 /* GPIO module 4 */
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+#define OMAP_INT_3XXX_GPIO5_MPU_IRQ 33 /* GPIO module 5 */
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+#define OMAP_INT_3XXX_GPIO6_MPU_IRQ 34 /* GPIO module 6 */
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+#define OMAP_INT_3XXX_USIM_IRQ 35
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+#define OMAP_INT_3XXX_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
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+#define OMAP_INT_3XXX_GPT1_IRQ 37 /* General-purpose timer module 1 */
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+#define OMAP_INT_3XXX_GPT2_IRQ 38 /* General-purpose timer module 2 */
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+#define OMAP_INT_3XXX_GPT3_IRQ 39 /* General-purpose timer module 3 */
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+#define OMAP_INT_3XXX_GPT4_IRQ 40 /* General-purpose timer module 4 */
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+#define OMAP_INT_3XXX_GPT5_IRQ 41 /* General-purpose timer module 5 */
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+#define OMAP_INT_3XXX_GPT6_IRQ 42 /* General-purpose timer module 6 */
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+#define OMAP_INT_3XXX_GPT7_IRQ 43 /* General-purpose timer module 7 */
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+#define OMAP_INT_3XXX_GPT8_IRQ 44 /* General-purpose timer module 8 */
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+#define OMAP_INT_3XXX_GPT9_IRQ 45 /* General-purpose timer module 9 */
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+#define OMAP_INT_3XXX_GPT10_IRQ 46 /* General-purpose timer module 10 */
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+#define OMAP_INT_3XXX_GPT11_IRQ 47 /* General-purpose timer module 11 */
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+#define OMAP_INT_3XXX_MCSPI4_IRQ 48 /* MCSPI module 4 */
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+#define OMAP_INT_3XXX_SHA1MD52_IRQ 49
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+#define OMAP_INT_3XXX_FPKA_READY 50
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+#define OMAP_INT_3XXX_SHA1MD51_IRQ 51
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+#define OMAP_INT_3XXX_RNG_IRQ 52
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+#define OMAP_INT_3XXX_MG_IRQ 53
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+#define OMAP_INT_3XXX_MCBSP4_IRQ_TX 54 /* MCBSP module 4 transmit */
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+#define OMAP_INT_3XXX_MCBSP4_IRQ_RX 55 /* MCBSP module 4 receive */
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+#define OMAP_INT_3XXX_I2C1_IRQ 56 /* I2C module 1 */
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+#define OMAP_INT_3XXX_I2C2_IRQ 57 /* I2C module 2 */
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+#define OMAP_INT_3XXX_HDQ_IRQ 58 /* HDQ/1-Wire */
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+#define OMAP_INT_3XXX_MCBSP1_IRQ_TX 59 /* MCBSP module 1 transmit */
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+#define OMAP_INT_3XXX_MCBSP1_IRQ_RX 60 /* MCBSP module 1 receive */
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+#define OMAP_INT_3XXX_I2C3_IRQ 61 /* I2C module 3 */
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+#define OMAP_INT_3XXX_MCBSP2_IRQ_TX 62 /* MCBSP module 2 transmit */
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+#define OMAP_INT_3XXX_MCBSP2_IRQ_RX 63 /* MCBSP module 2 receive */
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+#define OMAP_INT_3XXX_FPKA_ERROR 64
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+#define OMAP_INT_3XXX_MCSPI1_IRQ 65 /* MCSPI module 1 */
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+#define OMAP_INT_3XXX_MCSPI2_IRQ 66 /* MCSPI module 2 */
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+/* IRQ67 is reserved */
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+/* IRQ68 is reserved */
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+/* IRQ69 is reserved */
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+/* IRQ70 is reserved */
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+/* IRQ71 is reserved */
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+#define OMAP_INT_3XXX_UART1_IRQ 72 /* UART module 1 */
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+#define OMAP_INT_3XXX_UART2_IRQ 73 /* UART module 2 */
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+#define OMAP_INT_3XXX_UART3_IRQ 74 /* UART module 3 (also infrared)*/
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+#define OMAP_INT_3XXX_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite1 and 2 */
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+#define OMAP_INT_3XXX_OHCI_IRQ 76 /* OHCI controller HSUSB MP Host interrupt */
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+#define OMAP_INT_3XXX_EHCI_IRQ 77 /* EHCI controller HSUSB MP Host interrupt */
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+#define OMAP_INT_3XXX_TLL_IRQ 78 /* HSUSB MP TLL interrupt */
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+/* IRQ79 is reserved */
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+#define OMAP_INT_3XXX_UART4_IRQ 80 /* UART module 4 (OMAP3630 only) */
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+#define OMAP_INT_3XXX_MCBSP5_IRQ_TX 81 /* MCBSP module 5 transmit */
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+#define OMAP_INT_3XXX_MCBSP5_IRQ_RX 82 /* MCBSP module 5 receive */
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+#define OMAP_INT_3XXX_MMC1_IRQ 83 /* MMC/SD module 1 */
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+#define OMAP_INT_3XXX_MS_IRQ 84
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+/* IRQ85 is reserved */
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+#define OMAP_INT_3XXX_MMC2_IRQ 86 /* MMC/SD module 2 */
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+#define OMAP_INT_3XXX_MPU_ICR_IRQ 87 /* MPU ICR */
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+#define OMAP_INT_3XXX_D2DFRINT 88 /* 3G coprocessor */
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+#define OMAP_INT_3XXX_MCBSP3_IRQ_TX 89 /* MCBSP module 3 transmit */
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+#define OMAP_INT_3XXX_MCBSP3_IRQ_RX 90 /* MCBSP module 3 receive */
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+#define OMAP_INT_3XXX_MCSPI3_IRQ 91 /* MCSPI module 3 */
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+#define OMAP_INT_3XXX_HSUSB_MC 92 /* High-Speed USB OTG controller */
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+#define OMAP_INT_3XXX_HSUSB_DMA 93 /* High-Speed USB OTG DMA controller */
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+#define OMAP_INT_3XXX_MMC3_IRQ 94 /* MMC/SD module 3 */
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+#define OMAP_INT_3XXX_GPT12_IRQ 95 /* General-purpose timer module 12 */
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enum omap_dma_model {
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@@ -646,6 +754,86 @@ struct omap_dma_lcd_channel_s {
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# define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
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# define OMAP24XX_DMA_EXT_DMAREQ5 64
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+ * DMA request numbers for the OMAP3
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+ * Note that the numbers have to match the values that are
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+ * written to CCRi SYNCHRO_CONTROL bits, i.e. actual line
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+ * number plus one! Zero is a reserved value (defined as
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+ * NO_DEVICE here). Other missing values are reserved.
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+#define OMAP3XXX_DMA_NO_DEVICE 0
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+#define OMAP3XXX_DMA_EXT_DMAREQ0 2
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+#define OMAP3XXX_DMA_EXT_DMAREQ1 3
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+#define OMAP3XXX_DMA_GPMC 4
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+#define OMAP3XXX_DMA_DSS_LINETRIGGER 6
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+#define OMAP3XXX_DMA_EXT_DMAREQ2 7
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+#define OMAP3XXX_DMA_SPI3_TX0 15
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+#define OMAP3XXX_DMA_SPI3_RX0 16
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+#define OMAP3XXX_DMA_MCBSP3_TX 17
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+#define OMAP3XXX_DMA_MCBSP3_RX 18
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+#define OMAP3XXX_DMA_MCBSP4_TX 19
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+#define OMAP3XXX_DMA_MCBSP4_RX 20
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+#define OMAP3XXX_DMA_MCBSP5_TX 21
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+#define OMAP3XXX_DMA_MCBSP5_RX 22
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+#define OMAP3XXX_DMA_SPI3_TX1 23
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+#define OMAP3XXX_DMA_SPI3_RX1 24
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+#define OMAP3XXX_DMA_I2C3_TX 25
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+#define OMAP3XXX_DMA_I2C3_RX 26
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+#define OMAP3XXX_DMA_I2C1_TX 27
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+#define OMAP3XXX_DMA_I2C1_RX 28
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+#define OMAP3XXX_DMA_I2C2_TX 29
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+#define OMAP3XXX_DMA_I2C2_RX 30
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+#define OMAP3XXX_DMA_MCBSP1_TX 31
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+#define OMAP3XXX_DMA_MCBSP1_RX 32
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+#define OMAP3XXX_DMA_MCBSP2_TX 33
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+#define OMAP3XXX_DMA_MCBSP2_RX 34
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+#define OMAP3XXX_DMA_SPI1_TX0 35
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+#define OMAP3XXX_DMA_SPI1_RX0 36
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+#define OMAP3XXX_DMA_SPI1_TX1 37
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+#define OMAP3XXX_DMA_SPI1_RX1 38
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+#define OMAP3XXX_DMA_SPI1_TX2 39
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+#define OMAP3XXX_DMA_SPI1_RX2 40
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+#define OMAP3XXX_DMA_SPI1_TX3 41
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+#define OMAP3XXX_DMA_SPI1_RX3 42
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+#define OMAP3XXX_DMA_SPI2_TX0 43
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+#define OMAP3XXX_DMA_SPI2_RX0 44
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+#define OMAP3XXX_DMA_SPI2_TX1 45
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+#define OMAP3XXX_DMA_SPI2_RX1 46
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+#define OMAP3XXX_DMA_MMC2_TX 47
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+#define OMAP3XXX_DMA_MMC2_RX 48
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+#define OMAP3XXX_DMA_UART1_TX 49
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+#define OMAP3XXX_DMA_UART1_RX 50
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+#define OMAP3XXX_DMA_UART2_TX 51
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+#define OMAP3XXX_DMA_UART2_RX 52
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+#define OMAP3XXX_DMA_UART3_TX 53
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+#define OMAP3XXX_DMA_UART3_RX 54
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+#define OMAP3XXX_DMA_MMC1_TX 61
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+#define OMAP3XXX_DMA_MMC1_RX 62
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+#define OMAP3XXX_DMA_MS 63
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+#define OMAP3XXX_DMA_EXT_DMAREQ3 64
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+#define OMAP3XXX_DMA_AES2_TX 65
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+#define OMAP3XXX_DMA_AES2_RX 66
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+#define OMAP3XXX_DMA_DES2_TX 67
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+#define OMAP3XXX_DMA_DES2_RX 68
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+#define OMAP3XXX_DMA_SHA1MD5_RX 69
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+#define OMAP3XXX_DMA_SPI4_TX0 70
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+#define OMAP3XXX_DMA_SPI4_RX0 71
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+#define OMAP3XXX_DMA_DSS0 72
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+#define OMAP3XXX_DMA_DSS1 73
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+#define OMAP3XXX_DMA_DSS2 74
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+#define OMAP3XXX_DMA_DSS3 75
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+#define OMAP3XXX_DMA_MMC3_TX 77
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+#define OMAP3XXX_DMA_MMC3_RX 78
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+#define OMAP3XXX_DMA_USIM_TX 79
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+#define OMAP3XXX_DMA_USIM_RX 80
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+#define OMAP3XXX_DMA_UART4_TX 81
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+#define OMAP3XXX_DMA_UART4_RX 82
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struct omap_gp_timer_s;