1107
1107
if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1108
1108
VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1109
g_assert_not_reached();
1112
1112
VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1892
1892
vmxnet_tx_pkt_reset(s->tx_pkt);
1893
1893
vmxnet_tx_pkt_uninit(s->tx_pkt);
1894
1894
vmxnet_rx_pkt_uninit(s->rx_pkt);
1895
qemu_del_net_client(qemu_get_queue(s->nic));
1895
qemu_del_nic(s->nic);
1898
1898
static void vmxnet3_net_init(VMXNET3State *s)
2074
2074
VMW_CBPRN("Starting init...");
2076
memory_region_init_io(&s->bar0, &b0_ops, s,
2076
memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2077
2077
"vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2078
2078
pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2079
2079
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2081
memory_region_init_io(&s->bar1, &b1_ops, s,
2081
memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2082
2082
"vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2083
2083
pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2084
2084
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2086
memory_region_init(&s->msix_bar, "vmxnet3-msix-bar",
2086
memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2087
2087
VMXNET3_MSIX_BAR_SIZE);
2088
2088
pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2089
2089
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2453
2453
dc->reset = vmxnet3_qdev_reset;
2454
2454
dc->vmsd = &vmstate_vmxnet3;
2455
2455
dc->props = vmxnet3_properties;
2456
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2458
2459
static const TypeInfo vmxnet3_info = {