118
118
static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
120
struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
120
AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
121
PCIDevice *pci_dev = PCI_DEVICE(d);
122
123
DPRINTF(0, "raise irq\n");
124
if (msi_enabled(&d->card)) {
125
msi_notify(&d->card, 0);
125
if (msi_enabled(pci_dev)) {
126
msi_notify(pci_dev, 0);
127
128
qemu_irq_raise(s->irq);
131
132
static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
133
struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
134
AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
135
136
DPRINTF(0, "lower irq\n");
137
if (!msi_enabled(&d->card)) {
138
if (!msi_enabled(PCI_DEVICE(d))) {
138
139
qemu_irq_lower(s->irq);
598
599
/* map cmd_fis */
599
600
uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);
600
cmd_fis = dma_memory_map(ad->hba->dma, tbl_addr, &cmd_len,
601
cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len,
601
602
DMA_DIRECTION_TO_DEVICE);
630
631
ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);
632
633
if (cmd_mapped) {
633
dma_memory_unmap(ad->hba->dma, cmd_fis, cmd_len,
634
dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,
634
635
DMA_DIRECTION_TO_DEVICE, cmd_len);
660
if (!(prdt = dma_memory_map(ad->hba->dma, prdt_addr, &prdt_len,
663
if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,
661
664
DMA_DIRECTION_TO_DEVICE))){
662
665
DPRINTF(ad->port_no, "map failed\n");
694
qemu_sglist_init(sglist, (sglist_alloc_hint - off_idx), ad->hba->dma);
697
qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx),
695
699
qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos),
696
700
le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos);
706
dma_memory_unmap(ad->hba->dma, prdt, prdt_len,
710
dma_memory_unmap(ad->hba->as, prdt, prdt_len,
707
711
DMA_DIRECTION_TO_DEVICE, prdt_len);
836
840
tbl_addr = le64_to_cpu(cmd->tbl_addr);
839
cmd_fis = dma_memory_map(s->dma, tbl_addr, &cmd_len,
843
cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,
840
844
DMA_DIRECTION_FROM_DEVICE);
966
dma_memory_unmap(s->dma, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE,
970
dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE,
969
973
if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1105
1109
static int ahci_dma_set_inactive(IDEDMA *dma)
1114
static int ahci_async_cmd_done(IDEDMA *dma)
1107
1116
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1109
DPRINTF(ad->port_no, "dma done\n");
1118
DPRINTF(ad->port_no, "async cmd done\n");
1111
1120
/* update d2h status */
1112
1121
ahci_write_fis_d2h(ad, NULL);
1141
1150
.set_unit = ahci_dma_set_unit,
1142
1151
.add_status = ahci_dma_add_status,
1143
1152
.set_inactive = ahci_dma_set_inactive,
1153
.async_cmd_done = ahci_async_cmd_done,
1144
1154
.restart_cb = ahci_dma_restart_cb,
1145
1155
.reset = ahci_dma_reset,
1148
void ahci_init(AHCIState *s, DeviceState *qdev, DMAContext *dma, int ports)
1158
void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
1150
1160
qemu_irq *irqs;
1154
1164
s->ports = ports;
1155
1165
s->dev = g_malloc0(sizeof(AHCIDevice) * ports);
1156
1166
ahci_reg_init(s);
1157
1167
/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1158
memory_region_init_io(&s->mem, &ahci_mem_ops, s, "ahci", AHCI_MEM_BAR_SIZE);
1159
memory_region_init_io(&s->idp, &ahci_idp_ops, s, "ahci-idp", 32);
1168
memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
1169
"ahci", AHCI_MEM_BAR_SIZE);
1170
memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
1161
1173
irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1292
1310
static void sysbus_ahci_reset(DeviceState *dev)
1294
SysbusAHCIState *s = DO_UPCAST(SysbusAHCIState, busdev.qdev, dev);
1312
SysbusAHCIState *s = SYSBUS_AHCI(dev);
1296
1314
ahci_reset(&s->ahci);
1299
static int sysbus_ahci_init(SysBusDevice *dev)
1317
static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
1301
SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev);
1302
ahci_init(&s->ahci, &dev->qdev, NULL, s->num_ports);
1304
sysbus_init_mmio(dev, &s->ahci.mem);
1305
sysbus_init_irq(dev, &s->ahci.irq);
1319
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1320
SysbusAHCIState *s = SYSBUS_AHCI(dev);
1322
ahci_init(&s->ahci, dev, NULL, s->num_ports);
1324
sysbus_init_mmio(sbd, &s->ahci.mem);
1325
sysbus_init_irq(sbd, &s->ahci.irq);
1309
1328
static Property sysbus_ahci_properties[] = {
1314
1333
static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
1316
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1317
1335
DeviceClass *dc = DEVICE_CLASS(klass);
1319
sbc->init = sysbus_ahci_init;
1337
dc->realize = sysbus_ahci_realize;
1320
1338
dc->vmsd = &vmstate_sysbus_ahci;
1321
1339
dc->props = sysbus_ahci_properties;
1322
1340
dc->reset = sysbus_ahci_reset;
1341
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1325
1344
static const TypeInfo sysbus_ahci_info = {
1326
.name = "sysbus-ahci",
1345
.name = TYPE_SYSBUS_AHCI,
1327
1346
.parent = TYPE_SYS_BUS_DEVICE,
1328
1347
.instance_size = sizeof(SysbusAHCIState),
1329
1348
.class_init = sysbus_ahci_class_init,